KR20250145457A - Circuit board, Method for manufacturing circuit board, and electronic component package - Google Patents

Abstract

The disclosed circuit board includes a first insulating layer portion and a second insulating layer portion laminated on the first insulating layer portion, an insulating layer having a cavity penetrating a portion of the second insulating layer portion and the first insulating layer portion, a circuit layer at least partially embedded in the second insulating layer portion, and a metal pattern layer disposed along an edge of the cavity within the second insulating layer portion, wherein the insulating layer has a first surface constituting a bottom surface of the cavity and a second surface constituting a side surface of the cavity, and the metal pattern layer includes a plurality of metal layers exposed from the insulating layer at the second surface and including different metals.

Description

Circuit board, method for manufacturing circuit board, and electronic component package

The present disclosure relates to a circuit board, a method for manufacturing a circuit board, and an electronic component package.

To reduce the thickness of a circuit board, a cavity is formed within the circuit board and various electronic components are placed within the cavity. At this time, the circuit board must have pads on its surface, exposed through the cavity, onto which electronic components can be mounted.

However, in circuit boards including such cavities, structural problems such as pad appearance quality may occur, and it is difficult to simultaneously implement stoppers and mounting pads for cavity processing on the same layer.

One aspect of the present disclosure is to provide a thin circuit board and electronic component package capable of forming a stopper layer for forming a cavity in the same layer and a pad structure exposed in the cavity.

However, the problems to be solved by the embodiments of the present invention are not limited to the problems described above and can be expanded in various ways within the scope of the technical ideas included in the present invention.

A circuit board according to an embodiment includes a first insulating layer portion and a second insulating layer portion laminated on the first insulating layer portion, an insulating layer having a cavity penetrating a portion of the second insulating layer portion and the first insulating layer portion, a circuit layer at least partially embedded in the second insulating layer portion, and a metal pattern layer disposed along an edge of the cavity within the second insulating layer portion, wherein the insulating layer has a first surface constituting a bottom surface of the cavity and a second surface constituting a side surface of the cavity, and the metal pattern layer includes a plurality of metal layers exposed from the insulating layer at the second surface and including different metals.

The above multiple metal layers may have different etch selectivities for the same material.

The metal pattern layer may be arranged in a corner region of the cavity to connect the first surface and the second surface.

The above metal pattern layer may include a first metal layer including copper, and a second metal layer disposed on the first metal layer and including nickel.

The circuit layer includes a first conductive layer disposed on the first insulating layer portion, and a second conductive layer laminated on the first conductive layer, and one surface of the second conductive layer can be disposed on substantially the same plane as one surface of the second metal layer.

The circuit layer may include a first conductive layer comprising the same material as the first metal layer.

The first surface may further include a first pad exposed from the second insulating layer portion.

The above first pad may be partially embedded in the insulating layer.

With respect to the distance in the stacking direction based on the first insulating layer portion, the surface of the first pad exposed from the second insulating layer portion may be located further away than the surface facing the first insulating layer portion of the circuit layer.

In the thickness in the above lamination direction, the thickness of the first pad may be smaller than the thickness of the circuit layer.

The circuit layer may include a first conductive layer including copper, and a second conductive layer disposed on the first conductive layer.

The above first conductive layer may include an electroless plating layer.

The above metal pattern layer may be positioned concavely inward from the second surface.

The insulating layer may further include a first pad exposed from the insulating layer on one side where the cavity is located.

A method for manufacturing a circuit board according to an embodiment comprises: forming a first stopper layer including a first metal on a first insulating layer portion; forming a second stopper layer on the first stopper layer including a second metal different from the first metal; forming a first pad on the second stopper layer; forming a second insulating layer portion by laminating the first pad on the first insulating layer portion so that the first pad is buried; forming a first cavity forming portion by removing the first insulating layer portion on the first stopper layer by an area smaller than an area of the first stopper layer; forming a second cavity forming portion by removing a portion of the first stopper layer exposed within the first cavity forming portion; and forming a cavity by removing a portion of the second stopper layer exposed within the second cavity forming portion.

Forming the second stopper layer may include forming the second stopper layer by including the second metal having a different etching selectivity from the first metal for the same material.

Forming the second cavity forming portion may include removing an exposed portion of the first stopper layer and forming the remaining first metal layer along an edge of the first cavity forming portion.

Forming the cavity may include removing an exposed portion of the second stopper layer and forming a remaining second metal layer along an edge of the second cavity forming portion.

Forming the first stopper layer may include forming the first stopper layer including copper, and forming the second stopper layer may include forming the second stopper layer including nickel.

The method may further include forming a circuit layer on the first insulating layer portion, and forming the circuit layer may include forming a first conductive layer on the first insulating layer portion, and forming a second conductive layer on the first conductive layer so as to have one surface at substantially the same level as one surface of the second stopper layer.

Forming the first conductive layer may include forming the first conductive layer by including the same material as the first stopper layer.

The method may further include forming a circuit layer on the first insulating layer portion, and forming the first pad may include forming the first pad such that a surface of the first pad exposed from the second insulating layer portion has a higher level than a surface of the circuit layer facing the first insulating layer portion.

The method may further include forming a circuit layer on the first insulating layer, and forming the first pad may include forming the first pad to have a thickness in the lamination direction that is smaller than a thickness of the circuit layer.

It may further include forming a surface treatment layer on the first pad.

The method may further include forming a circuit layer on the first insulating layer, and forming the circuit layer may include forming a first conductive layer including copper, and forming a second conductive layer on the first conductive layer.

Forming the first conductive layer may include forming an electroless plating layer.

It may further include etching the first stopper layer to form a first metal layer so as to be recessed inward from the side surface of the second insulating layer portion.

It may further include etching the second stopper layer to form a second metal layer so as to be recessed inward from the side surface of the second insulating layer portion.

The method may further include forming an insulating layer including the first insulating layer portion and the second insulating layer portion and having the cavity formed on one surface thereof, and forming a second pad on the one surface of the insulating layer so as to be exposed from the insulating layer.

An electronic component package according to an embodiment comprises a circuit board having a cavity and including a pad portion exposed from an insulating layer within the cavity, and an electronic component mounted within the cavity to be connected to the pad portion, wherein the circuit board comprises an insulating layer having the cavity, a circuit layer at least partially embedded in the insulating layer, and a metal pattern layer arranged along an edge of the cavity within the insulating layer, wherein the insulating layer has a first surface constituting a bottom surface of the cavity and a second surface constituting a side surface of the cavity, and the metal pattern layer includes a plurality of metal layers exposed from the insulating layer at the second surface and including different metals.

The above metal pattern layer may include a first metal layer including copper, and a second metal layer disposed on the first metal layer and including nickel.

According to the circuit board, the method for manufacturing the circuit board, and the electronic component package according to the embodiment, a plurality of metal layers including different metals can be used as an etching stop layer to more easily form a cavity structure and a pad structure exposed in the cavity, and a circuit board having a thin thickness can be provided, thereby making it possible to reduce the thickness of an electronic product on which the circuit board is mounted.

Fig. 1 is a cross-sectional view schematically showing the structure of a circuit board according to one embodiment.
Fig. 2 is an enlarged cross-sectional view of part A of the circuit board shown in Fig. 1.
Fig. 3 is an enlarged cross-sectional view of part B of the circuit board shown in Fig. 1.
FIGS. 4 to 16 are cross-sectional views illustrating a method for manufacturing a circuit board according to one embodiment.
Fig. 17 is a cross-sectional view schematically illustrating an electronic component package according to one embodiment.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings so that those skilled in the art can easily practice the present invention. In the drawings, parts irrelevant to the description have been omitted to clearly explain the present invention, and the same reference numerals have been used throughout the specification to refer to the same or similar components. In addition, some components in the attached drawings are exaggerated, omitted, or schematically depicted, and the size of each component does not entirely reflect the actual size.

The attached drawings are only intended to facilitate understanding of the embodiments disclosed in this specification, and the technical ideas disclosed in this specification are not limited by the attached drawings, and should be understood to include all modifications, equivalents, or substitutes included in the spirit and technical scope of the present invention.

Terms that include ordinal numbers, such as first, second, etc., may be used to describe various components, but the components are not limited by these terms. These terms are used solely to distinguish one component from another.

Furthermore, when we say that a layer, membrane, region, plate, or other part is "above" or "on" another part, this includes not only cases where it is "directly above" the other part, but also cases where there are other parts in between. Conversely, when we say that a part is "directly above" another part, we mean that there are no other parts in between. Furthermore, saying that a part is "above" or "on" a reference part means that it is located above or below the reference part, and does not necessarily mean that it is located "above" or "on" the opposite direction of gravity.

Throughout the specification, terms such as "comprises" or "has" should be understood to indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but not to exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof. Therefore, when a part is said to "comprise" a certain component, this does not mean that other components are excluded, but rather that other components may be included, unless specifically stated otherwise.

Additionally, throughout the specification, when we say "in plan", we mean when the target portion is viewed from above, and when we say "in cross section", we mean when the target portion is viewed from the side in a cross-section cut vertically.

Additionally, throughout the specification, when we say "connected," this does not only mean that two or more components are directly connected, but also that two or more components are indirectly connected through other components, that they are electrically connected as well as physically connected, or that they are referred to by different names depending on location or function but are one.

Throughout the specification, the term "substantially identical" includes not only those that are numerically exactly identical, but also those that are designed to be the same size or level but may have slight differences within tolerances due to manufacturing process tolerances or material properties that would be considered identical by a person skilled in the art.

Hereinafter, a circuit board (10A) according to one embodiment will be described with reference to FIGS. 1 and 2.

Fig. 1 is a cross-sectional view schematically showing the structure of a circuit board according to one embodiment.

Referring to FIG. 1, a circuit board (10A) according to one embodiment may include an insulating layer (110) including a first insulating layer portion (111) and a second insulating layer portion (112), a first circuit layer (121), and a metal pattern layer (200). The second insulating layer portion (112) may be laminated on the first insulating layer portion (111). The insulating layer (110) may have a cavity (110a) penetrating a portion of the second insulating layer portion (112) and the first insulating layer portion (111). The first circuit layer (121) may be at least partially embedded in the second insulating layer portion (112). The metal pattern layer (200) may be disposed along an edge of the cavity (110a) within the second insulating layer portion (112). The insulating layer (110) may have a first surface (S1) constituting the bottom surface of the cavity (110a) and a second surface (S2) constituting the side surface of the cavity (110a). The metal pattern layer (200) may include a plurality of metal layers, each of which contains a different metal, and is exposed from the insulating layer (110) at the second surface (S2).

The insulating layer (110) may have a structure in which multiple layers are laminated. For example, the insulating layer (110) may include a first insulating layer portion (111), a second insulating layer portion (112), and a third insulating layer portion (113). The second insulating layer portion (112) may be laminated on one surface of the first insulating layer portion (111). The third insulating layer portion (113) may be disposed on the other surface of the first insulating layer portion (111). The third insulating layer portion (113) may be disposed to face the second insulating layer portion (112).

The insulating layer (110) may include an insulating material. The insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material including an inorganic filler, an organic filler, and/or glass fiber (glass cloth, and/or glass fabric) together with such a resin, and may be a photosensitive material and/or a non-photosensitive material. For example, insulating materials such as SR (Solder Resist), ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine), RCC (Resin Coated Copper), and CCL (Copper Clad Laminate) may be used, but are not limited thereto, and other polymer materials may be included. Meanwhile, a material of the insulating layer (110) may be used that includes an inorganic filler such as silica and a reinforcing material such as glass fiber in these resins. For example, prepreg may be used, but is not limited thereto. In addition, in FIG. 1, the insulating layer (110) is represented as three layers, but is not limited thereto, and the insulating layer (110) may include one or more insulating layer sections.

A circuit board (10A) according to one embodiment may include a plurality of circuit layers. For example, a circuit board (10A) according to one embodiment may include first to fourth circuit layers (121, 122, 123, 124). Each of the first to fourth circuit layers (121, 122, 123, 124) may be embedded in an insulating layer (110) or disposed on the insulating layer (110).

The first circuit layer (121) may be disposed on one surface of the first insulating layer portion (111). The first circuit layer (121) may be at least partially embedded in the second insulating layer portion (112). The second circuit layer (122) may be located on the second insulating layer portion (112). The second circuit layer (122) may be located on one surface of the insulating layer (110). The third circuit layer (123) may be located on one surface of the third insulating layer portion (113). The third circuit layer (123) may be at least partially embedded in the first insulating layer portion (111). The fourth circuit layer (124) may be located on the other surface of the third insulating layer portion (113). The fourth circuit layer (124) may be at least partially exposed on the other surface of the insulating layer (110). The fourth circuit layer (124) can be at least partially embedded in the third insulating layer (113).

A portion of the first circuit layer (121) may function as a pad for connection with another substrate or component. The first circuit layer (121) may include a first pad (121a) that is exposed to the outside of the insulating layer (110) on the other surface of the second insulating layer portion (112). The first pad (121a) may be partially embedded in the second insulating layer portion (112), but is not limited thereto, and the first pad (121a) may also be disposed on one surface of the first insulating layer portion (111) and protrude from the one surface.

A portion of the second circuit layer (122) may function as a pad for connection with another substrate or component. The second circuit layer (122) may include a second pad (122a) that is exposed to the outside of the insulating layer (110) on one surface of the second insulating layer portion (112). The second pad (122a) may be disposed on one surface of the insulating layer (110). The second pad (122a) may be disposed on one surface of the second insulating layer portion (112) and protrude from the one surface, but is not limited thereto, and the second pad (122a) may also be partially embedded in the insulating layer portion (112).

A portion of the fourth circuit layer (124) may function as a pad for connection with another substrate or component. The fourth circuit layer (124) may include a third pad (124a) that is exposed to the outside of the insulating layer (110) on the other surface of the third insulating layer portion (113). The third pad (124a) may be partially embedded in the third insulating layer portion (113), but is not limited thereto, and the third pad (124a) may also be disposed on the other surface of the third insulating layer portion (113) and protrude from the other surface.

The first pad (121a) may include an electrolytic plating layer. The first pad (121a) may be formed as a single layer. The second pad (122a) may include an electroless plating layer and an electrolytic plating layer. The second pad (122a) may include multiple layers. The third pad (124a) may include an electrolytic plating layer. The third pad (124a) may be formed as a single layer.

In Fig. 1, first to fourth circuit layers (121, 122, 123, 124) are illustrated, but the present invention is not limited thereto, and a greater number of circuit layers than illustrated may be arranged, or a smaller number of circuit layers may be arranged.

Each of the first to fourth circuit layers (121, 122, 123, 124) can transmit a signal inside the circuit board (10A). A metal material can be used as a material for each of the first to fourth circuit layers (121, 122, 123, 124). The metal material can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. Each of the first to fourth circuit layers (121, 122, 123, 124) can perform various functions according to the design, such as a ground pattern, a power pattern, a signal pattern, etc. Each of these patterns can have a line, a plane, or a pad shape. In the case of a circuit layer located on the outermost layer among the plurality of circuit layers, it can function as a pad for connection with another substrate or component.

Each of the first to fourth circuit layers (121, 122, 123, 124) may be formed by a wiring formation process, for example, an Additive Process (AP), a Semi AP (SAP), a Modified SAP (MSAP), a Tenting (TT), etc. Each of the first to third circuit layers (121, 122, 123) may include a seed layer, which is an electroless plating layer, and an electrolytic plating layer formed based on the seed layer. The fourth circuit layer (124) may include an electrolytic plating layer.

The first circuit layer (121) may include a first conductive layer (1211) disposed on one surface of the first insulating layer portion (111) and a second conductive layer (1212) laminated on the first conductive layer (1211). The first conductive layer (1211) may include an electroless plating layer, and the second conductive layer (1212) may include an electrolytic plating layer, but is not limited thereto. The second circuit layer (122) may include a third conductive layer (1221) disposed on the second insulating layer portion (112), and a fourth conductive layer (1222) laminated on the third conductive layer (1221). The third conductive layer (1221) may include an electroless plating layer, and the fourth conductive layer (1222) may include an electrolytic plating layer, but is not limited thereto. The third circuit layer (123) may include a fifth conductive layer (1231) disposed on the third insulating layer portion (113), and a sixth conductive layer (1232) laminated on the fifth conductive layer. The fifth conductive layer (1231) may include an electroless plating layer, and the sixth conductive layer (1232) may include an electrolytic plating layer, but is not limited thereto. The electroless plating layer may be a chemical copper plating layer, but is not limited thereto, and may be, for example, a sputtering layer.

A circuit board (10A) according to one embodiment may include a first via electrode (131) penetrating the second insulating layer portion (112) and electrically connecting the first circuit layer (121) and the second circuit layer (122), a second via electrode (132) penetrating the first insulating layer portion (111) and electrically connecting the first circuit layer (121) and the third circuit layer (123), and a third via electrode (133) penetrating the third insulating layer portion (113) and electrically connecting the third circuit layer (123) and the fourth circuit layer (124). In FIG. 1, the first to third via electrodes (131, 132, 133) are each illustrated as a single number, but this is not limited thereto, and the first to third via electrodes (131, 132, 133) may each be provided in multiple numbers.

A metal material may be used as the material of each of the first to third via electrodes (131, 132, 133). The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. Each of the first to third via electrodes (131, 132, 133) may include a signal via, a ground via, a power via, etc., depending on the design. Each of the first to third via electrodes (131, 132, 133) may be a via hole filled with a metal material, or a metal material may be formed along the wall surface of the via hole. Each of the plurality of via electrodes may be formed by a plating process. For example, the first to third via electrodes (131, 132, 133) may each have a tapered shape in which the width of one side is smaller than the width of the other side.

Meanwhile, in FIG. 1, a circuit board (10A) according to one embodiment is illustrated as including first to third via electrodes (131, 132, 133), but depending on the configuration of the insulating layer (110) and the design of the circuit layer, the via layer in which the via electrodes are arranged may be composed of a single layer or may be composed of more layers.

A circuit board (10A) according to one embodiment may include a first protective layer (141) and a second protective layer (142). Each of the first protective layer (141) and the second protective layer (142) may protect internal components from external physical and chemical damage, etc.

The first protective layer (141) may be disposed on one surface of the insulating layer (110). The first protective layer (141) may cover one surface of the insulating layer (110) and may be opened to expose at least a portion of the second circuit layer (122). The first protective layer (141) may have at least one opening. The first protective layer (141) may include a photosensitive resin material. The first protective layer (141) may be a solder resist layer.

The second protective layer (142) may be disposed on the other surface of the insulating layer (110). The second protective layer (142) may cover the other surface of the insulating layer (110) and may be opened to expose at least a portion of the fourth circuit layer (124). The second protective layer (142) may have at least one opening. The second protective layer (142) may include a photosensitive resin material. The second protective layer (142) may be a solder resist layer.

A circuit board (10A) according to one embodiment may include first to third surface treatment layers (151, 152, 153) that cover a portion of a circuit layer exposed to the outside of an insulating layer (110). The first surface treatment layer (151) may be disposed on a first pad (121a). The second surface treatment layer (152) may be disposed on a second pad (122a). The third surface treatment layer (153) may be disposed on a third pad (124a). The first to third surface treatment layers (151, 152, 153) may include any one metal selected from the group consisting of nickel (Ni), palladium (Pd), and gold (Au), and these metal layers may be implemented in multiple forms. Meanwhile, the present invention is not limited thereto, and the surface treatment layer may include an organic material. The first to third surface treatment layers (151, 152, 153) can improve the bonding strength and signal transmission strength of the first to third pads (121a, 122a, 124a) and the configuration mounted on the first to third pads (121a, 122a, 124a).

The insulating layer (110) may have a cavity (110a) penetrating a portion of the second insulating layer portion (112) and the first insulating layer portion (111). A circuit board (10A) according to one embodiment may include a metal pattern layer (200) disposed around the cavity (110a) within the second insulating layer portion (112). The insulating layer (110) may have a first surface (S1) forming a bottom surface of the cavity (110a) and a second surface (S2) forming a side surface of the cavity (110a). A first pad (121a) may be exposed from the second insulating layer portion (112) on the first surface (S1).

The metal pattern layer (200) may be exposed from the insulating layer (110) on the second surface (S2). The metal pattern layer (200) may include a plurality of metal layers. Each of the plurality of metal layers may include different metals.

Hereinafter, with reference to FIGS. 1 to 3, the metal pattern layer (200) of the circuit board (10A) according to one embodiment will be described in more detail.

Fig. 2 is an enlarged cross-sectional view of part A of the circuit board shown in Fig. 1. Fig. 3 is an enlarged cross-sectional view of part B of the circuit board shown in Fig. 1.

Referring to FIGS. 1 to 3, the metal pattern layer (200) may be arranged to connect the first surface (S1) and the second surface (S2). The metal pattern layer (200) may be arranged in a corner region of the cavity (110a). The metal pattern layer (200) may be arranged to surround the cavity (110a). The metal pattern layer (200) may be arranged to surround the first surface (S1).

The metal pattern layer (200) may include a first metal layer (210) and a second metal layer (220). The first metal layer (210) may be positioned on one surface of the first insulating layer portion (111). The second metal layer (220) may be disposed on one surface of the first metal layer (210). One surface of the second metal layer (220) may be in contact with the first surface (S1).

Each of the first metal layer (210) and the second metal layer (220) may include different metals. Each of the first metal layer (210) and the second metal layer (220) may have different etching selectivities for the same material. For example, the first metal layer (210) may include copper (Cu), and the second metal layer (220) may include nickel (Ni), but is not limited thereto, and any metals that allow the first metal layer (210) and the second metal layer (220) to have different etching selectivities for the same material may be used. The etching selectivity may mean a ratio of the etching rate of material X to the etching rate of material Y. Here, material X may be a material that is desired to be etched, and material Y may be a material that is not desired to be etched (such as a mask layer).

For example, the first metal layer (210) and the first conductive layer (1211) may be formed through the same process. The first metal layer (210) may include the same material as the first conductive layer (1211). The first metal layer (210) and the first conductive layer (1211) may include the same material including copper (Cu). In addition, the first metal layer (210) may include the same material as the third conductive layer (1221) and the fifth conductive layer (1231). The first metal layer (210), the third conductive layer (1221), and the fifth conductive layer (1231) may include the same material including copper (Cu). Therefore, the second metal layer (220) may include a different material from the first conductive layer (1211). The second metal layer (220) may include a different material from the third conductive layer (1221) and the fifth conductive layer (1231).

Referring to FIG. 2, the metal pattern layer (200) may be positioned inward from the second surface (S2) in a direction perpendicular to the stacking direction. The metal pattern layer (200) may be positioned concavely inward from the second surface (S2). The edge of the metal pattern layer (200) may include a portion that is recessed inward from the second surface (S2). One surface of the metal pattern layer (200) exposed toward the cavity (110a) may include an inclined surface that is inclined with respect to a reference line parallel to the stacking direction. The inclined surface of the metal pattern layer (200) may be a curved surface. For example, the metal pattern layer (200) may have a curved inclined surface by a wet etching process. The edge of the first metal layer (210) may have a shape that is recessed inward from the second surface (S2). One side of the first metal layer (210) exposed toward the cavity (110a) may include an inclined surface inclined with respect to a reference line parallel to the stacking direction. The inclined surface of the first metal layer (210) may be a curved surface. The edge of the second metal layer (220) may have a shape that is recessed inward from the second surface (S2). One side of the second metal layer (220) exposed toward the cavity (110a) may include an inclined surface inclined with respect to a reference line parallel to the stacking direction. The inclined surface of the second metal layer (220) may be a curved surface.

Referring to FIG. 3, the lower surface (S1212) of the second conductive layer (1212) may be disposed at substantially the same level as the lower surface (S220) of the second metal layer (220). The second conductive layer (1212) may be disposed on substantially the same plane as the second metal layer (220). The lower surface (S1212) of the second conductive layer (1212) may be positioned at substantially the same distance from the lower surface (S220) of the second metal layer (220) and the upper surface of the first insulating layer portion (111). The distance (d1) from the upper surface of the first insulating layer portion (111) to the lower surface (S1212) of the second conductive layer (1212) may be substantially the same as the distance (d2) from the upper surface of the first insulating layer portion (111) to the lower surface (S220) of the second metal layer (220).

The lower surface (S121a) of the first pad (121a) may be positioned at a greater distance in the stacking direction from the upper surface of the first insulating layer portion (111) than the lower surface (S121) of the first circuit layer (121). In terms of the distance in the stacking direction based on the first insulating layer portion (111), the surface of the first pad (121a) exposed from the second insulating layer portion (112) may be positioned further than the surface facing the first insulating layer portion (111) of the first circuit layer (121).

The lower surface (S121a) of the first pad (121a) may be located at a greater distance in the stacking direction from the upper surface of the first insulating layer portion (111) than the lower surface (S220) of the second metal layer (220). The distance (d3) from the upper surface of the first insulating layer portion (111) to the lower surface (S121a) of the first pad (121a) may be greater than the distance (d2) from the upper surface of the first insulating layer portion (111) to the lower surface (S220) of the second metal layer (220).

In terms of the distance in the stacking direction based on the first insulating layer portion (111), the surface exposed from the second insulating layer portion (112) of the first pad (121a) may be located further away than the surface facing the first insulating layer portion (111) of the second metal layer (220).

Referring to FIG. 3, in terms of thickness in the stacking direction, the thickness (t1) of the first pad (121a) may be smaller than the thickness (t2) of the first circuit layer (121). In terms of thickness in the stacking direction, the thickness (t1) of the first pad (121a) may be smaller than the thickness (t3) of the second conductive layer (1212). In terms of thickness in the stacking direction, the thickness (t4) of the metal pattern layer (200) may be smaller than the thickness (t2) of the first circuit layer (121). In terms of thickness in the stacking direction, the thickness (t5) of the first metal layer (210) may be substantially the same as the thickness (t6) of the first conductive layer (1211).

According to a circuit board according to one embodiment, a plurality of metal layers including different metals can be used as etching stop layers to more easily form a cavity structure and a pad structure exposed in the cavity, and a circuit board having a thin thickness can be provided, thereby making it possible to reduce the thickness of an electronic product package on which the circuit board is mounted.

Hereinafter, a method for manufacturing a circuit board (10A) according to one embodiment will be described with reference to FIGS. 4 to 17.

FIGS. 4 to 16 are cross-sectional views illustrating a method for manufacturing a circuit board according to one embodiment.

Referring to FIG. 4, a carrier board, which is a basic material for manufacturing a circuit board (10A) according to one embodiment, may be prepared. The carrier board may include a carrier insulating layer (510) and a carrier conductive layer (520) disposed on one surface of the carrier insulating layer (510). The carrier conductive layer (520) may be disposed on one surface of the carrier insulating layer (510), or alternatively, may be disposed on both surfaces. When the carrier conductive layer (520) is disposed on both surfaces of the carrier insulating layer (510), in the following process, a circuit board manufacturing process may be performed on both sides of the carrier board before the carrier board is removed. The carrier conductive layer (520) may be formed by performing electroless plating on the surface of the carrier insulating layer (510).

Also, referring to FIG. 4, a fourth circuit layer (124) can be formed on the carrier conductive layer (520). The fourth circuit layer (124) can be formed through a plating process. For example, the fourth circuit layer (124) can be formed by forming a photoresist on the carrier conductive layer (520), patterning the photoresist through an exposure and development process, filling the patterned area with plating, and then peeling off the photoresist. However, the present invention is not limited thereto, and any method capable of forming a pattern on a circuit board can be used without limitation.

Referring to FIG. 5, a third insulating layer portion (113) can be formed so that a carrier conductive layer (520) and a fourth circuit layer (124) are buried. The third insulating layer portion (113) can be formed using materials such as Prepreg (PPG), ABF (Ajinomoto build-up film), and RCC (Resin Coated Copper foil).

Referring to Fig. 5, a third via hole (1331) can be formed by penetrating the third insulating layer (113). The third via hole (1331) can be formed by laser, mechanical drilling, or the like.

In addition, a fifth conductive layer formation layer (P1231) may be formed on one surface of the third insulating layer portion (113). The fifth conductive layer formation layer (P1231) may be formed by performing electroless plating on one surface of the third insulating layer portion (113). In Fig. 5, the fifth conductive layer formation layer (P1231), which is an electroless plating layer, is illustrated as being positioned only on one surface of the third insulating layer portion (113), but an electroless plating layer may also be positioned on the inner surface of the third via hole (133).

Referring to Fig. 6, a sixth conductive layer (1232) can be formed on a fifth conductive layer formation layer (P1231). The sixth conductive layer (1232) can be formed through a plating process. In addition, a third via electrode (133) can be formed by filling a third via hole (1331) with a conductive material.

For example, the sixth conductive layer (1232) and the third via electrode (133) can be formed by forming a photoresist on the fifth conductive layer formation layer (P1231), patterning the photoresist through an exposure and development process, filling the patterned area with plating, and then peeling off the photoresist. However, this is not limited to this, and any method capable of forming a pattern on a circuit board can be used without limitation.

Referring to FIG. 7, a portion of the fifth conductive layer formation layer (P1231) may be removed to form a fifth conductive layer (1231). Accordingly, a third circuit layer (123) including the fifth conductive layer (1231) and the sixth conductive layer (1232) may be formed. For example, the fifth conductive layer (1231) may be removed through flash etching.

And, a first insulating layer portion (111) can be formed so that the fifth conductive layer (1231) and the sixth conductive layer (1232) are buried. The first insulating layer portion (111) can be formed using materials such as Prepreg (PPG), ABF (Ajinomoto build-up film), and RCC (Resin Coated Copper foil).

In addition, referring to FIG. 7, a second via hole (1321) can be formed by penetrating the first conductive layer forming layer (P1211) and the first insulating layer portion (111). The second via hole (1321) can be formed by laser, mechanical drilling, or the like.

And, a first conductive layer formation layer (P1211) can be formed on one surface of the first insulating layer portion (111). The first conductive layer formation layer (P1211) can be formed by performing electroless plating on one surface of the first insulating layer portion (111). In Fig. 7, the first conductive layer formation layer (P1211), which is an electroless plating layer, is illustrated as being positioned only on one surface of the first insulating layer portion (111), but an electroless plating layer may also be positioned on the inner surface of the second via hole (1321).

Referring to FIG. 8, a mask layer (530) may be formed on one surface of the first conductive layer formation layer (P1211). Specifically, the mask layer (530) may be formed in a portion excluding the area where the second stopper layer (2200) is to be formed. The mask layer (530) may be formed by including a dry film.

And, a second stopper layer (2200) can be formed on the first insulating layer portion (111). The second stopper layer (2200) can be formed including a second metal. For example, the second metal can include nickel (Ni). The second stopper layer (2200) can be formed on the first conductive layer forming layer (P1211). The first conductive layer forming layer (P1211) can include a first metal different from the second metal. For example, the first metal can include copper (Cu).

Referring to FIG. 9, a second via electrode (132) can be formed by filling a conductive material into a second via hole (1321).

Also, referring to FIG. 9, the mask layer (530) may be removed, and a second conductive layer (1212) may be formed on a portion of the first conductive layer forming layer (P1211) and the second stopper layer (2200). The second conductive layer (1212) may be formed through a plating process. The second conductive layer (1212) may be formed so that the lower surface (S1212) of the second conductive layer (1212) has substantially the same level as the lower surface of the second stopper layer (2200). Based on the upper surface of the first insulating layer portion (111), the lower surface (S1212) of the second conductive layer (1212) and the lower surface of the second stopper layer (2200) may be positioned at substantially the same distance.

For example, the second conductive layer (1212) can be formed by forming a photoresist on the first conductive layer formation layer (P1211), patterning the photoresist through an exposure and development process, filling the patterned area with plating, and then peeling off the photoresist. However, this is not limited to this, and any method capable of forming a pattern on a circuit board can be used without limitation.

Here, a second conductive layer (1212) can be formed to include a first pad (121a). The first pad (121a) can be formed on the second stopper layer (2200). The second conductive layer (1212) can be formed to include the first pad (121a) and a pattern portion arranged around the first pad (121a). The first pad (121a) can be formed to include a portion of the second conductive layer (1212).

Referring to FIG. 10, a portion of the first conductive layer forming layer (P1211) may be removed to form a first conductive layer (1211) and a first stopper layer (2100). The first conductive layer (1211) may be formed by including the same material as the first stopper layer (2100). Accordingly, a first circuit layer (121) including the first conductive layer (1211) and the second conductive layer (1212) may be formed on the first insulating layer portion (111).

The first pad (121a) may be formed so that the lower surface (S121a) of the first pad (121a) is positioned at a higher level than the lower surface (S121) of the first circuit layer (121). The first pad (121a) may be formed so that the lower surface (S121a) of the first pad (121a) is positioned at a greater distance from the upper surface of the first insulating layer portion (111) than the lower surface (S121) of the first circuit layer (121).

For example, the first challenge layer (1211) can be removed through flash etching.

The first stopper layer (2100) may be formed by including a first metal. The first metal may be a material having a different etching selectivity from the second metal for the same material. The first metal may include copper (Cu). The first stopper layer (2100) may be formed on the first insulating layer portion (111). The first stopper layer (2100) may have a shape corresponding to that of the second stopper layer (2200). The first stopper layer (2100) may overlap the second stopper layer in the lamination direction.

Referring to Fig. 11, a second insulating layer portion (112) can be formed so that a first circuit layer (121), a first stopper layer (2100), and a second stopper layer (2200) are embedded. A first pad (121a) can be laminated on the first insulating layer portion (111) to form a second insulating layer portion (112) so that it is embedded. The second insulating layer portion (112) can be formed using a material such as Prepreg (PPG), ABF (Ajinomoto build-up film), RCC (Resin Coated Copper foil), etc. Accordingly, an insulating layer (110) including a first insulating layer portion (111), a second insulating layer portion (112), and a third insulating layer portion (113) can be formed. In the embodiment, the insulating layer is illustrated as including three layers, but is not limited thereto.

In addition, referring to FIG. 11, a first via hole (1311) can be formed by penetrating the third conductive layer forming layer (P1221) and the second insulating layer portion (112). The first via hole (1311) can be formed by laser, mechanical drilling, or the like.

And, a third conductive layer formation layer (P1221) can be formed on one surface of the second insulating layer portion (112). The third conductive layer formation layer (P1221) can be formed by performing electroless plating on one surface of the second insulating layer portion (112). In Fig. 11, the third conductive layer formation layer (P1221), which is an electroless plating layer, is illustrated as being positioned only on one surface of the second insulating layer portion (112), but an electroless plating layer may also be positioned on the inner surface of the first via hole (1311).

Referring to FIGS. 11 and 12, a fourth conductive layer (1222) can be formed on a third conductive layer formation layer (P1221). The fourth conductive layer (1222) can be formed through a plating process. In addition, a first via electrode (131) can be formed by filling a first via hole (1311) with a conductive material.

For example, the fourth conductive layer (1222) and the first via electrode (131) can be formed by forming a photoresist on the third conductive layer formation layer (P1221), patterning the photoresist through an exposure and development process, filling the patterned area with plating, and then peeling off the photoresist. However, the present invention is not limited thereto, and any method capable of forming a pattern on a circuit board can be used without limitation.

And, referring to FIG. 12, a portion of the third conductive layer formation layer (P1221) may be removed to form a third conductive layer (1221). Accordingly, a second circuit layer (122) including the third conductive layer (1221) and the fourth conductive layer (1222) may be formed. For example, the third conductive layer (1221) may be removed through flash etching.

Here, a second circuit layer (122) can be formed to include a second pad (122a). The second pad (122a) can be formed to be exposed from the insulating layer (110) on one surface of the insulating layer (110). The second circuit layer (122) can be formed to include the second pad (122a) and a pattern portion arranged around the second pad (122a). The second pad (122a) can be formed to include a portion of the third conductive layer (1221) and a portion of the fourth conductive layer (1222). The second pad (122a) can be formed by stacking an electroless plating layer and an electrolytic plating layer.

In addition, the carrier insulating layer (510) and the carrier conductive layer (520) can be removed. For example, the carrier conductive layer (520) can be removed through quick etching. Accordingly, a third pad (124a), which is a portion of the fourth circuit layer (124) exposed on the other surface of the insulating layer (110), can be formed. In other words, the fourth circuit layer (124) can be formed to include the third pad (124a). In FIG. 12, the fourth circuit layer (124) is illustrated as being exposed on the other surface of the insulating layer (110), but is not limited thereto, and the fourth circuit layer (124) can be formed to include the third pad (124a) and a pattern portion disposed around the third pad (124a). The third pad (124a) can be formed to include an electroplating layer.

Referring to FIG. 13, a first protective layer (141) may be formed on a second insulating layer portion (112) to expose a portion of a second circuit layer (122). A second protective layer (142) may be formed on a third insulating layer portion (113) to expose a portion of a fourth circuit layer (124). The first protective layer (141) and the second protective layer (142) may be formed through exposure and development processes. The first protective layer (141) may have an opening that exposes a portion of the second circuit layer (122). The second protective layer (142) may have an opening that exposes a portion of the fourth circuit layer (124). The first protective layer (141) and the second protective layer (142) may be solder resist layers.

Referring to FIG. 14, a first cavity forming portion (110a1) may be formed by removing a portion of the insulating layer (110) from the other surface of the insulating layer (110) to the first stopper layer (2100). For example, a portion of the insulating layer (110) may be removed using a CO ₂ laser. By processing up to the first stopper layer (2100) during laser processing, the portion of the insulating layer (110) located on the first stopper layer (2100) may be prevented from being damaged. To this end, the area of the first cavity forming portion (110a1) in a direction perpendicular to the stacking direction may be smaller than the area of the first stopper layer (2100). In other words, the width of the first cavity forming portion in a direction perpendicular to the stacking direction may be smaller than the width of the first stopper layer (2100).

Referring to FIG. 15, the exposed portion within the first cavity forming portion (110a1) of the first stopper layer (2100) may be etched and removed to form a first metal layer (210) and a second cavity forming portion (110a2). Forming the second cavity forming portion (110a2) may include removing the exposed portion of the first stopper layer (2100) and forming the remaining first metal layer (210) along the edge of the first cavity forming portion (110a1). The first metal layer (210) may be formed to surround the cavity.

The etching process may utilize dry etching or wet etching, but is not limited thereto. For example, an etching resist may be formed in an area other than the area to be etched of the first stopper layer (2100), and a portion of the first stopper layer (2100) to be etched may be removed by etching. The etching resist may include a dry film.

Referring to FIG. 16, a second metal layer (220) and a cavity (110a) can be formed by removing an exposed portion within the second cavity forming portion (110a2) of the second stopper layer (2200). Accordingly, a metal pattern layer (200) including the first metal layer (210) and the second metal layer (220) can be formed. Forming the cavity (110a) may include removing the exposed portion of the second stopper layer (2200) and forming the remaining second metal layer (220) along the edge of the second cavity forming portion (110a2). The second metal layer (220) may be formed to surround the cavity (110a). The second metal layer (220) may be formed at a position corresponding to the first metal layer (210). The second metal layer (220) can be formed to overlap the first metal layer (210) in the lamination direction.

The first pad (121a) may be formed so that the lower surface (S121a) of the first pad (121a) is positioned at a higher level than the lower surface (S220) of the second metal layer (220). The first pad (121a) may be formed so that the lower surface (S121a) of the first pad (121a) is positioned at a greater distance from the upper surface of the first insulating layer portion (111) than the lower surface (S220) of the second metal layer (220).

The etching process may utilize dry etching or wet etching, but is not limited thereto. For example, an etching resist may be formed in an area other than the area to be etched of the first stopper layer (2100), and a portion of the first stopper layer (2100) to be etched may be removed by etching. The etching resist may include a dry film.

For example, the first stopper layer (2100) can be etched using a first etchant, and the second stopper layer (2200) can be etched using a second etchant that is different from the first etchant. The first stopper layer (2100) and the second stopper layer (2200) can include metal materials that can be selectively removed by different etchants, and as described above, for example, the first stopper layer (2100) can include a first metal, and the second stopper layer (2200) can include a second metal having an etching selectivity different from that of the first metal. Therefore, the first stopper layer (2100) and the second stopper layer (2200) can be sequentially removed using metals having different etching selectivities, thereby exposing the first pad (121a) from the insulating layer (110) without damage.

In addition, referring to FIG. 1 together with FIG. 16, the first to third surface treatment layers (151, 152, 153) may be formed to cover a portion of the circuit layer exposed to the outside of the insulating layer (110), thereby forming a circuit board (10A) according to an embodiment as in FIG. 1. The first surface treatment layer (151) may be formed on the first pad (121a). The second surface treatment layer (152) may be formed on the second pad (122a). The third surface treatment layer (153) may be formed on the third pad (124a). For example, the first to third surface treatment layers (151, 152, 153) may be formed using an ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold) method, an ENIG (Electroless Nickel Immersion Gold) method, or the like.

In terms of thickness in the stacking direction, the first pad (121a) may be formed to have a thickness smaller than the thickness of the first circuit layer (121). In terms of thickness in the stacking direction, the first pad (121a) may be formed to have a thickness smaller than the thickness of the second conductive layer (1212). In terms of thickness in the stacking direction, the metal pattern layer (200) may be formed to have a thickness smaller than the thickness of the first circuit layer (121). In terms of thickness in the stacking direction, the first metal layer (210) may be formed to have a thickness substantially the same as the thickness of the first conductive layer (1211).

Referring to FIG. 1 and FIG. 2, along with FIG. 16, the first metal layer (210) may be formed to be recessed inwardly from the side surface of the second insulating layer portion (112) as the first stopper layer (2100) is etched and formed. For example, the first metal layer (210) may have a curved slope by a wet etching process. The first metal layer (210) may be formed such that one surface exposed toward the cavity (110a) includes a sloped slope with respect to a reference line parallel to the stacking direction. The first metal layer (210) may be formed to have a curved sloped slope. In addition, the second metal layer (220) may be formed to be recessed inwardly from the side surface of the second insulating layer portion (112) as the second stopper layer (2200) is etched and formed. For example, the second metal layer (220) may have a curved slope by a wet etching process. The second metal layer (220) may be formed such that one surface exposed toward the cavity (110a) includes a sloped slope with respect to a reference line parallel to the stacking direction. The second metal layer (220) may be formed to have a curved sloped slope.

According to a method for manufacturing a circuit board according to one embodiment, by using a plurality of metal layers each containing a different metal as an etching stop layer, the efficiency of the process can be increased, and pads can be formed to be exposed more easily in a cavity, thereby forming a circuit board in a thinner shape.

Hereinafter, an electronic component package according to one embodiment will be described with reference to FIG. 17. FIG. 17 is a cross-sectional view schematically illustrating an electronic component package according to one embodiment.

Referring to FIG. 17, an electronic component package (20) according to one embodiment may include a first circuit board (10). The first circuit board (10) may include the circuit board (10A) according to the above-described embodiment. Hereinafter, the description of the first circuit board (10) may be equally applied to the description of the circuit board (10A) according to the above-described embodiment.

An electronic component package (20) according to one embodiment may include a first circuit board (10), a second circuit board (21), an electronic component (22), an encapsulant (23), a conductive member (24), and an electrode (25). The second circuit board (21) may be connected to the first circuit board (10). The first circuit board (10) may have a cavity (110a) and may include a first pad (121a) exposed from an insulating layer (110) within the cavity (110a). The electronic component (22) may be mounted on one surface of the first circuit board (10) so as to be connected to the pad portion of the first circuit board (10). The electronic component (22) may be accommodated within the cavity (110a). The encapsulant (23) may be disposed between the first and second circuit boards (10, 21). The sealant (23) can cover at least a portion of the electronic component (22). The conductive member (24) can electrically connect the first and second circuit boards (10, 21). The electrode (25) can electrically connect the first circuit board (10) and the electronic component (22).

The second circuit board (21) is a circuit board on which electronic components (22) are mounted, and may include an insulating layer, a wiring layer, a via layer, and a solder resist layer.

For example, the electronic component (22) may be an integrated circuit (IC) die in which hundreds to millions of elements are integrated into a single chip. For example, the electronic component (22) may be a processor chip such as a central processor (e.g., a CPU), a graphic processor (e.g., a GPU), a field programmable gate array (FPGA), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, or the like, specifically, an application processor (AP), but is not limited thereto, and may also be memory such as other volatile memories (e.g., DRAM), non-volatile memories (e.g., ROM), flash memories, or logic such as an analog-to-digital converter or an application-specific IC (ASIC). If necessary, the electronic component (22) may be a chip-type passive component, for example, a chip-type capacitor such as an MLCC (Multi-Layer Ceramic Capacitor), a chip-type inductor such as a PI (Power Inductor), etc. The electronic component (22) can be covered by a sealant (23), and at least one side can be in physical contact with the sealant (23).

The sealant (23) can cover at least a portion of one surface of the first circuit board (10) and the outer surface of the electronic component (22). In addition, the sealant (23) can fill at least a portion of the cavity (110a), thereby covering at least a portion of the upper surface of the electronic component (22). For example, the sealant (23) can physically contact at least a portion of each of the upper surface, lower surface, and side surface of the electronic component (22). Since the sealant (23) has fluidity before being cured, it can flow along the outer surface of the electronic component (22) and fill the interior of the cavity (110a).

An insulating material may be used as the material of the sealant (23), and a thermosetting resin such as an epoxy resin or a thermoplastic resin such as a polyimide may be used as the insulating material. In addition, a resin containing an inorganic filler such as silica may be used. For example, ABF (Ajinomoto Build-up Film) may be used as the material of the sealant (23). ABF may be provided in the form of RCC (Resin Coated Copper), but is not limited thereto. If necessary, a photosensitive material such as PIE (Photo Image-able Dielectric) may be used. In addition, the sealant (23) may be a known EMC (Epoxy Molding Compound), but is not limited thereto.

The conductive member (24) may be arranged in at least a portion of the opening of the first circuit board (10). The conductive member (24) may physically and/or electrically connect the first circuit board (10) to the outside. For example, the conductive member (24) may electrically connect the exposed circuit pattern layer of the second circuit board (21) and the third pad (124a) of the first circuit board (10). The conductive members (24) may be formed of tin (Sn) or an alloy containing tin (Sn), for example, solder, but are not limited thereto. For example, the conductive member (24) may be a metal post in the shape of a ball, a land, a pin, or a pillar, or a pillar shape in which a plurality of balls are combined.

An electrode (25) may be placed in a cavity (110a) of a first circuit board (10). The electrode (25) may physically and/or electrically connect the first circuit board (10) to an electronic component (22). For example, the electrode (25) may electrically connect a pad portion of the electronic component (22) to a first pad (121a) of the first circuit board (10).

According to an electronic component package according to one embodiment, a pad portion is positioned inside a cavity of a first circuit board in which an electronic component is accommodated, thereby providing a thin package while securing a mounting space for the electronic component.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited thereto, and various modifications can be made within the scope of the claims, the description of the invention, and the attached drawings, and it is obvious that this also falls within the scope of the present invention.

10A, 10B: Circuit board
20: Electronic component packages
22: Electronic components
110: Insulation layer
110a: Cavity
200: Metal pattern layer
210: First metal layer,
220: Second metal layer
2100: First stopper layer
2200: Second stopper layer

Claims (31)

An insulating layer comprising a first insulating layer portion and a second insulating layer portion laminated on the first insulating layer portion, and having a cavity penetrating a portion of the second insulating layer portion and the first insulating layer portion,
A circuit layer at least partially embedded in the second insulating layer, and
Including a metal pattern layer arranged along the edge of the cavity within the second insulating layer,
The insulating layer has a first surface constituting the bottom surface of the cavity and a second surface constituting the side surface of the cavity,
A circuit board, wherein the metal pattern layer is exposed from the insulating layer on the second surface and includes a plurality of metal layers containing different metals. In the first paragraph,
A circuit board wherein the plurality of metal layers have different etching selectivities for the same material. In the first paragraph,
A circuit board, wherein the metal pattern layer is disposed in a corner region of the cavity to connect the first surface and the second surface. In the first paragraph,
A circuit board, wherein the metal pattern layer comprises a first metal layer containing copper, and a second metal layer disposed on the first metal layer and containing nickel. In paragraph 4,
The circuit layer includes a first conductive layer disposed on the first insulating layer portion, and a second conductive layer laminated on the first conductive layer,
A circuit board, wherein one side of the second conductive layer is disposed on substantially the same plane as one side of the second metal layer. In paragraph 4,
A circuit board, wherein the circuit layer includes a first conductive layer comprising the same material as the first metal layer. In the first paragraph,
A circuit board further comprising a first pad exposed from the second insulating layer portion on the first surface. In paragraph 7,
The circuit board, wherein the first pad is partially embedded in the insulating layer. In paragraph 7,
A circuit board, wherein, with respect to the first insulating layer portion, the surface of the first pad exposed from the second insulating layer portion is located further away than the surface of the circuit layer facing the first insulating layer portion. In the first paragraph,
A circuit board, wherein the thickness of the first pad is smaller than the thickness of the circuit layer in the above-mentioned stacking direction. In the first paragraph,
A circuit board, wherein the circuit layer includes a first conductive layer containing copper, and a second conductive layer disposed on the first conductive layer. In paragraph 11,
A circuit board, wherein the first conductive layer includes an electroless plating layer. In the first paragraph,
A circuit board, wherein the metal pattern layer is positioned concavely inward from the second surface. In the first paragraph,
A circuit board further comprising a first pad exposed from the insulating layer on one surface of the insulating layer where the cavity is located. A first stopper layer is formed by including a first metal on the first insulating layer,
Forming a second stopper layer on the first stopper layer, including a second metal different from the first metal,
Forming a first pad on the second stopper layer,
A second insulating layer is formed by laminating the first pad on the first insulating layer so that the first pad is buried,
A first cavity forming portion is formed by removing the first insulating layer portion on the first stopper layer by an area smaller than the area of the first stopper layer,
A second cavity forming portion is formed by removing the exposed portion within the first cavity forming portion of the first stopper layer, and
A method for manufacturing a circuit board, wherein a cavity is formed by removing an exposed portion within the second cavity forming portion of the second stopper layer. In paragraph 15,
Forming the second stopper layer is as follows:
A method for manufacturing a circuit board, comprising forming a second stopper layer including a second metal having a different etching selectivity from the first metal for the same material. In paragraph 15,
Forming the above second cavity forming part is:
A method for manufacturing a circuit board, comprising removing an exposed portion of the first stopper layer and forming a remaining first metal layer along an edge of the first cavity forming portion. In paragraph 17,
Forming the above cavity is,
A method for manufacturing a circuit board, comprising removing an exposed portion of the second stopper layer and forming a remaining second metal layer along an edge of the second cavity forming portion. In paragraph 18,
Forming the above first stopper layer is:
Comprising forming the first stopper layer comprising copper,
Forming the second stopper layer is as follows:
A method for manufacturing a circuit board, comprising forming the second stopper layer containing nickel. In paragraph 15,
Further comprising forming a circuit layer on the first insulating layer,
Forming the above circuit layer is,
Forming a first conductive layer on the first insulating layer, and
A method for manufacturing a circuit board, comprising forming a second conductive layer on the first conductive layer so as to have one surface of substantially the same level as one surface of the second stopper layer. In paragraph 20,
Forming the above first challenge layer is:
A method for manufacturing a circuit board, comprising forming the first conductive layer by including the same material as the first stopper layer. In paragraph 15,
Further comprising forming a circuit layer on the first insulating layer,
Forming the above first pad is:
A method for manufacturing a circuit board, comprising forming a first pad so that a surface exposed from the second insulating layer portion of the first pad has a higher level than a surface facing the first insulating layer portion of the circuit layer. In paragraph 15,
Further comprising forming a circuit layer on the first insulating layer,
Forming the above first pad is:
A method for manufacturing a circuit board, comprising forming the first pad so that the thickness in the lamination direction is smaller than the thickness of the circuit layer. In paragraph 15,
A method for manufacturing a circuit board, further comprising forming a surface treatment layer on the first pad. In paragraph 15,
Further comprising forming a circuit layer on the first insulating layer,
Forming the above circuit layer is,
Forming a first conductive layer including copper, and
A method for manufacturing a circuit board, comprising forming a second conductive layer on the first conductive layer. In paragraph 25,
Forming the above first challenge layer is:
A method for manufacturing a circuit board, comprising forming an electroless plating layer. In paragraph 15,
A method for manufacturing a circuit board further comprising etching the first stopper layer to form a first metal layer so as to be recessed inward from the side surface of the second insulating layer portion. In paragraph 27,
A method for manufacturing a circuit board further comprising etching the second stopper layer to form a second metal layer so as to be recessed inward from the side surface of the second insulating layer portion. In paragraph 15,
Forming an insulating layer including the first insulating layer portion and the second insulating layer portion and having the cavity formed on one surface, and
A method for manufacturing a circuit board further comprising forming a second pad on one surface of the insulating layer so as to be exposed from the insulating layer. A circuit board having a cavity and including a pad portion exposed from an insulating layer within the cavity, and
Including an electronic component mounted within the cavity to be connected to the pad portion,
The above circuit board,
An insulating layer having the above cavity,
a circuit layer at least partially embedded in the insulating layer, and
Including a metal pattern layer arranged along the edge of the cavity within the insulating layer,
The insulating layer has a first surface forming the bottom surface of the cavity, and a second surface forming the side surface of the cavity,
An electronic component package, wherein the metal pattern layer is exposed from the insulating layer on the second surface and includes a plurality of metal layers containing different metals. In paragraph 30,
An electronic component package, wherein the metal pattern layer comprises a first metal layer comprising copper, and a second metal layer disposed on the first metal layer and comprising nickel.