KR20250133974A - Hardware mechanism for universal synchronization of communications in SOCs - Google Patents

Abstract

A method and system, including a computer-readable medium, for implementing a hardware synchronization unit in an integrated circuit, such as a system-on-chip ('SoC') of a mobile device, are described. The synchronization unit is configured to create a global synchronization object used to control and manage one or more synchronization events in the SoC. The synchronization unit determines context states by referencing the global synchronization object. Each context state corresponds to an individual IP device among a plurality of IP devices on the SoC. The synchronization unit creates register values representing each context state and manages the execution of synchronization events based on the global synchronization object and the register values. The synchronization events involve each IP device and are executed concurrently with heterogeneous operations performed using the IP devices in the SoC.

Description

Hardware mechanism for universal synchronization of communications in SOCs

This specification generally relates to a mechanism for general synchronization of communication between IP blocks of a system-on-chip ('SoC').

Modern computing systems typically include a wide variety of computational processing units, each offering different computational capabilities and tradeoffs. Efficient execution of a given computational task often involves parsing the computation into meaningful subtasks, or workloads, that are mapped to the computing system's available processor cores. Computations can be parsed and mapped based on suitability criteria such as processor capability, performance, and power. This overall process of assigning portions of a computation to appropriate processor resources is commonly referred to as heterogeneous computing.

At least one processor core of a computing system may be an intellectual property block (IP block), each of which executes a portion of the computational operations for different multimedia use cases. An example use case may involve processing image data captured by a mobile device's camera. Using heterogeneous computation to process image data requires synchronization between the processor cores that each receive assignments of subtasks. The resource overhead required to implement this synchronization is typically significant relative to the computational work itself. These resource requirements create bubbles in the data processing pipeline, which delay or degrade operations.

This specification describes a hardware mechanism used to universally synchronize communication between IP blocks (or devices) in a system-on-chip ('SoC'). The hardware mechanism may be an exemplary synchronization module implemented as a separate processor, a floating role migrating compute element, or both. For example, the hardware mechanism may be used to synchronize a subset of communications in the SoC based on synchronization objects passed between IP devices and register values representing the context states of the IP devices.

The synchronization module may include or even represent a hardware synchronization unit having various processor resources for implementing general-purpose IP synchronization, including one-to-many and many-to-many synchronization between IP devices of the SoC. The resources of the hardware synchronization unit include control logic and memory for creating, tracking, and managing objects or data values corresponding to synchronization events executed in the SoC. More specifically, the memory may include static random-access memory ('SRAM') circuitry as well as control and status registers ('CSR').

The hardware synchronization unit is configured to create a global synchronization object used to control and manage one or more synchronization events of heterogeneous computations running on the SoC. The hardware synchronization unit can create a global synchronization object in response to receiving a request from an IP device of the SoC. For example, the global synchronization object can be created based on a request from an application (e.g., a camera) that generates data for processing by multiple IP devices of the SoC. Each IP device can be a processor (or processor core) of an IP block on the SoC.

To process data, the SoC initiates heterogeneous computational operations, where each of multiple IP devices is responsible for a specific operation of the heterogeneous operation. For example, the data may be image data, and the heterogeneous computation may include: i) an inference operation for performing face recognition on the image data, and ii) a scaling operation for performing post-processing on the image data. The heterogeneous computation involves some (or all) of the multiple IP devices on the SoC and requires synchronization of specific computational steps between the IP devices.

The synchronization module configures a global synchronization object as a first-class object so that the hardware synchronization unit can implement the synchronization required for each IP device of the SoC in a general manner. The hardware synchronization unit uses the global synchronization object to control and manage synchronization events that facilitate the execution of heterogeneous operations in the SoC. The hardware synchronization unit determines context states by referencing the global synchronization object. At least one context state corresponds to an individual IP device on the SoC, and the hardware synchronization unit uses its CSRs to store values representing the context states for each of the IP devices.

As heterogeneous operations are executed, the hardware synchronization unit generates and iteratively updates register values for each context state, and manages the execution of synchronization events based on the global synchronization object and these register values.

One aspect of the subject matter described herein can be implemented as a computer-implemented method performed in a system-on-chip ('SoC') of a user device using a hardware synchronization unit of the SoC. The method includes creating, by the hardware synchronization unit, a global synchronization object used to control and manage one or more synchronization events in the SoC. The hardware synchronization unit determines context states by reference to the global synchronization object. Each context state corresponds to an individual IP device among a plurality of IP devices on the SoC. The method includes creating, by the hardware synchronization unit, a plurality of register values representing each of the context states corresponding to each individual IP device; and managing, by the hardware synchronization unit, execution of synchronization events involving each of the IP devices based on the global synchronization object and the register values.

These and other implementations may each optionally include one or more of the following features. For example, in some implementations, the step of creating a global synchronization object includes: receiving, by a hardware synchronization unit, a global synchronization request from a first IP device; and creating, by the hardware synchronization unit, a global synchronization object based on the global synchronization request from the first IP device. The step of creating the global synchronization object includes generating, by the hardware synchronization unit, a control signaling that initiates execution of synchronization events in the SoC. The control signaling may include a first synchronization control signal that conveys the global synchronization object to the first IP device.

In some implementations, the method further comprises detecting secondary global synchronization objects generated by a hardware synchronization unit based on control signaling that initiates execution of synchronization events in the SoC. Each of the secondary global synchronization objects corresponds to a universal/global synchronization ID that is propagated to an individual IP device among the plurality of IP devices. One or more of the secondary global synchronization objects can be communicated between at least two of the plurality of IP devices to execute one or more of the synchronization events, and can be used to execute individual synchronization events for distinct data processing operations that are performed concurrently to process event data associated with an application executing on the user device.

In some implementations, the method further comprises synchronizing a subset of communications in the SoC based on register values each representing a context state in the hardware synchronization unit and a global synchronization object, using a hardware synchronization unit. The method may further comprise associating each of the context states with an individual IP device among the plurality of IP devices and a synchronization activity corresponding to the IP device, using the global synchronization object.

For each of the plurality of IP devices, the synchronization activity may include: i) a first synchronization event representing a signal event; and ii) a different second synchronization event representing a wait event. The method may further include detecting, in the SoC, a request to process event data associated with an application running on the user device. In some implementations, the synchronization events are executed in the SoC concurrently with data processing operations of each IP device used to process the event data.

Other embodiments of these and other aspects include corresponding systems, devices, and computer programs encoded on a computer storage device, configured to perform the actions of the method. The system of one or more computers may be configured by software, firmware, hardware, or a combination thereof installed on the system that, when in operation, causes the system to perform the actions. The one or more computer programs may be configured to have instructions that, when executed by a data processing device, cause the device to perform the actions.

The subject matter described herein can be implemented in specific embodiments to achieve one or more of the following advantages:

The disclosed technology provides a general-purpose hardware synchronization mechanism across multiple (or all) IP devices in an exemplary computing system. The general-purpose aspect of the mechanism allows a single IP device to simultaneously (e.g., simultaneously) signal an event or computational task to multiple IP devices. For example, a first processor generating image data may use a hardware synchronization unit to simultaneously signal i) a second processor applying a machine-learning (ML) algorithm to the image data, and ii) a third processor performing digital signal processing on the image data.

The hardware synchronization mechanism involves a synchronization module that can create global synchronization objects and implement them as first-class objects. For example, a global synchronization object consists of a native identity that natively supports specific synchronization operations without requiring an application processor (AP) to be integrated into the IP device to decode or process synchronization instructions/commands. Therefore, the global synchronization object does not need to be coded or defined in a specific programming language, which simplifies design efforts and minimizes the resource overhead required to implement a hardware synchronization unit in an integrated circuit.

In this regard, the hardware synchronization mechanism provides universal/shared synchronization semantics that can be used and utilized by various IP devices on the SoC. The hardware synchronization mechanism can interact with a source IP device to impart meaning to a specific synchronization object. The hardware synchronization mechanism can create multiple synchronization objects, each with a global identity, so that the synchronization objects can be used by the source IP device to signal events to multiple other IP devices. The global identity of the synchronization objects is achieved based on a global representation maintained by the proposed hardware mechanism.

For example, a hardware synchronization mechanism may include control logic used to establish a parameter/data value, e.g., an integer '10', as a sync_ID. This sync_ID may be a global identifier for a synchronization object (or a global synchronization object) such that the parameter value of '10' represents the same synchronization object on different IP devices or executing processors of a SoC. The hardware synchronization mechanism may ensure that all processors within the system recognize '10' as the same/global identity for a given synchronization object identified by its data value.

Details of one or more embodiments of the subject matter described herein are set forth in the accompanying drawings and the description below. Other potential features, aspects, and advantages of the present invention will become apparent from the description, drawings, and claims.

FIG. 1 is a block diagram of an exemplary computing system having at least one SoC.
Figure 2a illustrates an exemplary hardware synchronization unit.
Figure 2b illustrates exemplary code for creating a global synchronization object.
FIG. 3 is a block diagram illustrating exemplary routing of synchronization signaling between IP blocks using the hardware central synchronization unit of FIG. 2.
Figure 4 is an exemplary process for synchronizing communication between IP blocks in the system of Figure 1.
FIG. 5 is a flowchart representing an exemplary synchronization procedure implemented in the SoC of FIG. 1.
Similar reference numbers and designations in various drawings indicate similar components.

FIG. 1 is a block diagram of an exemplary computing system (100) including a system-on-chip (102) ['SoC (102)']. In some implementations, the system (100) includes multiple SoCs. The SoC (102) includes a central processing unit (104) ['CPU (104)'], a shared memory (106) ['memory (106)'], a synchronization module (108) ['sync module (108)'], and IP/circuit blocks (110).

The CPU (104) may be a general-purpose CPU (e.g., a single or multi-core CPU). The CPU (104) generates one or more indicators, such as an app-launch indicator or a function call, that are triggered in response to executing or launching an application on the user device. For example, the application may be a camera application that generates image data using an imaging sensor, or a game application that requires significant memory and graphics processing resources to render the game's graphic content. The CPU (104) also generates one or more application values, such as pixel values or frame rates. The application values may be associated with a function call, may describe an event that occurs during the execution of the application, or both.

Memory (106) is system memory, shared memory, or both. In the example of FIG. 1, memory (106) is depicted external to circuit block (110). However, memory (106) may include portions of memory that are i) specific to circuit block (110), ii) external to circuit block (110), or iii) both. Memory (106) may be random access memory of SoC (102), such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), or double data rate (DDR) SDRAM.

In some implementations, the memory (106) is configured as a shared scratchpad memory that supports parallel access of its memory resources by two or more processors of the circuit (110). The memory (106) may also include various other types of memory, such as high bandwidth memory (HBM), narrow bandwidth memory (e.g., for storing 8-bit values), wide bandwidth memory (e.g., for storing 16-bit or 32-bit values), etc.

The synchronization module (108) is implemented in hardware and software. Aspects of the synchronization module (108) may also be implemented as firmware of the SoC (102) or firmware of a device of the SoC (102), such as the CPU (104). The synchronization module (108) includes a hardware synchronization unit (120) implemented in hardware and software. For example, the hardware synchronization unit (120) includes memory resources implemented in hardware (e.g., flip-flops, registers, buffers, etc.) and control logic implemented in software (e.g., programmed code). The hardware synchronization unit (120) is described in more detail below with reference to the example of FIG. 2.

One or more aspects of the synchronization module (108) may be implemented as software routines (or modules) of the CPU (104) that utilize one or more hardware resources of the CPU (104), such as registers, buffers, etc. In some implementations, the CPU (104) is configured as an instruction and vector data processing engine that processes data obtained from a system memory of the SoC (102), such as the memory (106).

As described in detail below, the synchronization module (108) is configured to generate global synchronization objects (122) as well as control signaling and associated data values used to synchronize events and communications between devices of the system (100). The devices include special purpose processing devices such as processors, processor cores, or individual IP devices of a circuit block (110).

The circuit block (110) may include an image signal processor (ISP) (112), a tensor processing unit (TPU) (114), a digital signal processor (DSP) (116), and a graphics processing unit (GPU) (118). The circuit block (110) is alternatively referred to as an IP block (110), where an IP block may include one or more proprietary hardware elements. For example, each of the ISP (112), the TPU (114), the DSP (116), and the GPU (118) may be a separate proprietary IP block (or IP device) of a particular entity or device manufacturer.

The synchronization module (108) dynamically controls and manages one or more synchronization events executed in the SoC (102) to support heterogeneous computational operations, utilizing operations performed by the hardware synchronization unit (120). More specifically, the synchronization module (108) is configured to generate control signaling (124) and, using one or more individual signal values of the control signaling (124), to arrange and synchronize operations between two or more processing units included in the IP block (110), the CPU (104), or both. In some implementations, each processor (e.g., an ISP, a DSP, a TPU, a GPU, or a CPU) of the SoC (102) includes multiple cores, and the synchronization module (108) may generate control signaling (124) to synchronize or otherwise manage events in each core of the processors.

In the example of FIG. 1, the system (100) and the SoC (102) are integrated circuits of exemplary user/client devices, consumer electronic devices, or mobile devices, which may each include items such as a smartphone (130a), a tablet (130b), a laptop (130c), a smartwatch, or a wearable device (130d). The devices may also include other items such as an e-notebook, a netbook, a smart speaker, or a mobile computer. In some implementations, the system (100) and the SoC (102) are integrated circuits of a desktop computer, a network server, or a related cloud-based asset.

FIG. 2A illustrates an exemplary hardware central synchronization unit ('CSU') (120) used to universally synchronize communication between devices of the SoC (102), such as IP devices of the circuit block (110). The hardware synchronization unit (120) includes various resources for implementing universal IP synchronization, including one-to-many and many-to-many synchronization, between IP devices of the SoC (102).

The resources of the hardware synchronization unit include control logic (202) and memory for generating, tracking, and managing synchronization objects or data values corresponding to synchronization events executed in the SoC. More specifically, the hardware synchronization unit (120) includes a first memory (204) and a second memory (206). In some implementations, the first memory (204) and the second memory (206) are the same memory. In some other implementations, the first memory (204) and the second memory (206) are different memory circuits/units.

The first memory (204) may include a combination of SRAM circuits and CSR circuits, while the second memory (206) may include one or more SRAM circuits. The first memory (204) may include one or more CSR groups (205) ('register groups (205)'), wherein each register group (205) includes a group of CSRs (or other registers), such as two or more 8-bit registers, 12-bit registers, 16-bit registers, 32-bit registers, etc. In the example of FIG. 2, the first memory (204) includes three register groups (205), but the first memory (204) may include more or fewer register groups (205). In some implementations, the first memory (204) includes a register group (205) for each IP device of the SoC (102).

Typically, for a given heterogeneous operation, the global state of one or more synchronization objects (or syncs) is well defined in the structured memory of SRAM and the register resources of a hardware synchronization unit (120). The hardware synchronization unit (120) uses the control logic (202) and memory resources (204, 206) to maintain the global synchronization states of multiple devices/IP devices of the SoC (102). In some implementations, the hardware synchronization unit (120) is a separate processor of the SoC (102), the synchronization module (108), or both.

For example, the control logic (202) may be a processor or logic unit that causes the hardware synchronization unit (120) to maintain the state (e.g., context state) of a plurality of global synchronization objects. In the example of FIG. 2B, the control logic (202) may create and/or define a synchronization object or a global synchronization object using the exemplary code (255). The control logic (202) may also generate control signaling to broadcast synchronization information to consumer IP devices when a producer IP device satisfies synchronization.

In some instances, a synchronization may be "satisfied" when an IP device associates a synchronization object with a specific condition. The IP device may associate the specific condition based on analysis or determination made by the IP device's driver software. The specific condition may be that IP device A (the producer) has completed writing data to a buffer in the system. When, or immediately after, the condition occurs, the synchronization will be signaled by the corresponding IP device A, thereby satisfying the synchronization (e.g., signaling the synchronization).

A synchronization unit (120) is configured to maintain a global state for synchronization activities spanning two or more devices of a SoC (102), such as a processor, processor core, processing unit, IP device, or circuit block (110). The hardware synchronization unit (120) is configured to maintain these global synchronization states without requiring or implementing software layer conversions for synchronization signals generated and transmitted between the devices.

The hardware synchronization unit (120) determines context states by referencing a global synchronization object used to control and manage synchronization events in the SoC (102). For example, the control logic (202) may detect and/or analyze incoming and outgoing synchronization signals (or values) and determine context states based on such synchronization signals. At least one context state corresponds to an individual device on the SoC (102). In some implementations, each context state corresponds to an individual IP device among a plurality of IP devices on the SoC (102).

For example, the hardware synchronization unit (120) may determine a separate context state for the ISP (112), a separate context state for the TPU (114), a separate context state for the DSP (116), and a separate context state for the GPU (118). In some implementations, the hardware synchronization unit (120) uses the contexts and context states to allow concurrent access between multiple IP devices and to maintain synchronization integrity for these concurrent accesses. For each client or IP device, a context provides an abstraction that each IP device operates within its own synchronization context. Generally, each context may be associated with a set of registers necessary to perform operations on a particular synchronization object or set of synchronization objects.

In some implementations, each context state is represented by a combination of values stored across the first memory (204) and the second memory (206). For a given synchronization event, the IP device may first obtain a context assignment from the hardware synchronization unit (120), create one or more synchronization objects, and then wait on the synchronization objects or signal the synchronization objects to other IP devices. In some implementations, the client IP driver of the IP device is used to obtain the context assignment.

Each context may have a set of CSRs for implementing the application programming interface (API) of the hardware synchronization unit (120). For example, a read-only CSR is used to acquire a new synchronization, while a write-only CSR is used to release synchronization. In some implementations, the control logic (202) determines the allocation and/or assignment of registers such that a context representing synchronization events for an IP device has a corresponding set of CSRs for performing operations associated with such synchronization events. For clarity, a context may include one or more context states, where each context state may represent an attribute or detail of a synchronization event, such as a synchronization signal event or a wait event.

The synchronization unit (120) generates register values corresponding to (or representing) each of the context states. For example, each context state for the IP device may be captured using a set of register values stored in the first memory (204) and one or more bookkeeping data values of the second memory (206). The hardware synchronization unit (120) includes interface connections (220-1, 220-2) representing interface controls of the hardware synchronization unit (120). The hardware synchronization unit (120) uses the interface connection (220-1) to detect, acquire, or otherwise receive incoming synchronization signals. In this regard, the hardware synchronization unit (120) uses the interface connection (220-2) to transmit, provide, or otherwise convey outgoing synchronization signals.

The control logic (202) can detect and analyze the incoming and outgoing synchronization signals and generate corresponding register values based on the analysis. The hardware synchronization unit (120) uses one or more of the CSRs of the first memory (204) to store register data values representing (or expressing) context states for each of the devices.

In the example of FIG. 2, the hardware synchronization unit (120) includes a register (240) for storing data for an acquisition 'acquire' parameter, a register (241) for storing data for a release 'release' parameter, a register (242) for storing data for a signal 'signal' parameter, a register (243) for storing data for a wait 'wait' parameter, a register (244) for storing data for a notification queue 'NotificationQ' parameter, and a register (250) for storing data for an 'IRQ'.

An exemplary synchronization operation using at least registers (240, 241, 242, and 243) will now be described.

An IP device A ('IP_A') may request a synchronization object for a given operation. For example, IP_A may need to configure a synchronization object so that as soon as IP_A completes a given task on a portion of data, IP device B ('IP_B') can be notified to perform additional work on that portion of data. The requested synchronization object may be triggered by a software driver or other operational logic of IP device A. IP_A initiates a read of register (240) to compute, generate, or otherwise obtain an identifier/ID (i.e., sync_ID) of a newly created synchronization object. In some implementations, IP_A obtains the ID based on the command 'sync my_new_sync = csu_contex0->acquire'.

The system (100) initiates a call to IP_B and passes a new sync in such a way that IP_B waits for a sync state as a dependency while IP_A performs a given task on the data. For example, the system (100) may initiate a call to the driver or other computational logic of IP_B using the hardware synchronization unit (120). The hardware synchronization unit (120) may use the register (241) to specify the register IDs used by IP_A and IP_B during the synchronization context covering processing such partial data. In some implementations, the system (100) initiates a call to IP_B and passes a new sync based on the command 'process_IP_B(work, my_new_sync)'.

IP_A signals synchronization by writing its corresponding synchronization ID to register (242) using hardware synchronization unit (120). Interaction between IP_A and hardware synchronization unit (120) may be initiated or managed by firmware and/or hardware logic supported by IP_A. In some implementations, system (100) signals synchronization based on command 'IP_A_Buffer_done_IRQ_event: csu_contex0->signal = my_new_sync' and writes the corresponding synchronization ID. System (100) may initiate processes involving IP_B based on command 'process_IP_B(work, sync)'. In general, IP_A and IP_B may be any of the devices of circuit block (110). Additionally, 'csu_context' represents a set of registers representing the client context in hardware synchronization unit (120).

The hardware synchronization unit (120) causes IP_B to wait for a dependency on IP_A by writing a sync_ID to the register (243). In some implementations, the system (100) causes IP_B to wait for a dependency based on the command 'csu_context1->wait = sync'. IP_B responds by performing additional 'work' on a portion of the data when the synchronization (sync) is signaled or after receiving a notification indicating that the synchronization is complete. For example, IP_B may perform or execute this additional 'work' dependent on the synchronization based on the command 'while ((notified_sync = csu_context1->notificationQ) != 0)'. The command may be executed using the IRQ_Handler of the hardware synchronization unit (120).

In some implementations, there may be multiple synchronizations in flight for the same context. This means that when a CSU IRQ occurs, there may be more than one synchronization notified in the notification queue. In other words, for the while loop 'while ((notified_sync = csu_context1->notificationQ) != 0)', the owner of csu_context1 checks which of its pending work items depends on the notified synchronization. In this example, the owner is IP_B. If IP_B is waiting for only one synchronization, the while loop will return non-zero only once.

In the above and other examples, register (240) is a read-only (RO) register, while registers (241, 242, and 243) are write-only registers. In some implementations, data values stored in register (240) are used to 'acquire' or create a synchronization object, a corresponding sync_ID, or both. Data values stored in register (244) are used to notify the IP device of activity associated with a particular synchronization object. For example, TPU (114) may be waiting on ten different synchronization objects, and a notification register queue is used to notify TPU (114) that synchronization objects 1, 3, and 5 have been signaled.

IP devices may use or read data values for IRQs stored in registers (250) to obtain notification from the hardware synchronization unit (120) regarding a particular synchronization object or synchronization event. For example, the hardware synchronization unit (120) may use an IRQ in registers (250) to notify the TPU (114) that an event or action has occurred regarding a synchronization or synchronization object for which the TPU (114) may have been waiting.

More specifically, the hardware synchronization unit (120) is configured to track signaled synchronizations for each context and may use IRQs in the register (250) to facilitate such tracking. When the IP device or a client of the context reads the register (244), each read of the register (244) returns the sync_ID of the corresponding synchronization that was signaled. In some implementations, each read of the register by the IP device will also clear the returned sync_ID from the notification queue. When there are no more signaled synchronizations in the notification queue, any read of the register (244) will return '0'.

The hardware synchronization unit (120) can identify one or more registers of the first memory (204) that are allocated or assigned (or have been allocated or assigned) for a given context by referencing a particular IP device. The hardware synchronization unit (120) interacts with the IP device to allow the IP device to obtain register IDs for the given context and to release register IDs for the context. Each IP device communicates information about a synchronization event to the hardware synchronization unit (120) by writing or updating values to the CSRs of the first memory (204) assigned to the IP device for the given synchronization context.

The second memory (206) is used to store a bookkeeping table containing various 'bookkeeping' values for one or more contexts, context states, or both. The second memory (206) can store the bookkeeping values using a row configuration, where a given row is used or assigned to store one or more values for a context or context state. For example, the values are stored in a 'bookkeeping' table containing one or more entries (206-0, 206-1, 206-n). In some implementations, the bookkeeping table contains n entries (e.g., rows) (206-n), where n is an integer greater than 1.

A bookkeeping table is a global state table that maintains status information for each synchronization object, including global synchronization objects associated with one or more synchronization events. The bookkeeping table may include an entry (e.g., a row entry) for each synchronization object obtained from or generated by the hardware synchronization unit (120). Each entry or row in the bookkeeping table reflects status information for each synchronization object, indicating how many synchronization objects are active or available, how many synchronization object entries are available in the bookkeeping table, and how many synchronization object entries have already been obtained.

Each data value for a synchronization object entry may correspond to a synchronization event, an IP device, or both. The control logic (202) generates a bookkeeping table based on data values acquired or read from the first memory (204). For example, the control logic (202) may extract, read, or obtain data values for a register group (205) and use some (or all) of these data values to generate or populate entries in a bookkeeping table stored in the second memory (206).

In the example of FIG. 2, to maintain state information for a given synchronization object, the bookkeeping table stores data values for 'sync_ID', 'state', and 'waiter queue'. In other examples, the bookkeeping table may store more or fewer data values to maintain state information for a given synchronization object. 'sync_ID' identifies the synchronization object, 'state' represents an exemplary state of the synchronization object, and 'waiter queue' represents a queue of clients or devices that may be waiting on the synchronization object. Exemplary 'states' of the synchronization object may include: i) free, indicating that the synchronization object is freely signalable; ii) unsignalled, indicating that the synchronization object is not signaled (or has not been signaled); iii) signaled, indicating that the synchronization object is signaled (or has been signaled); and iv) error, indicating an error condition associated with the synchronization object.

The synchronization module (108) may track and maintain various parameters for each synchronization object. For example, the hardware synchronization unit (120) may use the control logic (202) to determine a timestamp (e.g., a global timestamp) indicating the last state change of the synchronization object. The control logic (202) may implement a counter that counts or tracks the number of times the synchronization object (or synchronization event) has been signaled. In some implementations, the counter parameter is particularly relevant to recurring synchronization events.

As described below, the control logic (202) may configure the repeating synchronization using combinational logic including AND, OR, XOR, or other related logical operators. The control logic (202) may also implement a reference count to track existing references to the synchronization. The control logic (202) may use the reference count to trigger a change in the state to 'free' when the reference count value is reset to '0'.

The hardware synchronization unit (120) is configured to generate composite synchronization objects based on the composition or combination of two or more synchronization objects. More specifically, the control logic (202) can use logical operators to generate a new (or composite) synchronization object from two distinct synchronization objects. For example, if the designer is interested in an event that involves signaling of both synchronization objects A and B, the control logic (202) can generate a new synchronization object by ANDing synchronization objects A and B using the ADD operator. In another example, if the designer is interested in an event that involves signaling of any of synchronization objects A, B, and C, the control logic (202) can then generate a new synchronization object by ORing synchronization objects A, B, and C using the OR operator.

In another example, the hardware synchronization unit (120) may create ten different synchronization objects representing ten different images or audio samples. The ten images may represent a single stream with different image sizes. The SoC (102) may want to perform simultaneous operations on all ten images. Therefore, instead of performing a one-to-one wait operation on each image, the hardware synchronization unit (120) may use an AND operator to combine all ten synchronization objects to create a new synchronization object representing all ten images. The hardware synchronization unit (120) may then implement a more streamlined single wait event using the single composite synchronization object.

In addition to synthetic synchronization objects, the hardware synchronization unit (120) may implement certain custom or specialized synchronization objects. In some implementations, the hardware synchronization unit (120) may implement conditional synchronization objects, counter-based synchronization objects, QoS counter-based synchronization objects, and timer-based synchronization objects. For example, the control logic (202) may create a conditional synchronization object that is triggered only if/when a certain condition is met, where the condition may be predefined or determined on the fly.

For example, the condition can be based on a register value of a CSR of the SoC (102) or the synchronization module (108) or a specific processing event. The control logic (202) can also create conditional synchronization objects using AND, OR, and XOR operators. In some examples, the control logic (202) can create timer-based synchronization objects that are triggered after a specific time value has elapsed or after a specific time duration has expired. In some examples, the control logic (202) can create QoS counter-based synchronization objects that are triggered after detecting a specific value in a program counter or upon reading a specific quality of service (QoS) count value in a counter register. For example, the QoS value can be based on the number of bytes or data values for a given service parameter, such as the number of frames per second for a graphics processing operation.

In some implementations, the hardware synchronization unit (120) provides data values for updating and maintaining a bookkeeping table using information represented in a data block (210). The information in the data block (210) may represent data values transferred from the first memory (204) to the second memory (206). The values in the data block (210) may be stored or maintained in the hardware synchronization unit (120). For example, the data block (210) may be a buffer containing a subset of register values for a context of an IP device. The control logic (202) may read or extract values from the data block (210) and use those values to update status information for a synchronization object assigned to the IP device (or context) in a corresponding row of the bookkeeping table.

In some implementations, the synchronization module (108) and/or the hardware synchronization unit (120) are floating role migrating compute elements of the SoC (102). An aspect of the hardware mechanism that integrates the floating role elements will be to migrate between different processing devices that may be included in the active set of IP devices on the SoC (102). The hardware synchronization unit (120) may include logic (e.g., software/firmware) and control elements that enable the synchronization role to migrate or float between the IP devices of the circuit block (110). For example, to enable floating role synchronization functionality in a given IP device, the hardware synchronization unit (120) may implement a separate portion of the control logic and one or more interface connections in that IP device.

FIG. 3 is a block diagram (300) of an exemplary communication involving a hardware synchronization unit (120) and IP blocks of an SoC (102). In general, the example of FIG. 3 illustrates a high-level context of a central synchronization unit ('CSU') represented by the hardware synchronization unit (120). In this example, the CSU can be viewed as a synchronization router between computational IPs, enabling many-to-many synchronization in the most efficient and uniform manner.

As described above, the synchronization module (108) dynamically controls and manages synchronization events in the SoC (102) using operations performed by the central hardware synchronization unit (120). The synchronization events are controlled and executed to support heterogeneous operations. More specifically, the hardware synchronization unit (120) may generate individual signal values of the control signaling (124) to, for example, arrange and synchronize operations between i) IP devices of the IP block (110) and/or ii) between the CPU (104) and the circuit block (110).

In some implementations, the synchronization unit (120) generates control signaling (124) to synchronize or otherwise manage events in each IP device. For example, the control signaling (124) may include at least one control value for synchronizing events in the ISP (112), at least one control value for synchronizing events in the TPU (114), at least one control value for synchronizing events in the DSP (116), and at least one control value for synchronizing events in the GPU (118). Each of these control values may represent a global synchronization object, may be used to convey a global synchronization object to the IP device, or may be both.

The hardware synchronization unit (120) (or synchronization module (108)) uses control signaling (124) to synchronize events among multiple IP devices in a general manner for each IP device of the SoC (102). For example, the hardware synchronization unit (120) may create a global synchronization object included in the control signaling (124) used to control and manage synchronization events of heterogeneous operations running on the SoC (102).

The hardware synchronization unit (120) can create a global synchronization object in response to receiving a request from an IP device of the SoC (102). For example, the global synchronization object can be created based on a request (302) from an IP device or application (e.g., a camera) that generates data for processing by multiple IP devices of the SoC. Each IP device can be a processor (or processor core) of an IP block (110) on the SoC (102). In the example of FIG. 3, the hardware synchronization unit (120) can create a global synchronization object based on a 'GetSync' request (302) from an ISP (112).

A global synchronization object may be returned using one or more signal values of control signaling (124). In the exemplary implementation of FIG. 3, the global synchronization object is returned or communicated to an exemplary IP device (e.g., an ISP (112)) as a 'sync_ID' signal (304). This sync_ID signal (304) represents a global sync ID for tracking a subset of synchronization events in the SoC (102). For example, the sync_ID signal (304) may be used by the hardware synchronization unit (120) as a basis for tracking synchronization events associated with a particular heterogeneous operation.

In some implementations, control signaling (124) is used to trigger a first IP device to create a global synchronization object, which the first IP device then passes to a different second IP device to synchronize events between the first IP device and the second IP device. The first IP device may use control signaling (124) to signal a computational action or event (e.g., a 'wait' event) to more than one IP device. In the example of FIG. 3, the ISP (112) may create one or more secondary global synchronization objects based on the control signaling (124).

Secondary global synchronization objects may be represented by a 'sync_ID' signal (306). This 'sync_ID' signal (306) may indicate one or more synchronization events (or activities) of a heterogeneous operation. The synchronization events may include a 'signal event' and a 'wait event'. The hardware synchronization unit (120) may detect and monitor these 'sync_ID' signals via the control interfaces (220-1, 220-2). The hardware synchronization unit (120) may generate and transmit control signals via the control interface (220-2) to notify exemplary IP devices such as the TPU (114) and the DSP (116). The control signaling may be associated with a 'wait event'.

The hardware synchronization unit (120) can detect one or more secondary global synchronization objects generated based on control signaling (124) that initiates execution of synchronization events in the SoC (102). The secondary global synchronization objects can be waiting event signals or notification signals corresponding to a universal synchronization ID that is propagated to individual IP devices of the SoC (102). For example, the hardware synchronization unit (120) can transmit a notification signal (310) indicating a sync_ID for a global synchronization object. The IP devices (114, 116) can each generate individual waiting signals (312) that are propagated to the hardware synchronization unit (120).

In some implementations, the wait signals (312) are secondary global synchronization objects that indicate to the hardware synchronization unit (120) that the TPU (114) and DSP (116) have access to a synchronization handle/object associated with a sync_ID. The secondary synchronization objects may indicate to the hardware synchronization unit (120) that the IP devices are waiting on a synchronization event connected to the primary synchronization object or sync_ID. In some examples, the GPU (118) may consume an image generated by the ISP (112), and the notification signal (310) causes the TPU (114) and DSP (116) to wait for an event from the ISP (112) before accessing a buffer storing the image.

Secondary synchronization objects can be passed between at least two IP devices to execute one or more synchronization events for heterogeneous operations. In some implementations, secondary global synchronization objects are used to execute individual synchronization events for distinct data processing operations, such as inference operations and graphics operations, that are performed concurrently to process event data associated with an application running on the user device (130).

FIG. 4 illustrates an exemplary process (400) for synchronizing communication between IP blocks in the system of FIG. 1. The process (400) may be implemented or executed using the aforementioned system (100) and hardware synchronization unit (120). Accordingly, the description of the process (400) may refer to the computing resources of the aforementioned system (100). In some examples, the steps or actions of the process (400) are enabled by programmed software instructions, firmware instructions, or both. Each type of instruction may be stored in a non-transitory machine-readable storage device and executed by one or more of the processors or other resources described herein.

In some implementations, the steps of process (400) are performed on a hardware integrated circuit to generate machine learning (ML) output, which comprises output from a neural network layer of a neural network implementing one or more ML models. For example, the output may be part of a computation for an ML task or inference workload for generating image processing, speech processing, or image recognition output. As described above, part of the integrated circuit may include a special-purpose neural network processor or hardware ML accelerator configured to accelerate computation for generating various types of data processing output.

Referring back to process (400), the hardware synchronization unit (120) creates a global synchronization object (122) used to control and manage one or more synchronization events in the SoC (402). For example, the hardware synchronization unit (120) may receive a global synchronization request from an application running on a first IP device or a user device (130) of the circuit block (110). The hardware synchronization unit (120) may then create a global synchronization object based on the global synchronization request from the first IP device. The global synchronization request may be expressed as a 'GetSync' request (302).

In some implementations, a synchronization or synchronization object is coupled to an interrupt at creation time to achieve certain efficiencies. The hardware synchronization unit (120) can configure one or more repetitive synchronizations using interrupts. More specifically, the control logic (202) can configure the repetitive synchronizations using combinational logic including AND, OR, XOR, or other related logical operators. For example, when a synchronization object is created or acquired, the control logic (202) can couple the synchronization object to a logical AND/OR combination of interrupts to configure the repetitive synchronization.

The hardware synchronization unit (120) can streamline synchronization operations by using a logical combination of interrupts, resulting in improved efficiency. For example, instead of creating a different synchronization object for each occurrence of an interrupt, the control logic (202) can create a recurring synchronization so that the synchronization is automatically signaled whenever the target interrupt occurs. For example, the synchronization can be automatically signaled whenever the system (100) detects or determines the occurrence of the target interrupt. In this and other examples, an IP device that is a 'waiter client' can distinguish a new synchronization signal (e.g., from a recurring synchronization signal) via the timestamp and/or signal counter parameters described above with reference to FIG. 2 .

The synchronization unit (120) determines a plurality of context states by referencing a global synchronization object (404). For example, for heterogeneous operations (e.g., image or audio processing), the hardware synchronization unit (120) will control and/or manage a plurality of synchronization events. The hardware synchronization unit (120) is configured to analyze incoming and outgoing synchronization signals (or values) for at least some of the synchronization events. Based on the signal analysis, the hardware synchronization unit (120) can determine a plurality of context states for one or more IP devices.

The hardware synchronization unit (120) can associate each of a plurality of context states with i) an individual IP device of the circuit block (110), and ii) a synchronization activity corresponding to the individual IP device. The hardware synchronization unit (120) determines these associations using a global synchronization object, one or more secondary global synchronization objects, or both. More specifically, the hardware synchronization unit (120) can determine these associations based on an analysis of the global synchronization object, the secondary global synchronization objects, signaling communication between the IP devices, or a combination thereof.

The synchronization unit (120) generates register values representing each of the context states (406). In an exemplary heterogeneous operation, for each of a plurality of context states, the hardware synchronization unit (120) may also generate a corresponding set of register values based on analysis of incoming and outgoing synchronization signals. The hardware synchronization unit (120) may also use one or more register values to determine associations between context states and IP devices. In some implementations, the hardware synchronization unit (120) performs two or more operations in parallel to determine context states, determine associations between context states and IP devices, and generate register values.

The synchronization unit (120) manages the execution of synchronization events based on global synchronization objects and register values (408). The synchronization events involve each of the IP devices on the SoC (102) and are executed concurrently with heterogeneous computational operations performed on the SoC (102) using the IP devices of the circuit block (110).

FIG. 5 is a flowchart illustrating an exemplary synchronization procedure (500) implemented in the SoC of FIG. 1. Much like process (400), synchronization procedure (500) may be implemented or executed using the system (100) and hardware synchronization unit (120) described above. The steps or actions of procedure (500) are performed using programmed software instructions, firmware instructions, or both. One or more instructions may be stored in a non-transitory machine-readable storage device and be executable by one or more of the processors or other resources described herein.

As described above, to process data, the SoC (102) may initiate a heterogeneous computation operation in which some (or all) of multiple IP devices, for example, the ISP (112), the TPU (114), the DSP (116), and the GPU (118), perform specific operations of the heterogeneous operation. For example, the data may be image data, and the heterogeneous operation may include i) an inference operation to perform face recognition on the image data, and ii) a scaling operation to perform post-processing on the image data. In general, since the heterogeneous operation may involve multiple IP devices on the SoC (102), the system (100) requires synchronization of specific computational steps between the IP devices. In this manner, the hardware synchronization unit (120) is configured to provide generic/shared synchronization semantics to impart meaning to the synchronization objects used to simplify synchronization operations between the various IP devices on the SoC (102).

Referring back to the synchronization procedure (500), an exemplary operation using the procedure (500) may involve a camera IP device requiring a synchronization object to represent or indicate that an image has been generated by an image sensor of the user device (130), or a decoder IP device requiring a synchronization object to represent or indicate that data associated with an image has been decoded. The hardware synchronization unit (120) may process individual requests from each of these IP devices and allow them to obtain a synchronization object and allocate resources defining a synchronization context associated with the request.

Using an example involving a camera IP device, the image sensor may be controlled by an ISP (112) of a user device (130). The ISP (112) uses its own ISP driver (IPS Driver) to transmit a 'GetSync' signal (502) to a driver (or driver logic) of a synchronization module (108). The driver of the synchronization module may be an exemplary application processor (AP). In some implementations, this driver logic of the synchronization module (108) corresponds to or is included in the control logic (202) of the hardware synchronization unit (120).

The hardware synchronization unit (120) uses driver logic to generate control signaling (124) based on a 'GetSync' signal, wherein the control signaling may include a first synchronization control signal ('sync') (504). The 'sync' control signal of the control signaling (124) may initiate execution of one or more synchronization events in the SoC (102). The driver of the hardware synchronization unit (120) passes a global synchronization object to the ISP (112) based on the 'sync' control signal (506). In some implementations, the passing of this global synchronization object represents the generation (or acquisition) of a synchronization ID ('sync ID').

The ISP (112) uses a global synchronization object to signal a process operation (508) to the TPU (114). For example, the ISP (112) may signal the TPU (114) to request that the TPU (114) perform an image processing operation on an image, such as an inference operation to generate a facial recognition output. In the example of FIG. 5, the signaling for the process operation is performed between individual drivers of the ISP (112) and the TPU (114). In some implementations, the drivers referenced in the example of FIG. 5 run on an exemplary AP of a corresponding IP device. The TPU (114) may generate an internal call operation (510), for example, to call its own stack, which ultimately proceeds to the TPU firmware on the TPU hardware.

Similarly, the ISP (112) signals a process operation (512) to the DSP (116) using a global synchronization object. For example, the ISP (112) may signal the DSP (116) to request that the DSP (116) perform an image processing operation on the image, such as a scaling operation to perform post-processing on the image data. In the example of FIG. 5, the signaling for this particular process operation is performed between individual drivers of the ISP (112) and the DSP (116). The DSP (116) may generate an internal call operation (514), for example, to call its own stack, which ultimately proceeds to DSP firmware on the DSP hardware.

Before initiating their individual operations on an image, the TPU (114) and the DSP (116) may each signal the hardware synchronization unit (120) to signal 'wait(sync)' with a reference to a global synchronization object (516). For example, the TPU (114) and the DSP (116) may each perform individual 'wait events' to ensure that they do not proceed with operations on the image before the hardware synchronization unit (120) notifies the TPU (114) or the DSP (116) that they can begin their individual operations on the image. In some implementations, the TPU (114) and the DSP (116) each execute the wait events in parallel with each other and with other synchronization signaling operations performed by the ISP (112).

For example, the ISP (112) can proactively signal the TPU (114) and the DSP (116) even while the ISP (112) is still performing operations on the image. Once the ISP (112) has completed its work on the image, the ISP (112) can signal synchronization via a 'signal(sync)' operation (518) and pass a synchronization object to the hardware synchronization unit (120). The hardware synchronization unit (120) can generate and transmit control signals to notify the TPU (114) and the DSP (116) to begin individual processing operations on the image (520).

Embodiments of the subject matter and functional operations described herein may be implemented as digital electronic circuitry, tangible computer software or firmware, computer hardware including the structures disclosed herein and their structural equivalents, or a combination of one or more of these. Embodiments of the subject matter described herein may be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded in a tangible, non-transitory program carrier for execution by or controlling the operation of a data processing device.

Alternatively or additionally, the program instructions may be encoded in an artificially generated radio signal, e.g., a machine-generated electrical, optical, or electromagnetic signal that is generated to encode information for transmission to a suitable receiver device for execution by a data processing device. The computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of these.

The term 'computing system' encompasses all kinds of apparatus, devices, and machines for processing data, including, for example, a programmable processor, a computer, or multiple processors or computers. The apparatus may include special-purpose logic circuits, for example, a field programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). The apparatus may also include, in addition to the hardware, code that creates an execution environment for the corresponding computer program, for example, code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of these.

A computer program (which may also be referred to or described as a program, software, software application, module, software module, script, or code) may be written in any programming language, including compiled or interpreted languages, declarative or procedural languages, and may be distributed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

A computer program may correspond to a file within a file system, but need not. A program may be stored within a single file dedicated to the program, within a file containing one or more scripts stored within another program or data (e.g., a markup language document), within a single file, or within multiple coordinated files, such as files containing one or more modules, subprograms, or portions of code. A computer program may be distributed to be executed on a single computer, located at a single site, or across multiple sites interconnected by a communications network.

The processes and logic flows described herein can be performed by one or more programmable computers executing one or more computer programs to perform functions by operating on input data to produce output. The processes and logic flows can also be performed by special purpose logic circuitry, such as a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), or a general purpose graphics processing unit (GPGPU), and a device can also be implemented as such special purpose logic circuitry.

A computer suitable for executing a computer program may include, for example, a computer based on a general-purpose or special-purpose microprocessor, or both, or another type of central processing unit. Typically, the central processing unit will receive instructions and data from read-only memory or random-access memory, or both. Some elements of the computer include the central processing unit for performing or executing instructions and one or more memory devices for storing instructions and data. Typically, the computer will also include, or be operatively coupled to receive data from, transfer data to, or both of, one or more mass storage devices, such as magnetic disks, magneto-optical disks, or optical disks, for storing data. However, a computer need not necessarily include such devices. Additionally, the computer may be embedded in another device, such as a mobile telephone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a Global Positioning System (GPS) receiver, or a portable storage device, such as a universal serial bus (USB) flash drive.

Computer-readable media suitable for storing computer program instructions and data include, for example, all forms of non-volatile memory, media and memory devices, including semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices; magnetic disks, such as internal hard disks or removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks. The processor and memory may be supplemented by or incorporated into special purpose logic circuitry.

To provide interaction with a user, embodiments of the subject matter described herein can be implemented on a computer having a display device, such as a liquid crystal display (LCD) monitor, for displaying information to the user, and a keyboard and a pointing device, such as a mouse or trackball, through which the user can provide input to the computer. Other types of devices may also be used to provide interaction with the user; for example, feedback provided to the user may be any form of sensory feedback, such as visual, auditory, or tactile feedback, and input from the user may be received in any form, including acoustic, speech, or tactile input. Furthermore, the computer may interact with the user by transmitting documents to and receiving documents from a device used by the user, for example, by transmitting web pages to a web browser on the user's client device in response to a request received from the web browser.

Embodiments of the subject matter described herein may be implemented in a computing system that includes a back-end component, e.g., a data server, a middleware component, e.g., an application server, or a front-end component, e.g., a client computer having a graphical user interface or web browser through which a user can interact with an implementation of the subject matter described herein, or in any combination of one or more of such back-end, middleware, or front-end components. The components of the system may be interconnected via any form or medium of digital data communication, e.g., a communications network. Examples of communications networks include a local area network ('LAN') and a wide area network ('WAN'), e.g., the Internet.

A computing system may include clients and servers. Clients and servers are typically remote and interact through a communications network. The relationship between client and server is established by computer programs running on separate computers, each of which has a client-server relationship with the other.

Although this specification contains many specific implementation details, these should not be construed as limitations on the scope of any invention or what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. Certain features described herein in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple embodiments, either individually or in any suitable subcombination. Furthermore, features may be described as operating in a particular combination, and even if initially claimed as such, one or more features of a claimed combination may in some cases be removed from the combination, and the claimed combination may be directed toward subcombinations or variations of subcombinations.

Likewise, while the drawings depict operations in a particular order, this should not be construed as requiring that these operations be performed in the specific order shown or sequentially, or that all illustrated operations be performed, to achieve desired results. In certain situations, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the embodiments described above should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

Specific embodiments of the invention have been described. Other embodiments are within the scope of the following claims. For example, the actions described in the claims may be performed in a different order and still achieve desirable results. As an example, the processes depicted in the accompanying drawings do not necessarily require the specific order or sequential order shown to achieve desirable results. In certain implementations, multitasking and parallel processing may be advantageous.

Claims (20)

A method performed using a hardware synchronization unit of a system-on-chip ('SoC') of a user device,
A step of creating a global synchronization object used to control and manage one or more synchronization events in the SoC by the hardware synchronization unit;
A step of determining a plurality of context states by referring to the global synchronization object by the hardware synchronization unit, wherein the plurality of context states each correspond to an individual IP device among the plurality of IP devices on the SoC;
In the hardware synchronization unit, generating a plurality of register values each representing a plurality of context states corresponding to each individual IP device; and
A method comprising, by the hardware synchronization unit, managing the execution of synchronization events involving each of the plurality of IP devices based on the global synchronization object and the plurality of register values. In the first paragraph, the step of creating the global synchronization object comprises:
A step of receiving a global synchronization request from a first IP device by the hardware synchronization unit; and
A method comprising the step of creating the global synchronization object based on the global synchronization request from the first IP device by the hardware synchronization unit. In the second paragraph, the step of creating the global synchronization object comprises:
A step of generating a control signaling for initiating execution of the synchronization events in the SoC by the hardware synchronization unit,
A method wherein the control signaling comprises a first synchronization control signal that transmits the global synchronization object to the first IP device. In the first paragraph, the method further comprises a step of detecting a plurality of secondary global synchronization objects generated based on the control signaling that initiates execution of the synchronization events in the SoC by the hardware synchronization unit,
A method wherein each of the plurality of secondary global synchronization objects corresponds to a universal synchronization ID propagated to an individual IP device among the plurality of IP devices. In the fourth paragraph, at least one of the plurality of secondary global synchronization objects,
is communicated between at least two of the plurality of IP devices to execute one or more of the above synchronization events,
A method for executing individual synchronization events for distinct data processing operations that are performed concurrently to process event data associated with an application running on the user device. A method according to claim 1, further comprising the step of synchronizing a subset of communications in the SoC based on each of the plurality of register values representing each of the plurality of context states and the global synchronization object, using the hardware synchronization unit. A method according to claim 1, further comprising the step of associating each of the plurality of context states with an individual IP device among the plurality of IP devices and a synchronization activity corresponding to the IP device, using the global synchronization object. In the seventh paragraph, for each of the plurality of IP devices, the synchronization activity is:
A first synchronization event representing a signal event; and
A method comprising a second synchronization event representing a waiting event. In the first paragraph, the SoC further comprises a step of detecting a request for processing event data associated with an application running on the user device,
A method wherein the above synchronization events are executed in the SoC simultaneously with the data processing operations of each IP device used to process the event data. As a system,
A hardware synchronization unit, a processing device, and a non-transitory machine-readable storage device storing instructions executable by the processing device to perform operations, the operations comprising:
Creating a global synchronization object used to control and manage one or more synchronization events in the SoC by the hardware synchronization unit;
By the hardware synchronization unit, determining a plurality of context states by referring to the global synchronization object, wherein the plurality of context states each correspond to an individual IP device among the plurality of IP devices on the SoC;
In the hardware synchronization unit, generating a plurality of register values each representing a plurality of context states corresponding to each individual IP device; and
A system comprising: managing the execution of synchronization events involving each of the plurality of IP devices based on the global synchronization object and the plurality of register values by the hardware synchronization unit. In the 10th paragraph, creating the global synchronization object comprises:
Receiving a global synchronization request from a first IP device by the hardware synchronization unit; and
A system comprising: generating the global synchronization object based on the global synchronization request from the first IP device by the hardware synchronization unit. In the 11th paragraph, creating the global synchronization object comprises:
Including generating a control signaling to initiate execution of the synchronization events in the SoC by the hardware synchronization unit,
A system wherein the control signaling comprises a first synchronization control signal that transmits the global synchronization object to the first IP device. In the 10th paragraph, the above actions are:
Further comprising detecting a plurality of secondary global synchronization objects generated based on the control signaling that initiates execution of the synchronization events in the SoC by the hardware synchronization unit,
A system wherein each of the plurality of secondary global synchronization objects corresponds to a universal synchronization ID propagated to an individual IP device among the plurality of IP devices. In the 13th paragraph, at least one of the plurality of secondary global synchronization objects,
is communicated between at least two of the plurality of IP devices to execute one or more of the above synchronization events,
A system used to execute individual synchronization events for distinct data processing operations that are performed concurrently to process event data associated with an application running on the user device. In the 10th paragraph, the above actions are:
A system further comprising synchronizing a subset of communications in the SoC based on each of the plurality of register values representing each of the plurality of context states and the global synchronization object, using the hardware synchronization unit. In the 10th paragraph, the above actions are:
A system further comprising associating each of the plurality of context states with an individual IP device among the plurality of IP devices and a synchronization activity corresponding to the IP device, using the global synchronization object. In paragraph 16, for each of the plurality of IP devices, the synchronization activity is:
A first synchronization event representing a signal event; and
A system comprising a second synchronization event representing a waiting event. In the 10th paragraph, the above actions are:
In the above SoC, further comprising detecting a request for processing event data associated with an application running on the user device,
The above synchronization events are executed in the SoC simultaneously with the data processing operations of each IP device used to process the event data. A non-transitory machine-readable storage device storing instructions executable by a processing device to perform operations involving a hardware synchronization unit, said operations comprising:
Creating a global synchronization object used to control and manage one or more synchronization events in the SoC by the hardware synchronization unit;
By the hardware synchronization unit, determining a plurality of context states by referring to the global synchronization object, wherein the plurality of context states each correspond to an individual IP device among the plurality of IP devices on the SoC;
In the hardware synchronization unit, generating a plurality of register values each representing a plurality of context states corresponding to each individual IP device; and
A non-transitory machine-readable storage device comprising, by the hardware synchronization unit, managing the execution of synchronization events involving each of the plurality of IP devices based on the global synchronization object and the plurality of register values. In paragraph 19, creating the global synchronization object comprises:
Receiving a global synchronization request from a first IP device by the hardware synchronization unit; and
A non-transitory machine-readable storage device comprising: generating the global synchronization object based on the global synchronization request from the first IP device by the hardware synchronization unit.