KR20250107870A - Protection circuits for power amplifiers - Google Patents

Abstract

Various methods and circuit arrangements are presented for protecting a power amplifier (PA) from high input power conditions. In one aspect, a protection circuit coupled to a stage of the PA limits current passing through the stage during high input power conditions. The current limitation is provided by a current limiter circuit including a current generator coupled to a current mirror. The current is limited to a high value based on a reference current generated by the current generator. In one aspect, the reference current is programmable or variable. In another aspect, the protection circuit includes a clamp that limits an undervoltage at the output of the current limiter circuit. In another aspect, the protection circuit includes a pre-charge circuit that pre-charges the output of the current limiter circuit. In another aspect, a filter is incorporated within the current limiter circuit.

Description

Protection circuits for power amplifiers

Cross-reference to related applications

This application claims priority to U.S. Non-Provisional Application No. 18/056,128, filed November 16, 2022, entitled “PROTECTION CIRCUIT FOR POWER AMPLIFIERS,” the entire contents of which are incorporated herein by reference.

field

The present application relates to amplifiers. In particular, the present application relates to the protection of power amplifiers (PAs).

FIG. 1A illustrates a prior art radio frequency (RF) power amplifier (PA) module (100a), which may be used, for example, in a transmitter section of an RF front-end communication system, such as a mobile communication system. As illustrated in FIG. _1A , the power amplifier module (100a) may include a plurality of cascaded amplifier stages (e.g., a driver stage ( _A1) , a final stage (A2)) coupled in series via matching networks (e.g., MN 0 , MN 1 , MN ₂ ) to amplify an input RF signal (RFin) and generate an amplified output RF signal (RFout) therefrom. Power to the amplifier stages (A1, A2) may be provided via corresponding supply voltages (Vcc1, Vcc2 which may be the same or separate) referenced to ground, which are coupled to the amplifier stages (A1, A2) via respective inductors (L1, L2). The amplified signal (RFout) can in turn be transmitted via an antenna coupled to the PA module (100a), for example via an antenna switch (e.g., as known in the art).

As illustrated in FIG. 1b, each of the amplifier stages (A1, A2) may include a respective cascode arrangement of stacked (FET) transistors, (M ₁₁ , M ₁₂ , ... M _1k ) and (M ₂₁ , M ₂₂ , ... M _2k ), each of which is coupled between a respective supply voltage (Vcc1 , Vcc2 ) and a reference ground. Additionally, as illustrated in FIG. 1b, biasing of each of the transistors ((M ₁₁ , M ₁₂ , ... M _1k ) and (M ₂₁ , M ₂₂ , ... M _2k )) may be provided via associated biasing circuits (BIAS1 and BIAS2) configured to generate gate voltages at the gates of each of the stacked transistors. In particular, the DC biasing current (e.g., I _CC1 , I CC2 ) flowing (gain setting) through each of the transistor stacks (M ₁₁ , M ₁₂ , ... M _1k ) and (M ₂₁ , M ₂₂ , ... _{M 2k} ) may be primarily based on the gate voltage provided to each of the input transistors (e.g., M ₁₁ , M ₁₂ ) during normal operating conditions of the PA module (100a). In other words, the gain of each of the amplifier stages (A1, A2), i.e., the ratio between the RF power (at the drain) of the corresponding output transistor (e.g., M _1k , M _2k ) and the RF power (at the gate) of the corresponding input transistor (e.g., M ₁₁ , M ₂₁ ), may be based on the respective DC biasing current (e.g., I _CC1 , I _CC2 ).

Normal operating conditions of the PA module (100a) may include an upper limit of the input RF power provided by the input RF signal (RFin), which in turn may define an upper limit of the output RF power of the amplifier stage (A1) provided as input to the amplifier stage (A2). However, under certain conditions, (e.g., during a robustness test) whether controlled or not (e.g., transient), the input RF power to the amplifier stage (A1) may exceed the upper limit and/or may include a DC component (e.g., an average DC component of the RF signal) that may couple to the gate of the input transistor (M ₁₁ ) to provide a higher gain (i.e., a larger magnitude of I _CC1 ) of the amplifier stage ( _A1 ). In combination, these effects may generate an input RF signal to the amplifier stage (A2) that may include an amplitude sufficiently large to impair or at least affect the performance (e.g., hot carrier injection) of the corresponding input transistor (M 21 ). In other words, the amplitude of the RF signal to the amplifier stage (A2) can cause any one _of the gate-to-source voltage (Vgs), gate-to-drain voltage (Vgd), or drain-to-source voltage (Vds) of the input transistor (M 21) to reach levels high enough to damage and/or affect the performance of the transistor.

Therefore, improved protection of RF amplifier modules against high input RF power conditions that may not be considered normal operating conditions may be needed. The teachings of the present disclosure provide such improved protection while maintaining ongoing operation of the RF amplifier module.

According to a first aspect of the present disclosure, a circuit is provided comprising a plurality of cascaded amplifier stages; and a protection circuit coupled to a supply voltage node of a first stage of the plurality of cascaded amplifier stages, wherein the first stage operates between the supply voltage node and a reference ground, and the protection circuit comprises a current limiter circuit configured to limit a high value of a supply current flowing from the supply voltage node to the reference ground through the first stage, the high value of the supply current being based on a magnitude of the reference current.

According to a second aspect of the present disclosure, a method for protecting a multi-stage amplifier from a high input power condition is presented, the method comprising: coupling an output leg of a current limiter circuit to a supply voltage node of a first stage of the multi-stage amplifier; and limiting a high value of current flowing through the first stage from the supply voltage node based on a reference current flowing through the input leg of the current limiter based on the coupling.

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate one or more embodiments of the present disclosure and, together with the description of the exemplary embodiments, serve to explain the principles and implementations of the present disclosure.
FIG. 1a illustrates a prior art RF power amplifier (PA) module including multiple cascaded amplifier stages.
Figure 1b illustrates an exemplary implementation of cascaded amplifier stages of a PA module.
FIG. 2a illustrates a configuration of an RF power amplifier (PA) module having a protection circuit according to one embodiment of the present disclosure.
Figures 2b and 2c illustrate graphs showing performance benefits provided by the protection circuit of Figure 2a.
FIG. 3a illustrates a simplified schematic diagram of a current limiter circuit according to one embodiment of the present disclosure that may be used in the protection circuit of FIG. 2a.
Figures 3b and 3c illustrate graphs showing the performance benefits provided by the current limiter circuit of Figure 3a.
FIGS. 4A, 4B and 4C illustrate simplified schematic diagrams of other current limiter circuits according to additional embodiments of the present disclosure that may be used in the protection circuit of FIG. 2A.
FIGS. 5A and 5B illustrate graphs illustrating possible performance drawbacks that may be provided by a current limiter circuit according to the present disclosure.
FIG. 5c illustrates a simplified schematic diagram of a biasing circuit according to an exemplary embodiment of the present disclosure that may be used to overcome the possible performance drawbacks illustrated in FIGS. 5a and 5b.
FIG. 6a illustrates a simplified schematic diagram of a current limiter circuit with output voltage clamping according to an exemplary embodiment of the present disclosure.
Figures 6b and 6c illustrate graphs showing the performance benefits provided by the current limiter circuit with output voltage clamping of Figure 6a.
FIG. 7 illustrates a simplified schematic diagram of a current limiter circuit having pre-charging of the output voltage according to an exemplary embodiment of the present disclosure.
FIG. 8a illustrates a configuration according to another embodiment of the present disclosure of an RF power amplifier (PA) module having a protection circuit coupled to a final stage.
FIG. 8b illustrates a configuration according to another embodiment of the present disclosure of an RF power amplifier (PA) module having a protection circuit coupled to one of the plurality of stages.
FIG. 8c illustrates a configuration according to another embodiment of the present disclosure of an RF power amplifier (PA) module having protection circuitry shared between multiple stages.
FIG. 9 illustrates a configuration according to another embodiment of the present disclosure of a protection circuit shared between multiple RF power amplifier (PA) modules.
FIG. 10 illustrates a simplified schematic diagram of a current limiter circuit having a built-in RF filter according to an exemplary embodiment of the present disclosure.
FIG. 11 illustrates a configuration of an RF power amplifier (PA) module having a protection circuit whose operation can be controlled based on detected parameter values according to an embodiment of the present disclosure.
FIG. 12 illustrates a configuration of an RF power amplifier (PA) module having a protection circuit according to an embodiment of the present disclosure, wherein the RF PA module includes a bipolar transistor.
FIG. 13 is a process chart illustrating various steps of a method according to an embodiment of the present disclosure.
Identical reference numbers and designations in various drawings represent identical elements.

Throughout this disclosure, embodiments and variations are described for the purpose of illustrating uses and implementations of the concepts of the present invention in various embodiments. It should be understood that the exemplary descriptions are intended to present examples of the concepts of the present invention, but not to limit the scope of the concepts as disclosed herein.

FIG. 2a illustrates a configuration according to one embodiment of the present disclosure, which includes an RF power amplifier (PA) module (200a) including a protection circuit (220) coupled to a first (e.g., driver) stage (A1) of the PA module (200a). According to an embodiment of the present disclosure, the protection circuit (220) may include a current limiter (circuit) configured to limit the amount of current supplied to the first stage (A1). In other words, the current limiter of the protection circuit (220) may limit high values of the DC biasing/supply current (I _CC1 ), thereby limiting the gain of the first stage (A1). By limiting the gain of the first stage (A1), the input power to the second (e.g., final) stage (A2) can be limited to values that do not impair or negatively affect the performance of the second stage (A2), including the input transistor (e.g., M ₂₁ ) of the second stage (A2).

A protection circuit (220) according to the present teachings may be designed to limit the current supplied to a stage (e.g., A1) only for values of input RF power to the stage (e.g., RFin) that are greater than or equal to the expected value under normal operating conditions of the PA module (200a). According to one embodiment of the present disclosure, limiting the current supplied to the stage (e.g., A1) may prevent the operation of such a stage from being interrupted, thereby maintaining ongoing activity of the PA module (200a).

FIGS. 2b and 2c illustrate graphs illustrating performance advantages provided to a PA module (200a) by the protection circuit of FIG. 2a as compared to a prior art PA module (e.g., 100a of FIG. 1a) that is not protected. In these graphs, normal operating conditions of the PA modules (200a, 100a) are represented by the input power (Pin) to the first stage (e.g., A1 of FIGS. 1a, 2a) in a range of values to the left (i.e., less than) the power limit line (NL) (illustrated by an exemplary input power limit value of -5 dBm). As illustrated in FIG. 2b, during normal operating conditions, the supply current (e.g., I CC1 , labeled as CL in the graph) to the first stage (A1) of the (protected) PA module (e.g., 200a of FIG. 2a) is substantially equal to the supply current (e.g., I _CC1 , labeled as CV in the graph) to the first stage (A1) of the (unprotected) prior art PA module (e.g., 100a of FIG. _1a ). However, for values of input power (Pin) that are greater than the input power limit (e.g., to the right of the power limit line (NL)), the supply current (e.g., I CC1 , labeled as CL in the graph) for the (protected) PA module (e.g., 200a in Fig. 2a) gradually flattens out when the current limit is reached (e.g., when the two graphs become separated), whereas the supply current (e.g., I _CC1 , labeled as CV in the graph) for the prior art (unprotected) PA module (e.g., _100a in Fig. 1a) increases steadily (without a current upper limit limitation). Accordingly, as shown in the graphs of Fig. 2c, the output power (Pout) of the first stage (A1) for the protected (CL) and unprotected (CV) configurations can follow the same trend as the supply currents. In particular, as shown in Fig. 2c, as a result of the current limit, the output power (Pout) of the first stage (A1) can follow the same trend as the supply currents. For values of the input power (Pin) for the first stage (e.g., A1 in FIG. 1a, FIG. 2a) on the right side of the line (NL), the output power (Pout) of the first stage (A1) (labeled as CL in the graph) of the (protected) PA module (e.g., 200a in FIG. 2a) stops increasing (e.g., gradually decreases when reaching the current limit), whereas the output power (Pout) of the first stage (A1) (labeled as CV in the graph) of the prior art (unprotected) PA module (e.g., 100a in FIG. 1a) increases steadily (without a power upper limit). More details on these graphs can be found later in the present disclosure (e.g., with reference to FIG. 3a).

FIG. 3a illustrates a simplified schematic diagram of a current limiter circuit (222, 225) according to one embodiment of the present disclosure that may be included in the protection circuit (220) described above with reference to FIG. 2a. In the particular case illustrated in FIG. 3a, the stages (A1, A2) of the PA module (300a) are illustrated as including respective cascode arrangements of stacked (FET) transistors, (M ₁₁ , M ₁₂ , ... M _1k ) and (M ₂₁ , M ₂₂ , ... M _2k ), as described above with reference to FIG. 1b . According to one embodiment of the present disclosure, the current limiter (222, 225) may include a reference current source (222) coupled to a current mirror (225). A reference current source (222) generates a reference current (Iref) that can be used by an input leg (e.g., a PMOS FET transistor (M _IN )) of a current mirror (225), and thereby generates a current delivered through an output leg (e.g., a PMOS FET transistor (M _OUT )) that can be used as a biasing/supply current (I _CC1 ) for the first stage (A1). As illustrated in FIG. 3A, the transistors (M _IN , M _OUT ) of the current mirror (225) can be coupled to each other through their respective gates and to a supply voltage (Vdd) through their respective sources. The drain of the input transistor (M _IN ) of the current mirror (225) may be coupled to the reference current source (222), and the drain of the output transistor (M _OUT ) of the current mirror (225) may be coupled to the first stage (A1) via the inductor (L1). In particular, as illustrated in FIG. 3a , the drain of the output transistor (M _OUT ) of the current mirror (225) may be coupled to the drain of the output (NMOS FET) transistor (M _1k ) of the cascode arrangement of stacked (FET) transistors (M ₁₁ , M ₁₂ , ... M _1k ). The bypass capacitor (C1) may be coupled to the output of the protection circuit (220), or in other words, to the supply voltage node (V _CC1 ), to reduce coupling of RF frequency components to the protection circuit (220). In other words, the bypass capacitor (C1) in combination with the inductor (L1) can form a filter configured to reduce such coupling of RF frequency components to the protection circuit (220).

With continued reference to FIG. 3A, in some embodiments, the current limiters (222, 225) can limit a high value (magnitude) of the supply current (I _CC1 ) based on a mirrored value of the reference current (Iref). In some embodiments, this mirrored value can be proportionally related to the reference current (Iref ), for example, based on a ratio of the sizes of the transistors (M _IN , M _OUT ) of the current mirror (225). For the non-limiting exemplary case where the ratio of the sizes of the transistors (M _IN , M _OUT ) is 1 (same size transistors), the mirrored value of the reference current (Iref ) that determines the high value of the supply current (I _CC1 ) can be equal to the value of the reference current (Iref ).

When the current limiter (222, 225) is coupled to the first stage (A1) as illustrated in FIG. 3a, the supply current (I _CC1 ) output by the current limiter (222, 225) can follow the required current based on the biasing of the input transistor (M ₁₁ ) of the first stage (A1) up to a limit determined by the mirrored value of the reference current (Iref). During a current limiting condition, or in other words when the demand current is greater than a mirrored value of the reference current (Iref), the voltage at the supply voltage (node) (V _CC1 ) may decrease to limit the current passing through the first stage (A1 ), thereby increasing to some extent the current delivered through the output legs of the current limiters (222, 225) (e.g., the transistors M _OUT will have different bias conditions) beyond the mirrored value as shown in the graph (CL) of Fig. 2b . At the same time, this decrease in the voltage at the supply voltage (V _CC1 ) during the current limiting condition may reduce to some extent the power output by the first stage as shown in the graph (CL) of Fig. 2c .

With continued reference to FIG. 3A, in some embodiments, the flexibility and advantages provided by the current limiter (222, 225) include, for example: protection for at least one stage of a PA module (e.g., 300a of FIG. 3A) against high input power conditions by limiting current without interrupting operation of the (protected) PA module; no delay in protection against high input power conditions since no detection methods (e.g., current or power sensors) are used, but rather the current limiting is a (natural) response of the supply current circuitry for at least one stage; absence of any risk of oscillation that may be contributed by various feedback methods (e.g., RF power detection and feedback to limit supply current); Tunability and/or selectivity of (high) values of (limited) current (e.g., current limit) via a tunable/selectable Iref current source/generator (e.g., 222 of FIG. 3a and 422a/b of FIGS. 4a/4b described below), and tunability and/or selectivity of a corresponding input power limit value (e.g., threshold) defining high input power conditions thereby; and the ability to include temperature compensation/profile for the limit current (and thus power) as described below with reference to FIG. 4c; the ability to protect any one or more of a plurality of stages of a PA module, including a final stage, as described below with reference to FIGS. 8a/8b/8c; the ability to share the same protection circuit (e.g., current limiter) with a plurality of PA modules as described below with reference to FIG. 9; The ability to further control the high value of the limiting current (e.g., the value of the current limit) based on other detectable parameters, such as temperature or voltage/power levels, as described below with reference to FIG. 11; and the ability for use with a bipolar PA module, which may include bipolar devices such as a MOS PA module including MOS devices (e.g., FIG. 3a) or GaAs (gallium arsenide) devices (e.g., FIG. 12 described below).

FIGS. 3b and 3c illustrate graphs illustrating performance advantages provided by the current limiter circuit (222, 225) of FIG. 3a in protecting elements/transistors of stage (A2). In other words, by limiting the supply current (e.g., I _CC1 of FIG. 3a) to a first stage (e.g., A1 of FIG. 3a), elements/transistors of the next/second stage (e.g., A2 of FIG. 3a) can be protected against high input RF power conditions that may be experienced by a multi-stage PA module (e.g., 300a of FIG. 3a) including the first stage and the next stage. Advantageously, by not coupling the protection circuit (e.g., 220 in FIG. 3a) to the higher power final stage (e.g., A2 in FIG. 3a) of the multi-stage PA module, the flow of high supply current through the protection circuit to the final stage can be avoided, thus maintaining the overall RF performance of the module.

As shown in the graphs of FIGS. 3b and 3c labeled with CV, the (AC peak values) of the gate-source voltage (Vgs ₂₁ ) and drain-source voltage (Vds ₂₁ ) of the input transistor (M ₂₁ ) of the second/final (unprotected) stage (e.g., A2 in FIG. 1b ) steadily increase, which can increase the values of the input power (Pin) to the first/driver (unprotected) stage (e.g., A1 in FIG. 1b ). In particular, when operating under high input RF power conditions (right side of line NL), the voltages (Vgs ₂₁ and Vds ₂₁ ) of the (unprotected) second/final stage can reach values (e.g., more than 2 V) which may be higher than the voltage withstand capability of the input transistors (M ₂₁ ) (e.g., about 2 V), thereby potentially damaging these transistors.

Meanwhile, as shown in the graphs labeled as CL in FIGS. 3b and 3c, the (AC peak values) of the gate-source voltage (Vgs ₂₁ ) and the drain-source voltage (Vds ₂₁ ) of the input transistor (M ₂₁ ) of the second/final (protected) stage (e.g., A2 in FIG. 3a ) can be gradually flattened when the first/driver (protected) stage (e.g., A1 in FIG. 3a ) operates under high input RF power conditions (right side of line NL), especially when the supply current to the first/drive stage reaches its current limit. Because of this flattening (i.e. current/power limiting), the voltages of the (protected) second/final stage (Vgs ₂₁ and Vds ₂₁ ) may not reach values higher than the withstand voltage capability of the input transistor (M ₂₁ ) (e.g. about 2 V), thereby protecting this transistor.

FIGS. 4A, 4B and 4C illustrate simplified schematic diagrams of current limiter circuits according to additional embodiments of the present disclosure that may be used in the protection circuit (220) of FIG. 2A. In particular, these drawings illustrate different exemplary circuits (e.g., 422a, 422b and 422c) for generating a reference current (Iref) that may be provided to an input leg (e.g., M _IN ) of a current mirror (225). These include, for example, a voltage-to-current converter circuit (422a) of FIG. 4A that generates the reference current (Iref) based on a reference voltage (Vref) provided to the gate of a common-source (e.g., NMOS FET) transistor (Mref). Accordingly, depending on the IV characteristics of the transistor (Mref), the value of the reference current (Iref) can be controlled/adjusted/varied based on the value of the reference voltage (Vref).

FIG. 4b illustrates another exemplary voltage-to-current converter circuit (422b) that may be used to generate a reference current (Iref). In this implementation, a voltage (Vbg), which is input at the non-inverting input terminal (indicated by a + symbol in the drawing) of the operational amplifier (Op) and reproduced at the inverting input terminal (indicated by a - symbol in the drawing) of the operational amplifier (Op), is coupled to the source of the transistor (Mref). Since the source of the transistor (Mref) is coupled to the reference ground through the (shunted) resistor (Rref), the voltage drop across the resistor (Rref) is equal to the voltage (Vbg), and thus the current through the transistor (i.e., Iref) is equal to the ratio of Vbg/Rref. According to exemplary embodiments of the present disclosure, the resistor (Rref) may optionally have a programmable, variable, or settable resistance that may be controlled/changed stepwise and/or continuously. This programmability of the resistor (Rref) can allow for calibration of the voltage (Vbg) versus current (Iref) response provided by the circuit (422b).

The generation of the reference current (Iref) may include temperature compensation, as illustrated in the circuit (422c) of FIG. 4c. In such an implementation, the current (Iref) generated by the circuit (422c) may include a temperature profile that is designed to compensate for (e.g., take into account) performance variations/sensitivities of the PA module to temperature changes, which may include, for example, an increase or decrease in the nominal biasing current (e.g., I _CC1 ) for a given performance metric (e.g., for a given output power). By providing such a temperature profile, the triggering of the reference current (Iref) and thus the current limit condition can be adapted to the sensitivity of the PA module (of the stage) at a given temperature. In some embodiments, design techniques for implementing such a temperature profile may include, for example, the use of one or more of a proportional to absolute temperature (PTAT) profile, a complementary proportional to absolute temperature (CTAT) profile, or a zero-proportionality to absolute temperature (ZTAT) profile.

FIGS. 5A and 5B illustrate graphs illustrating possible performance drawbacks that may be introduced by the current limiting circuit of the protection circuit (220) described above (e.g., FIGS. 2A to 4C), and FIG. 5C illustrates a simplified schematic diagram of a biasing circuit (circled as detail a) according to an exemplary embodiment of the present disclosure that may be used to overcome the possible performance drawbacks illustrated in FIGS. 5A and 5B. In particular, FIG. 5C illustrates a portion of the configuration described above with reference to FIG. 3A regarding the first stage (A1) and the protection circuit (220), wherein the protection circuit (220) includes a reference current source/generator (522), which may be any of the current sources/generators (222, 422a/b/c) described above with reference to FIGS. 3A and 4A/4B/4C.

As mentioned above with reference to FIG. 3a , and with additional reference to FIG. 5c , as depicted in the graph of FIG. 5a , when the demand current by the input transistor (M ₁₁ ) of the first stage (A1 ) is greater than the mirrored value of the reference current (Iref), or in other words, in the case of a current limiting condition where the demand current is greater than the (limiting) current that the current limiter (522, 225) can generate or supply, the voltage at the supply voltage (node) (V _CC1 ) may be reduced to limit the current passing through the first stage (A1 ). This reduction in the supply voltage (V _CC1 ), which can be seen on the right side of the power limiting line (NL) of FIG. 5a , may be up to several volts (DC). Considering the output (top) transistor (M _1k ) of the first stage (A1), the corresponding drain voltage, which is DC coupled to the supply voltage (V _CC1 ), can vary with the supply voltage (V _CC1 ). Therefore, when the gate voltage (Vg _1k ) for the gate of the output transistor (M _1k ) is fixed/constant, as illustrated in Fig. 5b, the gate-to-drain voltage (Vgd _1k ) of the output transistor (M _1k ) can vary with the supply voltage (V _CC1 ) and may reach a voltage level which may be high enough to damage or otherwise affect the performance of the output transistor (M _1k ) and thus the performance of the first stage (A1) and the PA module in general. On the other hand, by making the gate voltage (Vg _1k ) to the gate of the output transistor (M _1k ) vary depending on the supply voltage (V _CC1 ), as performed by the biasing circuit detailed in FIG. 5c , the gate-drain voltage (Vgd _1k ) of the output transistor (M _1k ) can be kept substantially fixed/constant taking into account the variation of the supply voltage (V _CC1 ). The biasing circuit detailed a in FIG. 5c may include a resistor ladder including series-connected resistors (R ₁ , R 2 , ..., R _k ) coupled between the supply voltage node (V _CC1 ) and the reference ground to provide respective gate biasing voltages (Vg ₁₂ , _... , Vg _1k ) to the gates of the transistors (M ₁₂ , ..., Vg _1k ).

FIG. 6a illustrates a simplified schematic diagram of a current limiter circuit (225, 522) having output voltage clamping according to an exemplary embodiment of the present disclosure. As illustrated in FIG. 6a, according to one embodiment of the present disclosure, the clamping circuit (625) can be used to clamp/limit a low value of voltage at the output of the current limiter circuit (225) coupled/connected to the supply voltage (node) (V _CC1 ). Accordingly, the degree of voltage reduction at the supply voltage (node) (V _CC1 ) during the current limiting condition as described above with reference to FIGS. 5a/5c can be controlled/limited by the clamping circuit (625), and thus protection of the output (upper) transistor (M _1k ) of the first stage (A1) against overvoltage (voltage higher than the withstand voltage) can be provided. In other words, the clamping circuit (625) of FIG. 6a can provide a solution to the transistor overvoltage problem associated with a decreasing voltage at the supply voltage (node) (V _CC1 ) during a different current limiting condition than the solution provided by the biasing circuit illustrated in detail a of FIG. 5c . It should be noted that while both the configurations of FIG. 5c and FIG. 6a can solve the same problem, they can be used as separate solutions to the problem or together.

The clamping circuit (625) illustrated in FIG. 6a may include a (clamping, PMOS) transistor (M _C ) having a gate connected to the output of the current limiter circuit (225), and thus to the drain of the transistor (M _OUT ), and to a node (V _CC1 ); a source connected to a common (gate) node (N _CG ) connecting the gates of the transistors (M _IN , M _OUT ) of the current mirror (225); and a drain coupled to reference ground via a load (Load). During normal operating conditions, the voltage at the node (V _CC1 ) may be sufficiently high to set the gate-to-source voltage of the transistor (M _C ), which is sufficiently low to maintain the transistor (M _C ) in an off state (e.g., non-conducting). Meanwhile, during the current limiting condition, as the voltage at the node (V _CC1 ) decreases, the gate-source voltage of the transistor (M _C ) can increase until it reaches a level high enough to turn on (e.g., in the on state, conducting state) the transistor (M _C ). Turning on the transistor (M _C ) can ultimately lower the voltage at the common (gate) node (N CG ) to allow an increase in the current (I _CC1 ) output by the transistor (M _OUT ) while maintaining the gate-source voltage of the transistor (M _C ) at a substantially fixed/constant level (e.g., about 0.6 V). Thus, the (lower _{limit) voltage at the node (V CC1 )} can be set by the sum of the gate-source voltages of the transistors (M _CC1 and M _IN ), or in other words, at about Vdd-(2*0.6) V (assuming a gate-source voltage of about 0.6 V). Other lower limit (clamping) voltage values can be obtained by designing the transistors (M _CC1 and M _IN ) to provide corresponding ON-state gate-source voltages (i.e., threshold voltages).

FIGS. 6b and 6c illustrate graphs illustrating performance advantages provided by the current limiter circuit (225, 522) with the output voltage clamping of FIG. 6a. In particular, under current limiting conditions (right side of line NL), as illustrated in graph CL of FIG. 6b, when output voltage clamping is not provided, the voltage at node V _CC1 steadily/continuously decreases to levels that may be low enough to cause an overvoltage condition (e.g., about 2 volts) of the gate-to-drain voltage (Vgd _1k ) of the output transistor (M _1k ), as illustrated in graph CL of FIG. 6c . Meanwhile, under current limiting conditions (right side of line (NL)), when output voltage clamping is provided, as shown in the graph (CLP) of Fig. 6b, the voltage at node (V _CC1 ) decreases at a slower rate compared to the graph (CL) of Fig. _6b to reach a low/clamped level that may be sufficiently high not to cause an overvoltage condition (e.g., about 2 volts) of the gate-to-drain voltage (Vgd _1k ) of the output transistor (M 1k ), as shown in the graph (CLP) of Fig. 6c, for example.

FIG. 7 illustrates a simplified schematic diagram of a current limiter circuit (725, 522) having pre-charging of an output voltage according to an exemplary embodiment of the present disclosure. As illustrated in FIG. 7, a (switching) pre-charge circuit (728) may be coupled to the current mirror (725) to pre-charge the bypass capacitor (C1) prior to operation/use of the current limiter circuit (725, 522) (e.g., during a standby operation mode), thereby improving the turn-on time of the current limiter circuit (725, 522), which may include the charging time of the bypass capacitor (C1), to the nominal operating voltage (at node (V _CC1 )).

According to an exemplary embodiment of the present disclosure, as illustrated in FIG. 7, the pre-charge circuit (728) may include a first (e.g., single-pole, single throw, SPST) switch (SW1) having respective terminals coupled/connected to a common (gate) node (N _CG ) and a reference ground, and a second (e.g., single-pole, single throw, SPST) switch ( _SW2 ) having respective terminals coupled/connected to the common (gate) node (N _CG ) of the current mirror (725) and the drain node of the transistor (M IN ). During the pre-charge operation mode (the pre-charge circuit (728) illustrated in FIG. 7 is activated), the first switch (SW1) can be closed and the second switch (SW2) can be opened, so that the gate of the transistor (M _OUT ) of the current mirror (725) can be grounded, and the transistor (M _OUT ) can conduct current to charge the bypass capacitor (C1) to the nominal operating voltage. At the same time, the second switch (SW2) is opened, thereby eliminating the possibility that current leaking through the transistor (M _IN ) can reach the common (gate) node (N _CG ) and potentially affect the conduction state of the transistor (M _OUT ). On the other hand, when the pre-charge circuit (728) is not activated (e.g., in a disabled, inactive state), the first switch (SW1) can be opened and the second switch (SW2) can be closed, thereby resetting the configuration of the current limiter circuit (725, ₅₂₂ ) according to the current limiter circuits described above, including, for example, re-establishing the connection of the drain of the transistor (M _IN ) to the common (gate) node (N _CG ) and decoupling the common (gate) node (N CG ) from the reference ground.

As illustrated in FIGS. 8a/8b/8c, a protection circuit (220) including any of the current limiting circuits described above along with optional performance enhancements (e.g., FIGS. 5c/6a/7) may be used/coupled to any one or more stages of the PA module to protect the PA module by limiting current to the stage for protection of the same stage and/or protection of any subsequent stage (not necessarily the immediately subsequent/adjacent stage). This may include, for example, an output stage (e.g., A2) according to the configuration (800a) of FIG. 8a; a stage (Ak) of the (p) cascaded stages (A1, ..., Ak, ..., Ap) according to the configuration (800b) of FIG. 8b; Alternatively, such configurations may include connection/coupling of multiple stages (e.g., A1 and Ak) such that these stages (e.g., A1 and Ak) share the same protection circuit (220), as illustrated in the configuration (800c) of FIG. 8c. It should be noted that such configurations may impose different requirements (e.g., current magnitudes, size of transistor (M _OUT )) on the current limiting circuit, which may be based on, for example, operating power conditions/levels of the stages to which the protection circuit may be coupled.

FIG. 9 illustrates a configuration (900) according to another embodiment of the present disclosure of a protection circuit (e.g., including a current limiter 220) shared between a plurality of RF power amplifier (PA) modules (PA1, PA2, ..., PAk), each module including a plurality of cascaded stages (e.g., A1 ₁ , A2 ₁ ; A1 ₂ , A2 ₂ ; ...; and A1 _k , A2 _k ) and a plurality of matching networks (e.g., MN ₀₁ , MN ₁₁ , MN ₂₁ ; MN ₀₂ , MN ₁₂ , MN ₂₂ ; ...; and MN _0k , MN _1k , MN _2k ). In the configuration (900) illustrated in FIG. 9, at any given time, one of the PA modules (PA1, PA2, ..., PAk) can be coupled to an antenna (not shown) via an antenna switch (not shown) for transmission of an amplified RF signal (RFout ₁ , RFout ₂ , ..., RFout _k ). It should be noted that each stage (e.g., A1 ₁ , A1 ₂ , A1 _k ) of the PA modules (PA1, PA2, ..., PAk) to which the protection circuit (220) having a current limiter is coupled/connected may impose different requirements (e.g., current magnitudes, size of transistor M _OUT ) on the current limiting circuit based on their respective operating power conditions/levels. The possibility of programming the reference current of the current limiter circuit used in the protection circuit (220) (e.g. Iref generated by the circuit (222) of FIG. 4a/FIG. 4b) and/or the ratio of the sizes of the transistors (M _IN and M _OUT ) may allow programming different current limits for each of the PA modules (PA1, PA2, ..., PAk).

FIG. 10 illustrates a simplified schematic diagram of a current limiter circuit (225, 522) having an embedded RF filter circuit (1025) according to an exemplary embodiment of the present disclosure. The current limiter circuit (225, 522) may include a reference current source/generator (522), which may be any of the current sources/generators (222, 422a/b/c) described above with reference to FIGS. 3A and 4A/4B/4C. The RF filter circuit (1025) may include a resistor (R _FL ) connected in series between the gates of the transistors (M _IN , M _{OUT )} of the current mirror (225) and a capacitor (C _FL ) having a first terminal connected to the resistor (R _FL ) at the gate of the transistor (M OUT ) and a second terminal connected to a supply voltage (Vdd). The combination of resistor (R _FL ) and capacitor (C _FL ) can form a filter that can attenuate components of the RF signal coupled to the inductor (L1) that may not be sufficiently attenuated by the combination of (L1, C1), for example, including the RF envelope signal. Since this RF envelope signal may include frequencies that are sufficiently lower than the center frequency of the RF signal targeted for attenuation by the combination of (L1, C1), it may not be sufficiently attenuated by the latter combination. Attenuation/removal of RF signal related frequency components, including higher frequency components via (L1, C1) and lower frequency components via (R _FL , C _FL ), can allow for improved stability/performance of the current limiter circuit (225, 522).

FIG. 11 illustrates a configuration (1100) of an RF power amplifier (PA) module (e.g., including cascaded stages A1, ..., Ak, ..., Ap) having a protection circuit (220) whose operation can be controlled based on detected parameter values, according to an embodiment of the present disclosure. As illustrated in FIG. 11, a detector circuit (1145) can detect values of one or more parameters and provide these values to a controller circuit (1135) that can correspondingly control the operation of the protection circuit (220), including operation of a current limiter. According to an exemplary embodiment of the present disclosure, the one or more parameters detected (e.g., sensed) by the detector can be: a temperature, such as a local temperature (e.g., in the vicinity of the PA module or a stage thereof) or an ambient temperature (e.g., of a room in which a device including the PA module operates); or a voltage, such as a battery voltage (e.g., Vdd). Based on the detected parameter(s) value(s), the controller circuit (1135) can control/modify, for example, the magnitude of a reference current (e.g., Iref of FIGS. 4a/4b), and thus control/modify a current limit that can trigger a current limit condition.

FIG. 12 illustrates a configuration (1200) according to one embodiment of the present disclosure of an RF power amplifier (PA) module having a protection circuit, wherein the RF PA module includes bipolar transistors (e.g., Tr1, Tr2). The configuration (1200) of FIG. 12 may be similar to the configuration (300a) described above with reference to FIG. 3a, except that the stages (A1, A2) of the PA module include respective bipolar transistors (Tr1, Tr2) instead of a cascode arrangement of stacked (MOS FET) transistors, (M ₁₁ , M ₁₂ , ... M _1k ) and (M ₂₁ , M ₂₂ , ... M _2k ). Thus, by limiting the (DC) supply current (I _CC1 ) to the first stage (A1), that stage itself as well as the next stage (A2) can be protected from high input RF power conditions as described with reference to FIGS. 2a to 11.

FIG. 13 is a process chart (1300) illustrating various steps of a method for protecting a multi-stage amplifier from high input power conditions. As can be seen from the process chart (1300), the method includes, at step (1310), coupling an output leg of a current limiter circuit to a supply voltage node of a first stage of the multi-stage amplifier, and, at step (1320), limiting a high value of current flowing through the first stage from the supply voltage node based on a reference current flowing through the input leg of the current limiter based on the coupling.

It should be noted that various embodiments of the PA module having a protection circuit with current limiting for soft shutdown according to the present disclosure can be implemented as a monolithic integrated circuit (IC) according to any manufacturing technique and process known to those skilled in the art.

Applications that may include the novel devices and systems of the various embodiments include electronic circuits used in high-speed computers, communications and signal processing circuits, modems, single or multi-processor modules, single or multiple embedded processors, data switches, and application-specific modules including multi-layer, multi-chip modules. These devices and systems may further be incorporated as sub-components within various electronic systems, such as televisions, cellular telephones, personal computers (e.g., laptop computers, desktop computers, handheld computers, tablet computers, etc.), workstations, radios, video players, audio players (e.g., mp3 players), vehicles, medical devices (e.g., heart monitors, blood pressure monitors, etc.), and others. Some embodiments may include multiple methods.

The term "MOSFET" technically refers to metal-oxide-semiconductor; another synonym for MOSFET is "MISFET" for metal-insulator-semiconductor FET. However, "MOSFET" has become a common label for most types of insulated gate FETs ("IGFETs"). Nevertheless, it is well known that the term "metal" in the names of MOSFETs and MISFETs is now often a misnomer, since the former metal gate material is now often a layer of polysilicon (polycrystalline silicon). Similarly, the "oxide" in the name MOSFET can be a misnomer, since different dielectric materials are used to obtain stronger channels with lower applied voltages. Therefore, the term "MOSFET" as used herein is not to be read as being literally limited to metal-oxide-semiconductor, but instead generally includes IGFETs.

Various embodiments of the present invention may be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matter of design choice, and the various embodiments of the present invention may be implemented in any suitable IC technology (including but not limited to MOSFET and IGFET structures), or in hybrid or discrete circuit forms. The integrated circuit embodiments may be fabricated using any suitable substrates and processes, including but not limited to standard bulk silicon, silicon-on-insulator (SOI), silicon-on-sapphire (SOS), GaN HEMT, GaAs pHEMT, and MESFET technologies. However, the inventive concepts described above are particularly useful in SOI-based fabrication processes (including SOS), and fabrication processes having similar characteristics. Fabrication in CMOS on SOI or SOS allows for low power consumption, the ability to withstand high power signals during operation due to the stacking of FETs, good linearity, and high frequency operation (greater than about 10 GHz, and particularly greater than about 20 GHz). Monolithic IC implementations are particularly useful because parasitic capacitances can usually be kept low (or at a minimum, since they are kept uniform across all units, allowing them to be compensated for) by careful design.

Voltage levels may be adjusted, or voltage and/or logic signal polarities may be inverted, depending on particular specifications and/or implementation technology (e.g., NMOS, PMOS, or CMOS, and enhancement-mode or depletion-mode transistor devices). Component voltage, current, and power handling capabilities may be adapted as needed, for example, by adjusting device sizes, "stacking" components (particularly FETs) in series to withstand higher voltages, and/or using multiple components in parallel to handle higher currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and/or to provide additional functions without significantly altering the functionality of the disclosed circuits.

The examples presented above are provided to provide those skilled in the art with a complete disclosure and description of how to make and use the described embodiments and are not intended to limit the scope of what the applicants consider to be their invention. These embodiments may be used, for example, in mobile handsets for current communication systems (e.g., WCDMA, LTE, WiFi, etc.) where amplification of signals having frequency content greater than 100 MHz and at power levels greater than 50 mW may be required. Those skilled in the art will be able to find other suitable implementations of the presented embodiments.

Modifications of the above-described modes for carrying out the methods and systems disclosed herein that are obvious to those skilled in the art are intended to be within the scope of the following claims. All patents and publications mentioned in this specification are indicative of the level of skill of those skilled in the art to which this disclosure pertains. All references cited in this disclosure are incorporated by reference to the same extent as if each reference were individually incorporated by reference in its entirety.

It is to be understood that the present disclosure is not limited to particular methods or systems, which may of course vary. Furthermore, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” include plural referents unless the content clearly dictates otherwise. The term “plural” includes more than one referent unless the content clearly dictates otherwise. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

A number of embodiments of the present disclosure have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the present disclosure. Accordingly, other embodiments are within the scope of the following claims.

Claims (27)

As a circuit,
multiple cascaded amplifier stages; and
A protection circuit coupled to a supply voltage node of a first stage of the plurality of cascaded amplifier stages, the first stage operating between the supply voltage node and a reference ground,
The above protection circuit,
A circuit comprising a current limiter circuit configured to limit a high value of supply current flowing from the supply voltage node to the reference ground through the first stage, wherein the high value of the supply current is based on a magnitude of the reference current. In paragraph 1,
The above current limiter circuit,
a reference current source configured to generate the above reference current; and
A circuit comprising a current mirror having an input leg and an output leg, the input leg coupled to the reference current source and the output leg coupled to the supply voltage node. In the second paragraph,
The above reference current source is,
A circuit comprising a common-source transistor coupled to the input leg of the current mirror, wherein the reference current is a current flowing through the common-source transistor based on a voltage provided to a gate of the common-source transistor. A circuit in which, in the third aspect, the common-source transistor is connected in series with an input transistor of the input leg of the current mirror. In the second paragraph,
The above reference current source is,
a shunted resistor coupled to the input leg of the current mirror; and
A circuit comprising an operational amplifier having an inverting input terminal, the inverting input terminal coupled to the shunt resistor, the circuit setting a voltage drop across the shunt resistor based on a voltage provided at a non-inverting input terminal of the operational amplifier. In paragraph 5,
The above shunt resistor is coupled to the input leg through a reference transistor whose gate is coupled to the output of the operational amplifier,
A circuit wherein the above reference transistor is connected in series with the input transistor of the above input leg. In paragraph 5,
A circuit wherein the above shunt resistor comprises a tunable resistor. In the second paragraph,
The circuit, wherein the reference current source includes a temperature compensation profile. In the second paragraph,
A circuit wherein the protection circuit further comprises a clamp circuit configured to limit an undervoltage level at the supply voltage node. In Article 9,
The above low voltage level is,
The level of the supply voltage to the above current mirror,
The sum of the gate-source voltage of the clamping transistor of the above clamp circuit and the input transistor of the input leg of the above current mirror
Circuit based on the difference between the two. In Article 10,
The gate of the above clamping transistor is coupled to the supply voltage node,
The source of the above clamping transistor is coupled to the gate of the output transistor of the above output leg of the above current mirror,
A circuit wherein the drain of the above clamping transistor is coupled to the reference ground through a load. In the second paragraph,
A circuit wherein the protection circuit further comprises a pre-charge circuit configured to charge a bypass capacitor coupled to the supply voltage node during a standby operation mode of the protection circuit. In Article 12,
The above pre-charge circuit,
a first switch coupled between the gate of the output transistor of the output leg of the current mirror and the reference ground; and
A circuit comprising a second switch coupled between a gate of an input transistor of the input leg of the current mirror and a drain of the input transistor. In Article 12,
A circuit wherein, during at least a portion of said standby operation mode, said first switch is closed and said second switch is open. In the second paragraph,
The above current mirror circuit,
A circuit further comprising a filter coupled to the gate of the output transistor of the output leg, the filter comprising a resistor and a capacitor. In Article 15,
A circuit wherein the filter is configured to attenuate an envelope signal of an RF signal coupled to the supply voltage node. In paragraph 1,
A circuit wherein the first stage comprises a plurality of stacked FET transistors. In paragraph 1,
A circuit wherein the first stage comprises at least one bipolar transistor. In paragraph 1,
A circuit wherein the first stage is an input stage of the plurality of cascaded amplifier stages. In paragraph 1,
A circuit wherein the first stage is a driver stage of the plurality of cascaded amplifier stages that provides an input signal to an output stage of the plurality of cascaded amplifier stages. In paragraph 1,
A circuit wherein the first stage is an output stage of the plurality of cascaded amplifier stages. In paragraph 1,
The circuit wherein the above protection circuit is additionally coupled to a second stage among the plurality of cascaded amplifier stages. In paragraph 1,
The circuit further comprises one or more additional cascaded amplifier stages, each of which comprises a first stage coupled to the protection circuit,
At a given time, the circuit processes an RF signal through a plurality of activated cascaded amplifier stages, wherein the plurality of activated cascaded amplifier stages include only one of the plurality of cascaded amplifier stages or one or more additional plurality of cascaded amplifier stages, and
The circuit further comprises a protection circuit configured to programmatically generate said high value of said supply current based on a particular operating power requirement of each of said first stages of said activated plurality of cascaded amplifier stages. In paragraph 1,
A circuit further comprising a controller circuit configured to control operation of the protection circuit based on a value of a detected parameter, wherein the parameter comprises temperature or voltage. In paragraph 1,
The above circuit is a circuit that is monolithically integrated. A power amplifier module comprising the circuit of claim 1. As a method for protecting a multi-stage amplifier from high input power conditions,
A step of coupling the output leg of the current limiter circuit to the supply voltage node of the first stage of the multi-stage amplifier; and
Based on the above coupling, a step of limiting a high value of the current flowing through the first stage from the supply voltage node based on a reference current flowing through the input leg of the current limiter.
A method comprising: