KR20250032780A - Electronic device, memory device, and operating method thereof - Google Patents

Abstract

An electronic device, a memory device, and a method of operating the memory device are disclosed. A memory device according to the technical idea of the present disclosure includes a first bank including a first way group which receives power and stores a first cache line corresponding to a first address, a second bank including a second way group which receives power and stores a second cache line corresponding to a second address, a power control signal which instructs to stop supplying power to the first bank, and a second target which instructs the second bank based on the first address, and a cache controller configured to output the first address, and a way selector which is configured to transfer the first address to the second bank based on the first address, the power control signal, and the second target.

Description

ELECTRONIC DEVICE, MEMORY DEVICE, AND OPERATING METHOD THEREOF

The technical idea of the present disclosure relates to an electronic device, and more specifically, to an electronic device, a memory device, and an operating method of the memory device for improving the operation time, response time, processing speed, power consumption, etc. of a flush.

Semiconductor memory is widely used to store data in various electronic devices such as computers, wireless communication devices, etc. In SRAM (Static Random Access Memory), which is one type of semiconductor memory, a single-port SRAM and a dual-port SRAM capable of performing read and write operations at a higher speed than the single-port SRAM have been developed. While a conventional single-port SRAM has one unit memory cell composed of six transistors and can perform read and write operations sequentially, a dual-port SRAM adds two active transistors to a conventional single-port SRAM and is configured to perform read and write operations in dual mode, and is used in integrated circuits that require ultra-high speed.

The technical idea of the present disclosure provides an electronic device, a memory device and an operating method thereof for improving the operation time, response time, processing speed, power consumption, etc. of a flush.

A memory device according to the technical idea of the present disclosure includes a first bank including a first way group which receives power and stores a first cache line corresponding to a first address, a second bank including a second way group which receives power and stores a second cache line corresponding to a second address, a cache controller configured to output a power control signal which instructs to stop supplying power to the first bank, and a second target which instructs the second bank based on the first address, and a way selector configured to transfer the first address to the second bank based on the first address, the power control signal, and the second target.

In addition, a memory device according to the technical idea of the present disclosure includes a first bank including a first way group, a second bank including a second way group which receives power and stores a first cache line corresponding to a first address and a second cache line corresponding to a second address, a cache controller configured to output a power control signal instructing to supply power to the first bank, and a first target instructing the first bank based on the first address, and a way selector configured to transfer the first address to the first bank based on the first address, the power control signal, and the first target.

In addition, a method of operating a memory device according to the technical idea of the present disclosure includes a step of receiving a power control signal for instructing whether to supply power to a first bank group including at least one bank among a plurality of independently operable banks, a step of selecting a second bank group including at least one bank that is excluded from the first bank group and is supplied with power among the first bank group or the plurality of banks based on a transaction including an address and the power control signal, and a step of transmitting a transaction to the selected bank group based on the transaction and the power control signal.

In addition, an electronic device according to the technical idea of the present disclosure includes a memory including a processor configured to output a transaction including an operation request and an address, a power manager configured to generate power and output a power control signal instructing whether to supply power to a first bank group including at least one bank among a plurality of banks, and a plurality of banks that can be independently operated by receiving power, a cache controller configured to select the first bank group or a second bank group including at least one bank excluded from the first bank group and supplied with power among the plurality of banks based on the transaction and the power control signal, and a way selector configured to transmit the transaction to the bank group selected based on the transaction and the power control signal.

According to the technical idea of the present disclosure, there is an effect of improving the operation time, response time, processing speed, power consumption, etc. of the flush.

The effects obtainable from the embodiments of the present disclosure are not limited to the effects mentioned above, and other effects not mentioned can be clearly derived and understood by a person having ordinary knowledge in the technical field to which the embodiments of the present disclosure belong from the following description. That is, unintended effects resulting from practicing the embodiments of the present disclosure can also be derived from the embodiments of the present disclosure by a person having ordinary knowledge in the technical field.

FIG. 1 is a block diagram of an electronic device according to exemplary embodiments of the present disclosure.
FIGS. 2A, 2B, and 2C are diagrams illustrating exemplary embodiments of selecting a hash function according to a power control signal.
FIGS. 3, 4, and 5 are drawings illustrating the operation of a memory according to some embodiments of the present disclosure.
FIG. 6 is a flowchart illustrating the operation of an electronic device according to one embodiment of the present disclosure.
FIG. 7 is a drawing for explaining an exemplary embodiment of transmitting a first transaction to a bank when the operation according to FIG. 6 is performed.
FIG. 8 is a drawing for explaining an exemplary embodiment of transmitting a second transaction to a bank when the operation according to FIG. 6 is performed.
FIG. 9 is a flowchart illustrating the operation of an electronic device according to another embodiment of the present disclosure.
FIG. 10 is a drawing for explaining an exemplary embodiment of transmitting a transaction to a bank when the operation according to FIG. 9 is performed.
FIG. 11 is a flowchart illustrating the operation of an electronic device according to another embodiment of the present disclosure.
FIG. 12 is a drawing for explaining an exemplary embodiment of transmitting a transaction to a bank when the operation according to FIG. 11 is performed.
FIG. 13 is a block diagram of a way selector according to an exemplary embodiment of the present disclosure.
FIGS. 14, 15, and 16 are drawings for explaining the operation of an electronic device according to some other embodiments of the present disclosure.
FIG. 17 is a flowchart illustrating a cache hit operation and a cache miss operation according to exemplary embodiments of the present disclosure.
FIG. 18 is a block diagram of a bank according to an exemplary embodiment of the present disclosure.
FIG. 19 is a circuit diagram of a memory cell according to an exemplary embodiment of the present disclosure.
FIG. 20 is a flowchart illustrating a method of operating an electronic device according to exemplary embodiments of the present disclosure.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the attached drawings.

FIG. 1 is a block diagram of an electronic device according to exemplary embodiments of the present disclosure.

Referring to FIG. 1, an electronic device according to an embodiment of the present disclosure may be included in a mobile device such as a smart phone or a wearable device, and in this case, the electronic device (10) may be implemented as an application processor (AP) or a system-on-a-chip (SoC). However, the present invention is not limited thereto, and the electronic device (10) may be included in a computing device such as a personal computer (PC), a tablet PC, a server, etc.

The electronic device (10) may include a processor (110), a memory device (120), and a power manager (130).

The processor (110) may be a device capable of processing data, such as a CPU (Central Processing Unit), an NPU (Neural Processing Unit), a GPU (Graphics Processing Unit), an application processor (AP), etc. The processor (110) may execute an operating system (OS) and/or various applications. The processor (110) may transmit a transaction requesting to perform a specific operation to the memory device (120). In addition, the processor (110) may receive a response to the transaction from the memory device (120). For example, the processor (110) may transmit a transaction including a read request and an address to the memory device (120), and the memory device (120) may read data stored in a memory area corresponding to the address. However, the present invention is not limited thereto.

The memory device (120) may receive power from the power manager (130) to perform an operation. The memory device (120) may be referred to as a memory. The memory device (120) may include a cache controller (121), a way selector (122), and a plurality of banks (123_1, 123_2, ..., 123_n). The cache controller (121) may receive a transaction provided from the processor (110). The cache controller (121) may transfer the transaction to a bank corresponding to an address included in the transaction so as to access the bank. In one embodiment, the cache controller (121) may select a first bank group or a second bank group among the plurality of banks (123_1, 123_2, ..., 123_n) based on the transaction and the power control signal. The first bank group may include at least one bank among the plurality of banks (123_1, 123_2, ..., 123_n). The second bank group may include the remaining banks among the plurality of banks (123_1, 123_2, ..., 123_n) except for the first bank group. In some embodiments, the first bank group may include at least one bank whose power supply can be interrupted while the electronic device (10) is turned on, and the second bank group may include at least one bank designed to always be supplied with power while the electronic device (10) is turned on. The power control signal may be generated by the power manager (130). The way selector (122) may transmit the transaction to the selected bank group. In one embodiment, the way selector (122) may transmit the transaction to at least one way among the plurality of ways included in the selected at least one bank based on the transaction and the power control signal transmitted by the cache controller (121). The number of multiple banks (123_1, 123_2, ..., 123_n) may be n. n may be an integer greater than or equal to 2. Each of the multiple banks (123_1, 123_2, ..., 123_n) may be supplied with power generated by the power manager (130) and may operate independently. A bank may also be referred to as a slice.

In one embodiment, the memory device (120) may be implemented as an SRAM. The SRAM may be used as a cache in a computing device. In order to improve the throughput, which indicates the amount of data processed per unit time of the cache, an independently operable bank structure may be applied to the SRAM. The bank structure is a structure in which the cache is partitioned into multiple partitions so that each partition can be accessed simultaneously. When relatively low performance is required in the SRAM of the bank structure, some banks may be powered off for power saving. Meanwhile, when high performance is required in the SRAM of the bank structure, power may be supplied to the powered-off banks. When the power mode is transitioned, cache lines mapped to the powered-off banks must be redirected to the powered-on banks, and cache flushing may be performed to ensure normal operation. When the number of banks to be operated decreases, all cache lines of the banks being powered off must be flushed, and when the number of banks to be operated increases, cache lines of the banks that were powered on and that must be mapped to the newly powered-on banks must be flushed.

The power manager (130) can generate power. The power generated by the power manager (130) can be supplied to the processor (110) and/or the memory device (120). In one embodiment, the power generated by the power manager (130) can be supplied to at least one bank among the plurality of banks (123_1, 123_2, ..., 123_n). The power manager (130) can output a power control signal that instructs whether to supply power to a first bank group among the plurality of banks (123_1, 123_2, ..., 123_n). In one embodiment, the power manager (130) can output a power control signal that instructs whether to supply power (e.g., turn off or turn on) to be supplied to at least one bank. In another embodiment, the power manager (130) may output a power control signal that indicates a first mode for supplying power only to one specific bank (e.g., the first bank (123_1)) among the plurality of banks (123_1, 123_2, ..., 123_n), a second mode for supplying power to a preset number (e.g., n/2) of banks among the plurality of banks (123_1, 123_2, ..., 123_n), or a third mode for supplying power to the plurality of banks (123_1, 123_2, ..., 123_n). According to an embodiment, the power manager (130) may be implemented as a Power Management Unit (PMU).

The memory device (120) of the present disclosure can reduce power consumption while improving performance degradation in a system that controls power-performance balance through dynamic cache size adaptation. The memory device (120) of the present disclosure can be implemented as an L1 cache or an L2 cache of a CPU, and can also be implemented as an L3 cache of a CPU cluster. Alternatively, the memory device (120) of the present disclosure can be utilized in a cache built into a GPU or an NPU and an LLC (Last Level Cache) existing in a bus interconnect.

According to the above-described embodiment, there is an effect of improving the speed of changing the mode of turning the bank on or off, an effect of improving power consumption, and an effect of improving the response time.

FIGS. 2A, 2B, and 2C are diagrams illustrating exemplary embodiments of selecting a hash function according to a power control signal.

Referring to FIGS. 2A, 2B, and 2C, the memory (200) may correspond to the memory device (120) of FIG. 1. The cache controller (210) included in the memory (200) may select one hash function among a plurality of hash functions according to a power control signal. The cache controller (210) may input an address to the selected hash function, and generate and output a target as an output of the selected hash function. In one embodiment, the address included in each address group includes information necessary to identify whether a block in the cache is requested by the processor (110) or not, and may include a tag field composed of upper part bits of the address, and an index field including an index value indicating a specific way among a plurality of ways. The address may further include an offset field including an offset value. At this time, the tag field and the index field may be input to the hash function. The memory (200) may include a plurality of banks, for example, the memory (200) may include first to third banks (230_1, 230_2, 230_3), and the cache controller (210) may include first to third hash functions (211, 212, 213). However, the present invention is not limited thereto.

In one embodiment, the power control signal may instruct to supply power to at least one of the plurality of banks. For example, referring to FIGS. 2A, 2B, and 2C, the power control signal may instruct to supply power to only one of the first to third banks (230_1, 230_2, 230_3). As another example, the power control signal may instruct to supply power to only two of the first to third banks (230_1, 230_2, 230_3). As yet another example, the power control signal may instruct to supply power to all of the first to third banks (230_1, 230_2, 230_3). However, the present invention is not limited thereto. In another embodiment, the power control signal may also instruct to stop supplying power to one or two of the three banks. Hereinafter, it is assumed that the power control signal instructs at least one bank to supply power. In one embodiment, the first bank group of the present disclosure may include the first and second banks (230_1, 230_2), and the second bank group of the present disclosure may include the third bank (230_3).

Referring to FIG. 2a, a first power control signal (PCS1) may be input to the memory (200). The first power control signal (PCS1) may instruct to supply power to all of the first to third banks (230_1, 230_2, 230_3). The cache controller (210) may select a first hash function (211) in response to the first power control signal (PCS1). The cache controller (210) may input a first address group (ADDa) to the first hash function (211) and output a first target (TGT1) pointing to the first bank (230_1) (or representing the first bank (230_1)). The first address group (ADDa) may include a plurality of first addresses (ADDa1, ADDa2, ADDa3, ADDa4). Each of the plurality of first addresses (ADDa1, ADDa2, ADDa3) may correspond to at least one way included in the first bank (230_1). Although the number of the plurality of first addresses (ADDa1, ADDa2, ADDa3, ADDa4) is illustrated as four, this is only an example. The cache controller (210) may input the second address group (ADDb) to the first hash function (211) and output a second target (TGT2) pointing to the second bank (230_2). The second address group (ADDb) may include a plurality of second addresses (ADDb1, ADDb2, ADDb3, ADDb4). Each of the plurality of second addresses (ADDb1, ADDb2, ADDb3, ADDb4) may correspond to at least one way included in the second bank (230_2). The cache controller (210) can input a third address group (ADDc) to the first hash function (211) and output a third target (TGT3) pointing to the third bank (230_3). The third address group (ADDc) can include a plurality of third addresses (ADDc1, ADDc2, ADDc3, ADDc4). Each of the plurality of third addresses (ADDc1, ADDc2, ADDc3, ADDc4) can correspond to at least one way included in the third bank (230_3). In this way, when power is supplied to all banks, a specific address group can be mapped only to a specific bank.

Referring to FIG. 2b, a second power control signal (PCS2) may be input to the memory (200). The second power control signal (PCS2) may instruct to supply power only to two banks among the first to third banks (230_1, 230_2, 230_3), for example, the second and third banks (230_2, 230_3). Since the supply of power to the first bank (230_1) is cut off, the first address group (ADDa) needs to be remapped to another second bank (230_2) or third bank (230_2, 230_3) excluding the first bank (230_1). For example, some of the first addresses (ADDa1, ADDa2) among the plurality of first addresses (ADDa1, ADDa2, ADDa3, ADDa4) may be mapped to the second bank (230_2), and other of the first addresses (ADDa3, ADDa4) among the plurality of first addresses (ADDa1, ADDa2, ADDa3, ADDa4) may be mapped to the third bank (230_3). An embodiment of mapping some of the addresses is not limited to FIG. 2B and may be designed in various ways. The cache controller (210) may select the second hash function (212) in response to the second power control signal (PCS2). When the first addresses (ADDa1, ADDa2) are input to the cache controller (210), the cache controller (210) can output the second target (TGT2) using the second hash function (212). When some other first addresses (ADDa3, ADDa4) are input to the cache controller (210), the cache controller (210) can output the third target (TGT3) using the second hash function (212). When the second address group (ADDb) and/or the third address group (ADDc) are input to the cache controller (210), it is as described above with reference to FIG. 2a.

Referring to FIG. 2c, a third power control signal (PCS3) may be input to the memory (200). The third power control signal (PCS3) may instruct to supply power to only one of the first to third banks (230_1, 230_2, 230_3), for example, the third bank (230_3). Since the power supplied to the first bank (230_1) and the second bank (230_1) is cut off, the first address group (ADDa) and the second address group (ADDb) need to be remapped to the third bank (230_2, 230_3). To this end, the cache controller (210) may select the third hash function (213) in response to the third power control signal (PCS3). When the first address group (ADDa), the second address group (ADDb), or the third address group (ADDc) is input to the cache controller (210), the cache controller (210) can output the third target (TGT3) using the third hash function (213). In this way, when power supplied to at least one bank is cut off, a specific address group can be remapped to a bank different from the previously mapped bank.

Although not shown, the cache controller (210) may further include an arbitrator for forwarding the address (or transaction including the address) to the bank, depending on the target.

FIGS. 3, 4, and 5 are diagrams for explaining the operation of a memory according to some embodiments of the present disclosure. Specifically, FIG. 3 is a diagram for explaining an embodiment of transmitting a first transaction (TXNa) including an arbitrary first address (ADDai) to a first bank (230_1), and FIGS. 4 and 5 are diagrams for explaining an embodiment of transmitting a second transaction (TXNb) including an arbitrary second address (ADDb) to a second bank (230_2).

Referring to FIGS. 3, 4, and 5, the memory (200) may include a cache controller (210), a way selector (220), a first bank (230_1), and a second bank (230_2). Although the memory (200) is illustrated as including two banks in FIGS. 3, 4, and 5, this is merely for the purpose of illustratively explaining exemplary embodiments of the present disclosure. In one embodiment, the first bank (230_1) may be included in a first bank group as a bank whose power supply may be interrupted, and the second bank (230_2) may be included in a second bank group as at least one bank designed to always be supplied with power while the memory (200) is turned on. Each of the first bank (230_1) and the second bank (230_2) may be supplied with power (PWR) and operate independently. Each bank may include a plurality of ways. For example, each of the first bank (230_1) and the second bank (230_2) may include first to fourth ways (WAY1, WAY2, WAY3, WAY4). Although each of the first bank (230_1) and the second bank (230_2) is illustrated as including four ways in FIGS. 3, 4, and 5, the present invention is not limited thereto. Each of the first to fourth ways (WAY1, WAY2, WAY3, WAY4) may include at least one cache line. Each cache line may store a tag and data. For example, tags (TAG_a1, TAG_a2, TAG_a3, TAG_a4) and data (DATA_a1, DATA_a2, DATA_a3, DATA_a4) for the first address group (ADDa) may be stored in each cache line of the first to fourth ways (WAY1, WAY2, WAY3, WAY4) included in the first bank (230_1). The first address group (ADDa) may include, for example, four first addresses (ADDa1, ADDa2, ADDa3, ADDa4). At this time, the tag (TAG_a1) can point to the first address (ADDa1), the tag (TAG_a2) can point to the first address (ADDa2), the tag (TAG_a3) can point to the first address (ADDa3), and the tag (TAG_a4) can point to the first address (ADDa4). For example, in each of the first to fourth ways (WAY1, WAY2, WAY3, WAY4) included in the second bank (230_2), tags (TAG_b1, TAG_b2, TAG_b3, TAG_b4) and data (DATA_b1, DATA_b2, DATA_b3, DATA_b4) for the second address group (ADDb) can be stored. The tags (TAG_b1, TAG_b2, TAG_b3, TAG_b4) may point to second addresses (ADDb1, ADDb2, ADDb3, ADDb4) included in the second address group (ADDb), respectively. A first power control signal (PCS1) may be input to the cache controller (210) and the way selector (220). The first power control signal (PCS1) may instruct to supply power to the first and second banks (230_1, 230_2). The cache controller (210) may select a first hash function (211).

Referring to FIG. 3, any first address (ADDai) included in the first transaction (TXNa) may be mapped to the first bank (230_1). That is, the first transaction (TXNa) may be transmitted to the first bank (230_1). For example, an external device, such as the processor (110) of FIG. 1, of the memory (200) may output the first transaction (TXNa) including the arbitrary first address (ADDai) to the memory (200). The cache controller (210) may generate a first target (TGT1) indicating the first bank (230_1) based on the arbitrary first address (ADDai) and the first hash function (211). Then, the cache controller (120) may output the first target (TGT1) and the first transaction (TXNa). In one embodiment, the first target (TGT1) and the first transaction (TXNa) may be transmitted to the way selector (220). The way selector (220) may generate first way information (WI1) based on the first power control signal (PCS1), the first target (TGT1), and an arbitrary first address (ADDai). The way information may include a way to be mapped among a plurality of ways included in a bank. For example, the first way information (WI1) may indicate any one way among the first to fourth ways (WAY1, WAY2, WAY3, WAY4) included in the first bank (230_1). In one embodiment, the first way information (WI1) may include a way field. The way field may include information indicating a way to be masked and a way to be unmasked among a plurality of ways included in the bank. An unmasked way is accessed, and a masked way is not accessed. The way field will be described later with reference to FIGS. 8 to 13. The way selector (220) can output the first way information (WI1) and the first transaction (TXNa) to the first bank (230_1). The first bank (230_1) can perform an operation according to the request of the first transaction (TXNa) in a specific way mapped to (or corresponding to) any first address (ADDai). For example, when the first transaction (TXNa) includes a read request and the first address (ADDa1), the first bank (230_1) can determine whether there is a cache hit or a cache miss based on the tag (TAG_a1) of the cache line stored in the first way (WAY1), and if a cache hit occurs, can read and output data (DATA_a1).

Referring to FIG. 4, any second address (ADDbi) included in the second transaction (TXNb) may be mapped to the second bank (230_2). That is, the second transaction (TXNb) may be transmitted to the second bank (230_2). For example, the cache controller (210) may output a second target (TGT2) and a second transaction (TXNb) indicating the second bank (230_2) based on the arbitrary second address (ADDbi) and the first hash function (211). In one embodiment, the second target (TGT2) and the second transaction (TXNb) may be transmitted to the way selector (220). The way selector (220) may generate second way information (WI2) based on the first power control signal (PCS1), the second target (TGT2), and the arbitrary second address (ADDbi). For example, the second way information (WI2) may point to any one of the first to fourth ways (WAY1, WAY2, WAY3, WAY4) included in the second bank (230_2). In one embodiment, the second way information (WI2) may include a way field.

In one embodiment, the way selector (220) may be included in each of the first bank (230_1) and the second bank (230_2). However, the present invention is not limited thereto. In another embodiment, the way selector (220) may be included only in a bank that is designed to be always powered. For example, referring to FIG. 5, if the second bank (230_2) is designed to always be powered while the memory (200) is turned on, the way selector (220) may be included in the second bank (230_2). A second transaction (TXNb) including an arbitrary second address (ADDbi) may be transmitted to the second bank (230_2). At this time, the way selector (220) may transmit the second transaction (TXNb) to the second bank (230_2) so as to access the second bank (230_2) based on the second target (TGT2).

FIG. 6 is a flowchart illustrating the operation of an electronic device according to one embodiment of the present disclosure.

Referring to FIGS. 1 and 5, in step S110, the memory device (120) receives a request to turn off power to at least one bank. At this time, the request may correspond to the power control signal described above. For example, the power manager (130) may output a power control signal instructing to stop supplying power to the first bank group.

In step S120, the memory device (120) flushes at least one bank to be powered off. For example, the cache controller (121) may control the first bank group to flush the first bank group in response to the power control signal, and cache lines included in the first bank group may be flushed. The flush may include an operation of reading a tag of a cache line stored in the bank, and an operation of moving and storing data of the cache line stored in the bank to a memory or storage device of a lower layer than the memory device (120) using information included in the tag. If necessary, the flush may omit an operation of storing data of the cache line to a memory or storage device of a lower layer if the information included in the tag does not require an update of data to the memory or storage of a lower layer, such as when a dirty flag is not set. The memory layer may be composed of a register included in the processor, an L1 cache, an L2 cache, an L3 cache, a main memory, a secondary storage, etc. For example, if the memory device (120) is an L1 cache, a memory in a lower layer than the memory device (120) may be an L2 cache, an L3 cache, or a main memory, and a storage device in a lower layer than the memory device (120) may be a secondary storage. However, the present invention is not limited thereto. The main memory may correspond to, for example, DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), LPDDR (Low Power Double Data Rate) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, RDRAM (Rambus Dynamic Random Access Memory), etc. The secondary storage may correspond to, for example, a memory card, a PC card, a compact flash card, a smart media card, a memory stick, a multimedia card, an SD card, a universal flash memory device, an HDD (Hard Disk Drive), or an SSD (Solid State Disk/Drive).

In step S130, the memory device (120) changes the hash function of the master that generates the transaction request. For example, the master may be a cache controller (121), and the cache controller (121) may select a hash function from among a plurality of hash functions that receive an address and output a hash value as a target according to the request of step S110, and output the hash value of the selected hash function as a target.

In step S140, the power manager (130) turns off the power of at least one bank to be powered off. For example, the power manager (130) may stop supplying power to the first bank group after a flush operation for the first bank group is performed.

FIG. 7 is a drawing for explaining an exemplary embodiment of transmitting a first transaction to a bank when the operation according to FIG. 6 is performed.

Referring to FIGS. 6 and 7, before the second power control signal (PCS2) is input to the cache controller (210) and the way selector (220), the first bank (230_1) may include a first way group capable of receiving power (PWR) and storing a first cache line corresponding to the first address (ADDai). The first way group may include first to fourth ways (WAY1, WAY2, WAY3, WAY4). The second power control signal (PCS2) may be input to the cache controller (210) and the way selector (220). The second power control signal (PCS2) may instruct only one of the first and second banks (230_1, 230_2) to supply power to the second bank (230_2). The first bank (230_1) may flush the first cache line. At this time, if the tag and data of the first cache line are updated, the data of the first cache line may be stored in the memory of the lower layer (or the storage of the lower layer) as illustrated in FIG. 7. Unlike as illustrated in FIG. 7, if the tag and data of the first cache line are not updated and are maintained, the first cache line may not be stored in the memory of the lower layer (or the storage of the lower layer). Power (PWR) supplied to the first bank (230_1) may be cut off. The second bank (230_2) may include a second way group that receives power (PWR) and stores a second cache line corresponding to the second address (ADDbi). The second way group may include first to fourth ways (WAY1, WAY2, WAY3, WAY4). The second cache line corresponding to the second address may be, for example, a cache line of the first way (WAY1) or a cache line of the second way (WAY2) included in the second bank (230_2).

When the second power control signal (PCS2) is input to the memory (200), any first address (ADDai) may be remapped to the second bank (230_2). For example, the cache controller (210) may receive a first transaction (TXNa). The first transaction (TXNa) may include any first address (ADDai). The cache controller (210) may select a second hash function (212) in response to the second power control signal (PCS2). The cache controller (210) may generate the second bank (230_2) based on the second hash function (212) and the first transaction (TXNa). The cache controller (210) may output the second target (TGT2) and the first transaction (TXNa) to the way selector (220).

The way selector (220) may transmit the first transaction (TXNa) to at least one way of the second bank (230_2) based on the first transaction (TXNa), the second power control signal (PCS2), and the second target (TGT2). According to an embodiment, the way selector (220) may transmit the first transaction (TXNa) to at least one way of the second bank (230_2) based on the first address (ADDai) of the first transaction (TXNa) and the second power control signal (PCS2).

In one embodiment, the way selector (220) may generate a second way field (WF22) using an arbitrary first address (ADDai), a first power control signal (PCS1), and a second target (TGT2). At this time, the masked ways (MW) in the second way field (WF22) may be the first and second ways (WAY1, WAY2), and the unmasked ways (UMW) may be the third and fourth ways (WAY3, WAY4). However, the present invention is not limited thereto. The number of unmasked ways (UMW) may be preset. The first and second ways (WAY1, WAY2) may be included in a first way group, and the third and fourth ways (WAY3, WAY4) may be included in a second way group. The second bank (230_2) can access the third way (WAY3) and/or the fourth way (WAY4) to perform an operation according to the first transaction (TXNa). For example, the second bank (230_2) can determine whether there is a cache hit or a cache miss based on a tag stored in the third way (WAY3) and/or the fourth way (WAY4). In this case, if the tag stored in the third way (WAY3) and/or the fourth way (WAY4) does not exist or includes information about an address different from the first address (ADDai), a cache miss may occur.

FIG. 8 is a drawing for explaining an exemplary embodiment of transmitting a second transaction to a bank when the operation according to FIG. 6 is performed.

Referring to FIGS. 6 and 8, when a second power control signal (PCS2) is input to the memory (200), the first bank (230_1) may flush the first cache line, and power (PWR) supplied to the first bank (230_1) may be cut off. An arbitrary second address (ADDbi) may be remapped to the second bank (230_2), and a second transaction (TXNb) including the arbitrary second address (ADDbi) may be transmitted to the second bank (230_2). For example, the cache controller (210) may select a second hash function (212) and generate a second target (TGT2) based on the second hash function (212) and the arbitrary second address (ADDbi). The way selector (220) can generate a second way field (WF21) based on the second power control signal (PCS2) and an arbitrary second address (ADDbi), and in the second way field (WF22), the unmasked ways (UMW) can be the first to fourth ways (WAY1, WAY2, WAY3, WAY4), and there can be no masked ways (MW). That is, the second bank (230_2) can access the first to fourth ways (WAY1, WAY2, WAY3, WAY4).

FIG. 9 is a flowchart illustrating the operation of an electronic device according to another embodiment of the present disclosure.

Referring to FIG. 1 and FIG. 9, in step S210, the memory device (120) receives a request to turn on power of at least one bank. At this time, the request may correspond to the power control signal described above. The at least one bank may be, for example, the first bank (230_1) and may be included in the first bank group. For example, the power manager (130) may stop supplying power to the first bank group and supply power to the second bank group before a power control signal instructing to supply power to the first bank group is generated. Then, the power manager (130) may output the power control signal to the memory device (120).

In step S220, the power manager (130) turns on power to at least one bank, and the memory device (120) invalidates cache lines stored in at least one bank to be powered on. For example, the power manager (130) may supply power to a first bank group. The cache controller (121) may control the first bank group to invalidate cache lines included in the first bank group in response to the power control signal.

In step S230, the memory device (120) flushes all ways in at least one other bank that is not powered off. The at least one other bank that is not powered off may be, for example, the second bank (230_2) and may be included in the second bank group. For example, the cache controller (121) may control the second bank group (for example, the second bank (230_2)) to flush the first to fourth ways (WAY1, WAY2, WAY3, WAY4) of the second bank (230_2) included in the second bank group after the cache lines included in the first bank group are invalidated, and at this time, all cache lines included in the second bank (230_2) may be flushed.

In step S240, the memory device (120) changes the hash function of the master that generates the transaction request. That is, the hash function may be changed so that a first transaction (TXNa) including an arbitrary first address (ADDai) is transmitted to the first bank (230_1), and a second transaction (TXNb) including an arbitrary second address (ADDbi) is transmitted to the second bank (230_2). For example, the cache controller (210) may select the first hash function (211).

FIG. 10 is a drawing for explaining an exemplary embodiment of transmitting a transaction to a bank when the operation according to FIG. 9 is performed.

Referring to FIGS. 9 and 10, a first power control signal (PCS1) may be input to the memory (200). The first bank (230_1) may be supplied with power (PWR), and cache lines stored in the first to fourth ways (WAY1, WAY2, WAY3, WAY4) included in the first bank (230_1) may be invalidated. Meanwhile, the second bank (230_2) may flush all of the first to fourth ways (WAY1, WAY2, WAY3, WAY4).

When the first power control signal (PCS1) is input to the memory (200), any first address (ADDai) can be remapped to the first bank (230_1). An embodiment thereof may be the same as described above with reference to FIG. 3. The unmasked way (UMW) in the first way field (WF1) output by the way selector (220) may be the first to fourth ways (WAY1, WAY2, WAY3, WAY4). The way selector (220) may transfer the first way field (WF1) and the first transaction (TXNa) to the first bank (230_2).

In another embodiment, as illustrated in FIG. 10, for example, when the way selector (220) is included in the second bank (230_2) as described above with reference to FIG. 4, the cache controller (210) may transfer the first transaction (TXNa) to the first bank (230_1) according to the first target (TGT1).

FIG. 11 is a flowchart illustrating the operation of an electronic device according to another embodiment of the present disclosure.

Referring to FIGS. 1, 9, and 11, steps S210, S220, and S240 are as described above with reference to FIG. 9.

In step S231, the memory device (120) flushes predefined ways in at least one other bank that is not powered off. The at least one other bank that is not powered off may be, for example, the second bank (230_2), and the predefined ways may be the third and fourth ways (WAY3, WAY4) included in the second way group in the second bank (230_2) described above with reference to FIG. 7, as unmasked ways (UMWs). Flushing the predefined ways may be referred to as a partial flush.

FIG. 12 is a drawing for explaining an exemplary embodiment of transmitting a transaction to a bank when the operation according to FIG. 11 is performed.

Referring to FIGS. 7, 11, and 12, when a first power control signal (PCS1) is input to the memory (200), the first bank (230_1) is supplied with power (PWR), and the first to fourth ways (WAY1, WAY2, WAY3, WAY4) included in the first bank (230_1) may be processed as invalid. Meanwhile, the second bank (230_2) may partially flush predefined ways (for example, the third and fourth ways (WAY3, WAY4)) among the first to fourth ways (WAY1, WAY2, WAY3, WAY4). As described above with reference to FIG. 7, the first and second ways (WAY1, WAY2) can store cache lines corresponding to any second address (ADDbi), and the third and fourth ways (WAY3, WAY4) can store cache lines corresponding to any first address (ADDai). Meanwhile, the first transaction (TXNa) including any first address (ADDai) can be transmitted to the first bank (230_1).

FIG. 13 is a block diagram of a way selector according to an exemplary embodiment of the present disclosure.

Referring to FIG. 13, the way selector (300) may include a hash function (310), a plurality of way field generators, and a way field selector (340). The plurality of way field generators may include, but are not limited to, a first way field generator (320) and a second way field generator (330), and in other embodiments, three or more way field generators may be included in the way selector (300) depending on the number of banks and a power control signal.

The hash function (310) may output a selection signal (SEL) that instructs to select one of a plurality of way field generators (for example, the first way field generator (320) and the second way field generator (330)) based on the address (ADD) and the target (TGT). According to an embodiment, the hash function (310) may receive a tag field and an index field of the address (ADD) and output a selection signal (SEL). In one embodiment, the hash function (310) may be identical to the first hash function (211) of the cache controller (210). If the address (ADD) is the first address (ADDai), the selection signal (SEL) may be a first value. If the selection signal (SEL) is the first value, values output by each of the first registers (321, 331) may be selected. If the address (ADD) is the second address (ADDbi), the selection signal (SEL) can be the second value. If the selection signal (SEL) is the second value, the values output by each of the second registers (322, 332) can be selected.

The first way field generator (320) and the second way field generator (330) can output values of way fields that are stored in advance. In one embodiment, each of the first way field generator (320) and the second way field generator (330) can include a plurality of registers and a register selector. The number of the plurality of registers can be two, but is not limited thereto, and in another embodiment, three or more registers may be included in each way field generator depending on the number of banks and the power control signal.

The first way field generator (320) can generate a way field for mapping the first address (ADDai) to the first bank (230_1) and the second address (ADDbi) to the second bank (230_2). In one embodiment, the first way field generator (320) can include a first register (321), a second register (322), and a register selector (323). The first register (321) can store values of a way field (WF11) for mapping the first address (ADDai) and the first bank (230_1), and output the values of the way field (WF11) to the register selector (323). The second register (322) stores the values of the way field (WF12) for mapping the second address (ADDbi) and the second bank (230_2), and can output the values of the way field (WF12) to the register selector (323). In one embodiment, the values of each of the way fields (WF11, WF12) can be bit values (b4, b3, b3, b1). Each bit value can indicate whether each way is masked. The bit values (b4, b3, b3, b1) can be configured in various ways, such as, for example, '0001', '0011', '0111', '1111', etc. The bit value (b4) may indicate whether the fourth way (WAY4) is masked, the bit value (b3) may indicate whether the third way (WAY3) is masked, the bit value (b2) may indicate whether the second way (WAY2) is masked, and the bit value (b1) may indicate whether the first way (WAY1) is masked. For example, “0001” may indicate that the second to fourth ways (WAY2, WAY3, WAY4) are masked and the first way (WAY1) is unmasked. Depending on an embodiment in which the way selector (300) is included in the second bank (230_2), the first register (321) may be omitted. In one embodiment, the way field (WF12) may have values indicating that all of the first to fourth ways (WAY1, WAY2, WAY3, WAY4) are unmasked. The register selector (323) can select output values of the first register (321) or the second register (322) according to the selection signal (SEL). For example, if the selection signal (SEL) has a first value, the register selector (323) can output values of the way field (WF11) stored in the first register (321). If the selection signal (SEL) has a second value, the register selector (323) can output values of the way field (WF12) stored in the second register (322).

The second way field generator (330) can generate a way field for mapping a first address (ADDai) to some predefined ways (e.g., the third and fourth ways (WAY3, WAY4)) in the second bank (230_2) and for mapping a second address (ADDbi) to some ways (e.g., the first to fourth ways (WAY1, WAY2, WAY3, WAY4)) of the second bank (230_2). In one embodiment, the second way field generator (330) can include a first register (331), a second register (332), and a register selector (333). The first register (331) can store values of a way field (WF21) for mapping the first address (ADDai) and some predefined ways, and output the values of the way field (WF21) to the register selector (333). The second register (332) stores the values of the way field (WF22) for mapping the second address (ADDbi) and the second bank (230_2), and can output the values of the way field (WF12) to the register selector (333). In one embodiment, the values of each of the way fields (WF21, WF22) may be bit values (b4, b3, b3, b1) indicating whether each way is masked. For example, the bit values (b4, b3, b3, b1) of the way field (WF21) may be "1100", and the bit values (b4, b3, b3, b1) of the way field (WF22) may be "1111". However, the present invention is not limited thereto, and the bit values may be set in various design methods. The register selector (333) can select the output values of the first register (321) or the second register (322) according to the selection signal (SEL).

The way field selector (340) can select the output values of the first way field generator (320) or the second way field generator (330) as the way field (WR) according to the power control signal (PCS). For example, if the power control signal (PCS) is the first power control signal (PCS1), the way field selector (340) can output the output values of the first way field generator (320). The first power control signal (PCS1) can instruct to supply power to the first and second banks (230_1, 230_2). If the power control signal (PCS) is the second power control signal (PCS2), the way field selector (340) can output the output values of the second way field generator (330). The second power control signal (PCS2) can instruct to supply power only to the second bank (230_2).

Although not shown, in another embodiment, the way selector (300) may, similarly to the cache controller (210), select one of the hash functions among a plurality of hash functions according to a power control signal (PCS), and output way information based on the selected hash function and an address (ADD).

FIGS. 14, 15, and 16 are drawings for explaining the operation of an electronic device according to some other embodiments of the present disclosure.

Referring to FIGS. 14, 15, and 16, the electronic device (400) may include an applied cache having a bank structure. The cache included in the electronic device (400) may include a plurality of hash functions (410, 430), a plurality of arbitrators (420, 440), and a plurality of banks (450, 460). According to an embodiment, the hash function (410) and the arbitrator (420) may be implemented outside the cache. The cache included in the electronic device (400) performs hash functioning based on an address of a cache line through request arbitration logic to determine which bank to allocate an address (or cache line). Accordingly, a bank to be allocated may be distinguished according to an address pattern. When a part of a bank is powered off, the request arbitration logic can be changed so that the cache lines assigned to the corresponding bank are assigned to other banks that are powered on. At this time, the cache lines of the bank that is the target of the power-off are flushed, so that the changed information can be updated in the cache. Meanwhile, when the powered-off bank is powered on again, the request arbitration logic that assigns the address to other banks that were previously powered on can be restored to its original state. At this time, among the cache lines of other banks that were previously powered on, the cache lines that should be allocated to the newly powered-on bank must be flushed, so that normal operation of the cache can be guaranteed thereafter. Since the complexity of the operation of finding the corresponding cache lines can be high, a method of flushing all the powered-on banks can be used to improve the complexity. The banks can be selected through the results of applying the values of the address to hash functions that are hardwired to the CPU slave and master ports. For example, a mode may be selected where only one bank is powered on, or where only half of the banks are powered on, or where all banks are powered on. Depending on the mode selected among the hash functions hardwired to the CPU slave and master ports in the replacement logic included in a particular bank, only pre-designated ways may be selected if the bank pointed to by the result of a particular hash function is different from the particular bank.

Referring to FIG. 14, when an address (411) of a requested transaction is input into a hash function (410), the hash function (410) and the arbitrator (420) can determine which bank the corresponding transaction will be arbitrated to among bank 0 (450) and bank 1 (460). In one embodiment, the hash function (410) and the arbitrator (420) may be included in the cache memory (121) of FIG. 1. However, the present invention is not limited thereto. In another embodiment, the hash function (410) and the arbitrator (420) may be implemented in a bridge of the electronic device (400). By means of the hash function (410) and the arbitrator (420), address group A (Address group A, 421) can be arbitrated and transferred to bank 0 (450), and address group B (Address group B, 422) can be arbitrated and transferred to bank 1 (460). Address group A (421) arbitrated to bank 0 (450) can be arbitrated again by the hash function (430) and the arbitrator (440). When bank 1 (460) is in a powered-on state, address group A (441) can be allocated to all of the ways (Way0, Way1, Way2, Way3) included in bank 0 (450). Address group B (442) cannot be allocated to bank 0 (450). When information (412) instructing to power off bank 1 (460) is input to the electronic device (400), the cache lines stored in bank 1 (460) can be flushed.

Referring to FIG. 15, information (412) indicating that bank 1 (460) is powered off may be transmitted to the hash function (410) and the hash function (430). Address group B (424) may be arbitrated and transmitted to bank 0 (450) without being arbitrated to bank 1 (460). That is, address groups A and B (423) may be arbitrated and transmitted to bank 0 (450). By the hash function (430) and the arbitrator (440), address group A (441) may be assigned to all of the ways (Way0, Way1, Way2, Way3) included in bank 0 (450), and address group B (443) may be assigned to some predefined ways (Way2, Way3). Address group B (443) may be managed only in some ways (Way2, Way3).

Referring to FIG. 16, information (413) instructing to power on bank 1 (460) may be input to the electronic device (400). In this case, since the hash function (410) and the arbitrator (420) can no longer transfer address group B (442) to bank 0 (450), all cache lines corresponding to address group B among all cache lines stored in bank 0 (450) must be flushed. For example, only cache lines stored in some predefined ways (Way2, Way3) may be read. Then, it may be checked through a tag whether an address stored in the corresponding cache lines corresponds to address group B. Then, the corresponding cache lines may be flushed. However, the present invention is not limited thereto, and the process of checking the address using the tag may be omitted in order to increase the processing speed.

According to the above-described embodiments, by presetting the number of ways for allocating a cache line to a bank other than a specific bank and flushing only the preset ways in the other bank when the specific bank transitions from power off to power on, there is an effect of improving performance degradation, reducing response time, reducing flushing operation time, and reducing power consumption.

FIG. 17 is a flowchart illustrating a cache hit operation and a cache miss operation according to exemplary embodiments of the present disclosure.

Referring to FIG. 17, in step S310, the memory device receives transaction requests. In step S320, the memory device checks for a cache hit/miss. In step S330, the memory device determines whether the transaction request is a cache hit. If the transaction request is a cache hit (S330, Yes), in step S340, the memory device processes the transaction request for a cache line hit. If the transaction request is a cache miss (S330, No), in step S350, the memory device checks the address group using a hash function used when all banks are powered on. In step S360, the memory device determines whether the address group of the request is an address group for the bank. If the address group of the request is an address group for the bank (S360, Yes), in step S370, the memory device selects a victim line from all ways. The victim line may be a cache line for storing data stored in a lower-layer memory or storage when a cache miss occurs. If the address group of the corresponding request is not an address group for the corresponding bank (S360, No), the memory device selects a victim line from the predefined ways. In step S390, the memory device can perform a cache miss operation for the selected victim line.

FIG. 18 is a block diagram of a bank according to an exemplary embodiment of the present disclosure.

Referring to FIG. 18, the bank (500) may receive a command (CMD), an address (ADDR), a clock (CLK), and input data (DATA_IN) during a write operation. For example, the bank (500) may receive a command (CMD), an address (ADDR), and input data (DATA_IN) instructing a write operation, and store the input data (DATA_IN) in a memory cell area corresponding to the address (ADDR) in the memory cell array (510). The bank (500) according to one embodiment of the present disclosure may receive a command (CMD), an address (ADDR), and a clock (CLK) during a read operation. For example, the bank (500) may receive a command (CMD) and an address (ADDR) instructing a read operation, read data stored in a memory cell area corresponding to the address (ADDR), and output the read data to the outside as output data (DATA_OUT).

In one embodiment, a bank (500) may include a memory cell array (510), a column decoder (520), a row decoder (530), a light driver/sense amplifier (540), input/output circuitry (550), and control logic (560).

The memory cell array (510) may include a plurality of memory cells (511). The plurality of memory cells (511) may be arranged at points where word lines (WLs) and bit lines (BLs) intersect. The column decoder (520) may select at least one bit line among the plurality of bit lines (BLs) based on a column address (CA). The row decoder (530) may activate at least one word line among the plurality of word lines (WLs) based on a row address (RA). That is, the row decoder (530) may select at least one word line among the plurality of word lines (WLs).

The write driver/sense amplifier (540) can transmit input data (DATA_IN) transmitted from the input/output circuit (550) to the column decoder (520) during a write operation. Alternatively, the write driver/sense amplifier (540) can amplify data transmitted from the column decoder (520) during a read operation and transmit output data (DATA_OUT) to the input/output circuit (550). The input/output circuit (550) can transmit input data (DATA_IN) to the write driver/sense amplifier (540). Alternatively, the input/output circuit (550) can output output data (DATA_OUT) transmitted from the write driver/sense amplifier (540).

The control logic (560) can receive a command (CMD), an address (ADDR), and a clock (CLK), and can generate a row address (RA), a column address (CA), and a control signal (CTR). For example, the control logic (560) can identify a read command by decoding the command (CMD), and can generate a row address (RA), a column address (CA), and a control signal (CTR) to read output data (DATA_OUT) from the memory cell array (510). In addition, the control logic (560) can identify a write command by decoding the command (CMD), and can generate a row address (RA), a column address (CA), and a control signal (CTR) to write input data (DATA_IN) to the memory cell array (510).

FIG. 19 is a circuit diagram of a memory cell according to an exemplary embodiment of the present disclosure.

Referring to FIG. 19, when the bank (500) is included in the SRAM, the memory cell (MC) may be an SRAM cell composed of 6 transistors. The memory cell (MC) may be referred to as a 6T SRAM cell. The memory cell (MC) may include first and second PMOS transistors (P1, P2) and first to fourth NMOS transistors (N1, N2, N3, N4). The first and second PMOS transistors (P1, P2) may be connected between a power supply voltage (VDD) line and a first node (A) and a second node (B), respectively. The first and second NMOS transistors (N1, N2) may be connected between a ground voltage (VSS) line and the first node (A) and the second node (B), respectively. The first node (A) may be connected to the gates of each of the second PMOS transistor (P2) and the second NMOS transistor (N2). The second node (B) may be connected to the gates of the first PMOS transistor (P1) and the first NMOS transistor (N1), respectively. The first node (A) and the second node (B) may be connected to the bit line (BL) and the complementary bit line (/BL) by the third and fourth NMOS transistors (N3, N4), respectively. The gates of the third and fourth NMOS transistors (N3, N4) may be connected to the word line (WL). The third and fourth NMOS transistors (N3, N4) may be referred to as access transistors or pass transistors. The memory cell (MC) may store data and complementary data in the first node (A) and the second node (B), and maintain the latched state thereof. Specifically, when the word line (WL) is enabled in a write operation, data and complementary data transferred to the bit line (BL) and the complementary bit line (/BL) through the third and fourth NMOS transistors (N3, N4) can be latched at the first node (A) and the second node (B). Meanwhile, in the memory cell (MC), when the word line (WL) is enabled in a read operation, data latched at the first node (A) and the second node (B) can be transferred to the bit line (BL) and the complementary bit line (/BL) through the third and fourth NMOS transistors (N3, N4). In another embodiment, the memory cell (MC) may include a first inverter and a second inverter. The first inverter may be composed of a first PMOS transistor (P1) and a first NMOS transistor (N1). The second inverter may be composed of a second PMOS transistor (P2) and a second NMOS transistor (N2).

FIG. 20 is a flowchart illustrating a method of operating an electronic device according to exemplary embodiments of the present disclosure.

Referring to FIG. 20, the operating method of the electronic device may include a step of receiving a power control signal (S1000), a step of selecting a bank group (S2000), and a step of transmitting a transaction to the selected bank group (S3000).

In step S1000, the electronic device receives a power control signal instructing whether to supply power to a first bank group including at least one bank among a plurality of independently operable banks.

In step S2000, the electronic device selects a first bank group or a second bank group excluding the first bank group among a plurality of banks based on a transaction and power control signal including an address.

In step S3000, the electronic device transmits a transaction to a selected bank group based on the transaction and power control signals.

In one embodiment, in step S1000, a first power control signal instructing to stop supplying power to a first bank group may be transmitted to the memory device (120). Step S2000 may include a step in which the memory device (120) outputs a first transaction including a first address corresponding to the first bank group, and a target instructing at least one bank included in a second bank group based on the first power control signal, and a step in which the memory device (120) selects a way included in at least one bank of the second bank group based on the first transaction and the target. At this time, the operating method of the electronic device may further include a step of flushing the first bank group.

In another embodiment, in step S1000, a second power control signal instructing to supply power to the first bank group may be transmitted to the memory device (120). Step S2000 may include a step in which the memory device (120) outputs a target instructing at least one bank included in the first bank group based on a first transaction including a first address corresponding to the first bank group and the second power control signal, and a step in which the memory device (120) selects a way included in at least one bank of the first bank group based on the first transaction and the target. At this time, the operating method of the electronic device may further include a step of flushing the second bank group.

It will be apparent to those skilled in the art that the structure of the present disclosure may be variously modified or changed without departing from the scope or technical spirit of the present disclosure. In view of the foregoing, if the modifications and variations of the present disclosure fall within the scope of the following claims and their equivalents, the present disclosure is deemed to include the modifications and variations of this invention.

As described above, exemplary embodiments have been disclosed in the drawings and the specification. Although specific terms have been used in the specification to describe the embodiments, these have been used only for the purpose of explaining the technical idea of the present disclosure and have not been used to limit the meaning or the scope of the present disclosure described in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Accordingly, the true technical protection scope of the present disclosure should be determined by the technical idea of the appended claims.

Claims (20)

A first bank including a first way group that is powered and stores a first cache line corresponding to a first address;
A second bank including a second way group that receives the power and stores a second cache line corresponding to a second address;
A cache controller configured to output a power control signal instructing to stop supplying the power to the first bank, and a second target instructing the second bank based on the first address; and
A memory device comprising a way selector configured to transmit the first address to the second bank based on the first address, the power control signal, and the second target. In the first paragraph,
The above cache controller,
A first hash function that receives the first address and outputs a first target indicating the first bank, receives the second address and outputs the second target, and includes a second hash function that outputs the second target.
A memory device characterized in that the second hash function is selected in response to the power control signal among the first hash function and the second hash function. In the first paragraph,
The above way selector is,
A hash function configured to receive the first address and output a selection signal;
A first way field generator configured to output a way field that maps the first address to the first way group and maps the second address to the second way group based on the selection signal;
A second way field generator configured to output a way field that maps the first address to some preset ways in the second way group based on the selection signal and maps the second address to the second way group; and
A memory device characterized by including a way field selector configured to output a way field of a way field generator selected from among the first way field generator and the second way field generator according to the value of the power control signal. In the third paragraph,
The above first way field generator,
A first register storing bit values including mapping information between the first address and the first way group;
A second register storing bit values including mapping information between the second address and the second way group; and
A memory device characterized by including a register selector that outputs bit values of a register selected from among the first register and the second register according to the value of the selection signal. In the third paragraph,
The above second way field generator,
A first register storing bit values including mapping information between the first address and some of the preset ways;
A second register storing bit values including mapping information between the second address and the second way group; and
A memory device characterized by including a register selector that outputs bit values of a register selected from among the first register and the second register according to the value of the selection signal. In the first paragraph,
The above cache controller,
A memory device characterized in that, in response to the power control signal, the first bank is controlled to flush the first cache line. In the first paragraph,
The above cache controller,
Based on the second address, output the second target to the way selector,
The above way selector is,
A memory device characterized in that the second address is transmitted to the second bank so as to access the second bank based on the second target. In the first paragraph,
A memory device, characterized in that the way selector is included in the second bank. A first bank containing a first way group;
A second bank including a second way group that receives power and stores a first cache line corresponding to a first address and a second cache line corresponding to a second address;
A power control signal instructing to supply power to the first bank, and a cache controller configured to output a first target instructing the first bank based on the first address; and
A memory device comprising a way selector configured to transmit the first address to the first bank based on the first address, the power control signal, and the first target. In Article 9,
The above cache controller,
A memory device characterized in that, in response to the power control signal, the first bank is controlled to invalidate cache lines stored in the first way group. In Article 9,
The above cache controller,
A memory device characterized in that, in response to the power control signal, the second bank is controlled to flush at least one cache line included in the second way group. In Article 11,
The above cache controller,
A memory device characterized by controlling the second bank to flush all cache lines included in the second way group. In Article 11,
The above cache controller,
A memory device characterized by controlling the second bank to flush the first cache line. In Article 9,
The above cache controller,
A first hash function that receives the first address and outputs the first target, receives the second address and outputs the second target indicating the second bank, and a second hash function that outputs the second target,
A memory device characterized in that the first hash function is selected in response to the power control signal among the first hash function and the second hash function. In Article 9,
The above way selector is,
A hash function configured to receive the first address and output a selection signal;
A first way field generator configured to output a way field that maps the first address to the first bank and the second address to the second bank based on the selection signal;
A second way field generator configured to output a way field that maps the first address to some preset ways in the second way group based on the selection signal and maps the second address to the second way group; and
A memory device characterized by including a way field selector configured to output a way field of a way field generator selected from among the first way field generator and the second way field generator according to the value of the power control signal. A step of receiving a power control signal instructing whether to supply power to a first bank group including at least one bank among a plurality of independently operable banks;
A step of selecting a second bank group including at least one bank that is excluded from the first bank group and supplied with power among the first bank group or the plurality of banks, based on a transaction including an address and the power control signal; and
A method of operating a memory device, comprising the step of transmitting the transaction to the selected bank group based on the transaction and the power control signal. In Article 16,
The step of receiving the above power control signal is:
receiving a first power control signal instructing to supply the power to the first bank group;
The above selection steps are:
A step of outputting a first transaction including a first address corresponding to the first bank group, and a target indicating at least one bank included in the first bank group based on the first power control signal; and
A method of operating a memory device, characterized by comprising the step of selecting a way included in at least one bank of the first bank group based on the first transaction and the target. In Article 17,
A method of operating a memory device, characterized in that it further comprises the step of flushing the second bank group. In Article 16,
The step of receiving the above power control signal is:
receiving a second power control signal instructing to stop supplying said power to said first bank group;
The above selection steps are:
A step of outputting a first transaction including a first address corresponding to the first bank group, and a target indicating at least one bank included in the second bank group based on the second power control signal; and
A method of operating a memory device, characterized by comprising the step of selecting a way included in at least one bank of the second bank group based on the first transaction and the target. In Article 19,
A method of operating a memory device, characterized in that it further comprises a step of flushing the first bank group.

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