KR20190064200A - Display device - Google Patents

Abstract

A display device according to the present invention includes a display panel having a plurality of pixels including a light emitting element, a capacitor for storing a data voltage corresponding to image data, and a drive transistor for causing a drive current corresponding to a data voltage to flow in the light emitting element, ; A timing controller for generating a control signal for controlling the driving of the display panel, analyzing the image data, and generating a voltage control signal based on the analyzed data; And a power generator for varying an initialization voltage for initializing a plurality of pixels based on the voltage control signal and supplying the initialization voltage to the display panel. The timing controller compares the video data of the n-th frame with the video data of the (n + 1) -th frame and outputs a voltage control signal as a first logic value for raising the level of the initialization voltage when the luminance change is larger than a predetermined value And generate a second logic value that causes the voltage control signal to lower the level of the initialization voltage when the luminance change is smaller than the predetermined value. Therefore, even if a rapid screen switching occurs, the screen drag phenomenon is reduced, and sufficient black luminance can be ensured even for low gradation data.

Description

Display device {DISPLAY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to a display device for adjusting a voltage for initializing a light emitting element.

The active matrix type organic light emitting display includes an organic light emitting diode (OLED) that emits light by itself, has a high response speed, and has advantages of high luminous efficiency, high luminance, and wide viewing angle.

The OLED that emits light by itself includes an anode electrode, a cathode electrode, and organic compound layers (HIL, HTL, EML, ETL, EIL) formed therebetween. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer EIL). When a driving voltage is applied to the anode electrode and the cathode electrode, holes passing through the HTL and electrons passing through the ETL are transferred to the EML to form excitons, Thereby generating visible light.

The organic light emitting display device arranges pixels each including an OLED in a matrix form and controls the amount of emitted light of the OLED according to the gradation of the image data to adjust the luminance. Each pixel circuit includes a light emitting element OLED, a switch transistor or a TFT (Thin Film Transistor) for controlling the application of a data voltage corresponding to the gray level, a pixel current flowing in the OLED according to a voltage applied between the gate electrode and the source electrode And a capacitor for storing a data voltage, and may further include a plurality of switch transistors for threshold voltage detection, light emission control, initialization control, etc. of the driving transistor.

When driving a pixel including an OLED, a low voltage initialization voltage is applied to the anode of the OLED and / or the gate electrode of the driving transistor before applying a data voltage corresponding to the gradation to be displayed by the pixel to the pixel circuit Thereby removing the charge remaining in the OLED and initializing the gate electrode of the driving transistor.

When the initialization voltage for subtracting the remaining charge in the OLED is low, the luminance corresponding to the black data may be sufficiently low. However, if the initialization voltage is too low, it takes time for the data voltage corresponding to the gray level to exceed the threshold voltage of the driving transistor, It can have a bad influence.

Particularly, when there is a screen switching with a large difference in brightness, a screen drag phenomenon occurs in which a residual image of the previous screen remains on the next screen, resulting in degraded display quality and adverse effect on the user's eyes.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an organic light emitting display device in which screen drag phenomenon is reduced.

An object of the present invention is to provide an organic light emitting display device capable of ensuring a sufficiently low luminance and improving a response speed.

A display device according to an embodiment of the present invention includes a plurality of pixels including a light emitting element, a capacitor for storing a data voltage corresponding to image data, and a driving transistor for causing a driving current corresponding to a data voltage to flow in the light emitting element A display panel; A timing controller for generating a control signal for controlling the driving of the display panel, analyzing the image data, and generating a voltage control signal based on the analyzed data; And a power generator for varying an initialization voltage for initializing a plurality of pixels based on the voltage control signal and supplying the initialization voltage to the display panel.

In one embodiment, the initialization voltage may initialize at least one of the gate electrode of the driving transistor and the anode electrode of the light emitting element before the data voltage corresponding to the image data is applied to the pixel.

In one embodiment, the timing controller includes a sampling period in which an initialization voltage is applied to the gate electrode of the driving transistor, a sampling period in which an initialization voltage is applied to the anode electrode of the light emitting element and a threshold voltage of the driving transistor is sampled and stored in a capacitor, One frame can be dividedly driven in an emissive period in which a current flows to the light emitting element and the light emitting element emits light.

In one embodiment, the timing controller compares the image data of the n-th frame with the image data of the (n + 1) -th frame to raise the voltage control signal to the level of the initialization voltage when the luminance change is larger than the predetermined value And generate a second logic value that causes the voltage control signal to lower the level of the initialization voltage when the luminance change is smaller than the predetermined value.

In one embodiment, the timing controller includes an APL calculation unit for calculating an average picture level (APL) for each frame, an APL difference calculation unit for calculating an APL difference value between two consecutive frames, and an APL difference calculation unit And a voltage control signal generator for generating a voltage control signal of the first logic value and generating a voltage control signal of the second logic value when the APL difference value is smaller than the first value.

In one embodiment, the voltage control signal generator may generate a voltage control signal of a first logic value when the APL difference value is less than the first value and the APL of the nth frame and the (n + 1) th frame is greater than the second value have.

In one embodiment, when the APL difference value between the n-th frame and the (n + 1) -th frame is larger than the first value, You can raise the level.

In one embodiment, the voltage control signal generator may generate the voltage control signal as the first logic value for a predetermined number of frame periods when the APL difference value between the n-th frame and the (n + 1) -th frame is greater than the first value .

In one embodiment, the timing controller generates the histogram of the n-th frame and the histogram of the (n + 1) -th frame, calculates the position of the peak, the interval between the power and the peak for each histogram, It is possible to determine whether the luminance change between the two frames is larger than a predetermined value based on the analysis of the change of the peak by comparing the two histograms.

In one embodiment, the pixel comprises: a first transistor for applying a data voltage to the source electrode of the driving transistor; A second transistor for applying a high potential voltage output from the power generator to the source electrode of the driving transistor; A third transistor for connecting the gate electrode and the drain electrode of the driving transistor; A fourth transistor for connecting the drain electrode of the driving transistor and the anode electrode of the light emitting element; A fifth transistor for applying an initializing voltage to a gate electrode of the driving transistor; And a sixth transistor for applying an initialization voltage to the anode electrode of the light emitting device.

In one embodiment, the display device comprises: a data driving circuit for applying a data voltage to a pixel; A first scan signal for activating the fifth transistor in the initialization period, a second scan signal for activating the first, third, and sixth transistors during the sampling period, and a second scan signal for activating the second and sixth transistors in the emission period And a gate driving circuit for generating an emission signal for the emission signal.

A method of adjusting an initialization voltage in a display device according to another exemplary embodiment of the present invention includes analyzing image data to be displayed on a display panel having a plurality of pixels including a light emitting element and a driving transistor for driving a current to the light emitting element Obtaining a difference value of an average picture level (APL) of two consecutive frames; Generating a voltage control signal at an initialization voltage that initializes at least one of a gate electrode of the driving transistor and an anode electrode of the light emitting element to a first logic value when the APL difference value is greater than a first value; Generating a voltage control signal at a second logic value when the APL difference value is less than a first value; And generating an initialization voltage based on the voltage control signal, wherein when the initialization voltage is the first logic value, the initialization voltage is raised, and when the initialization voltage is the second logic value, the initialization voltage is decreased.

Therefore, even when the screen is switched quickly from a low gray level to a high gray level, the screen drag phenomenon is reduced, and a sufficient black brightness can be secured even for low gradation data, thereby solving the problem of defective due to an optical compensation error.

FIG. 1 shows an example in which screen switching occurs between two frames having a large luminance difference,
FIG. 2 shows an example in which a residual image remains in pixels displaying a low gray level at the time of screen switching as shown in FIG. 1,
FIG. 3 is a table showing display quality indices such as optical compensation error, black luminance, response speed, and the like for various initialization voltages.
4 is a block diagram of a display device to which the present invention is applied,
Fig. 5 shows an equivalent circuit of a pixel to which the present invention is applied,
FIG. 6 shows the waveform of the driving signal applied to the pixel of FIG. 5 and the voltage change of the main node,
FIG. 7 shows a voltage of a main node when a data voltage of black to black to white gradation is applied to three consecutive frames,
8 illustrates an embodiment of adjusting the initialization voltage according to the present invention,
9 is a block diagram for generating a control signal for controlling an initialization voltage through image analysis according to an embodiment of the present invention,
10 is a flowchart illustrating a process of adjusting an initialization voltage through image analysis according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

FIG. 1 shows an example in which screen switching occurs in two frames having a large luminance difference. FIG. 2 shows an example in which a residual image remains in pixels displaying low gray levels in the screen switching as shown in FIG.

The average picture level (APL) is defined as the luminance average of the brightest color in one frame of image data, and can be expressed as Equation (1).

Max (R, G, B)} denotes a maximum value among R, G, and B, and R, G, Is the sum of the maximum values of R, G, and B. An image with a large number of bright pixel data has a high average image level, whereas a small number of bright pixel data has a low average image level. When the pixel data is 8 bits, the tone value of the peak white gray level is 255.

1, an n-th frame (Frame #n) displays a peak white gradation of about 25% of all the pixels on the screen, and the remaining pixels represent 0 (zero) of black gradation, so that the APL is 25%. On the other hand, the (n + 1) th frame (Frame # (n + 1)) shows 255 pixels, which are peak white gradations of all the pixels on the screen.

When there is a scene change from the small n-th frame (Frame #n) to the (n + 1) -th frame (n + 1) in which the APL is large, the response speed of the pixel circuit is slow (n + 1) -th frame (Frame # (n + 1)) to the peak white gradation in the nth frame (Frame # n + 1)), the peak white gradation can not be properly displayed and the gradation lower than the peak white gradation is displayed.

In the opposite case, that is, when the APL changes from a large frame to an APL small frame, the pixels displaying white gradation in the previous frame but changing to black gradation in the next frame do not display black gradation properly in the next frame, The gradation is displayed.

On the other hand, one electrode of the OLED, for example, an anode electrode, may be initialized to an initialization voltage between the frame and the frame, and the initialization voltage is set so that the voltage difference across the OLED is smaller than the threshold voltage of the OLED.

Further, in order to emit light of the OLED, the voltage of the anode electrode of the OLED must be increased so that the voltage difference between both ends of the OLED is larger than the threshold voltage of the OLED. That is, the current outputted when the driving transistor is turned on charges the parasitic capacitor of the OLED so that the anode electrode of the OLED is raised from the initializing voltage, and the voltage difference across the OLED must increase to a value equal to or higher than the threshold voltage of the OLED.

Further, in order for the OLED to express the desired gradation, the current output from the driving transistor increases and the anode electrode of the OLED must increase from the initialization voltage to the voltage corresponding to the desired gradation.

As shown in FIG. 1, when a rapid change occurs in a pixel, the change in the voltage applied to the OLED is very large and the change in the voltage difference across the OLED (or the voltage change width of the OLED anode) and / Or the voltage variation between the gate electrode and the drain electrode of the driving transistor becomes very large.

In order for the OLED to display the black gradation with sufficiently low luminance, it is necessary to initialize the anode electrode of the OLED with a sufficiently low initializing voltage to remove the charge remaining in the parasitic capacitor of the OLED. However, if the initialization voltage is lowered, the charge can not be quickly applied to the parasitic capacitor of the OLED, and the driving transistor can not quickly exceed the threshold voltage, and the voltage of the gate electrode and the drain electrode The rate of change may be slowed, and the OLED may not be properly emitted at the luminance corresponding to the gradation of the next frame as shown in FIG.

On the other hand, if the initialization voltage is increased, the voltage variation width of the OLED anode electrode is reduced in a rapid screen switching, and the OLED can emit light quickly at a luminance corresponding to the gray level at which the OLED is input in the next frame. However, even if the initialization voltage is applied to the OLED anode electrode, the charge can not be completely removed from the parasitic capacitor of the OLED, and even if the data voltage of the black gradation is applied and the current hardly flows in the driving transistor, So that it can not express low brightness.

When the initialization voltage is fixed as described above, there arises a problem that the black gradation can not be expressed properly or the response speed is slow depending on the potential of the set initialization voltage, so that a drag phenomenon occurs in a sudden change of the screen.

FIG. 3 is a table showing display quality indices such as optical compensation error, black luminance, response speed, and the like for various initialization voltages.

3, when the initialization voltage V _INI is fixed while the low-potential driving voltage V _SS is fixed, it can be seen that the lower the initialization voltage V _INI , the lower the black luminance of the black gradation.

Also, an optical compensation error (OC Error) does not occur only when the black luminance of the black gradation is sufficiently low. In the optical compensation error of FIG. 3, O indicates that an optical compensation error occurs, and X indicates that no optical compensation error occurs.

Further, even when the data voltage of black gradation is applied only when the initialization voltage V _INI is sufficiently low, a bright dot is not generated.

The higher the response speed (FFR), the higher the response speed is, and the higher the initialization voltage (V _INI ), the better the response speed.

As described above, the black luminance and the optical compensation error (OC Error) of the black gradation are good when the initialization voltage V _INI is low, while the frame response speed FFR is high when the initialization voltage V _INI is high Good, they have opposite results. Therefore, it is possible to solve both problems by judging the situation in which the luminance of the black gradation is required and the situation in which the response speed is important and the initialization voltage V _INI is adjusted appropriately.

According to the present invention, the input image data is analyzed and the potential of the initialization voltage for initializing the OLED is adjusted based on the analyzed image data, so that the black gradation can be expressed with sufficiently low luminance and the drawing phenomenon can be reduced even in the case of a sudden change of screen. That is, according to the present invention, when the input image data is analyzed, when the abrupt screen change occurs, the initialization voltage is increased to reduce the voltage change amount of the OLED anode electrode, and when the screen transition state is not sudden, the initialization voltage is lowered, So that it can be expressed.

As an image analysis method, an average picture level (APL) method can be used. By comparing the APL of the previous frame and the current frame, it is possible to confirm whether the brightness of the screen changes rapidly. The APL is calculated for each frame and the difference between the APLs between frames is calculated. If the APL difference is equal to or larger than the predetermined value, it is determined that the screen switching state is sudden, and the initialization voltage applied to the pixel before applying the data voltage of the frame, .

Another method of analyzing an image is to use a histogram method of displaying the number of pixels having corresponding gradations for each gradation. The interval between the gradation where the peak occurs in the previous frame and the gradation where the peak occurs in the current frame is predetermined It is possible to judge that the screen switching state is sudden when the value is equal to or larger than the gray level value. Alternatively, if a peak occurs in the black grayscale in the previous frame, the black grayscale peak disappears in the current frame, the height of the peak is reduced, the peak occurs in the white grayscale, or the peak height becomes large,

In addition, by adding a bitmap method, it is possible to more precisely judge a sudden change of screen state by examining a positional relationship (e.g., proximity or the like) of pixels where a peak occurs in the histogram.

4 is a block diagram of a display device to which the present invention is applied. A display device according to the present invention includes a display panel 10, a timing controller 11, a data driving circuit 12, a gate driving circuit 13, and a power generating unit 16.

In the display panel 10, a plurality of data lines 14 and a plurality of scan lines 15 cross each other, and pixels PXL are arranged in a matrix form for each crossing region to form a pixel array. The scan lines 15 include a plurality of gate lines GL for supplying a scan signal for applying a data voltage and a plurality of emission lines for supplying emission signals for controlling emission of the light emitting devices. EL).

In the pixel array, the pixel PXL is connected to either one of the data lines 14, any one of the gate lines GL, and the emission lines EL to form a pixel line. The pixel is electrically connected to the data line 14 in response to a scan pulse input through the gate line GL to receive a data voltage and emit light in response to an emission pulse input through the emission line EL The light emission of the device can be controlled. The pixels arranged in the same pixel line operate simultaneously according to the scan pulse and the emission pulse applied from the emission line EL such as the same gate line GL.

The pixel is supplied with the high potential driving voltage V _DD , the low potential driving voltage V _SS and the initializing voltage V _INI from the power source generating unit 16 and supplies the light emitting element, the driving transistor, the storage capacitor, A transistor may be provided. The light emitting device may be an inorganic electroluminescent device or an organic light emitting diode (OLED) device. Hereinafter, the OLED will be described as an example for convenience.

The transistors (or TFTs) constituting the pixels may be implemented as a p-type or n-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure or a hybrid type in which p-type and n-type are mixed. In the following embodiments, p-type transistors are exemplified, but the present invention is not limited thereto.

A transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. Within the transistor, the carriers begin to flow from the source. The drain is an electrode from which the carrier exits from the transistor. That is, the flow of carriers in the MOSFET flows from the source to the drain.

In the case of an n-type MOSFET (NMOS), since the carrier is an electron, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. In an n-type MOSFET, the direction of current flows from drain to source because electrons flow from source to drain. In the case of a p-type MOSFET (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type MOSFET, the current flows from the source to the drain because the holes flow from the source to the drain.

It should be noted that the source and drain of the MOSFET are not fixed. For example, the source and drain of the MOSFET may be varied depending on the applied voltage. In the following embodiments, the invention should not be limited due to the source and drain of the transistor.

The timing controller 11 supplies image data (RGB) transmitted from an external host system (not shown) to the data driving circuit 12. The timing controller 11 receives timing signals such as a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, a data enable signal DE and a dot clock CLK from the host system, 12 and the gate driving circuit 13. The control signals for controlling the operation timings of the gate driving circuit 12 and the gate driving circuit 13 are shown in FIG. The control signals include a gate timing control signal GCS for controlling the operation timing of the gate driving circuit 13 and a data timing control signal DCS for controlling the operation timing of the data driving circuit 12. [

The timing controller 11 can drive one frame to which the video data constituting one screen is applied to the pixels constituting the display panel 10 by dividing the frame into at least the initialization period, the sampling period and the emission period.

The timing controller 11 analyzes input image data to determine whether a sudden change of screen occurs. If it is determined that abrupt change of screen occurs, the timing controller 11 generates an initialization voltage control signal IVC and supplies the initialization voltage control signal IVC to the power generation unit 16 This will be described in detail below with reference to FIGS. 7 and 8. FIG.

The data driving circuit 12 converts the image data RGB into data voltages and outputs them to the data lines 14 under the control of the timing controller 11. [

The gate driving circuit 13 can generate a scan signal and an emission signal based on the gate control signal GDC under the control of the timing controller 11. [ The gate drive circuit 13 may be composed of a plurality of gate drive integrated circuits each including a shift register, a level shifter for converting an output signal of the shift register into a swing width suitable for driving a TFT of a pixel, have. Alternatively, the gate driving circuit 13 may be formed directly on the lower substrate of the display panel 10 using a GIP (gate drive IC in panel) method. In the case of the GIP method, the level shifter is mounted on a PCB (Printed Circuit Board), and the shift register can be formed on the lower substrate of the display panel 10. [

The gate driver circuit 13 may include a separate scan driver and an emission driver. The scan driver generates a scan signal in a row-sequential manner and supplies the scan signal to at least one gate line GL connected to each pixel line , The emission driver may generate an emission signal in a row sequential manner and supply the emission signal to at least one emission line EL connected to each pixel line. The emission signal applied to the pixel circuit can control the emission time of the pixel.

The power generation section 16 generates and supplies a voltage required for the operation of the data driving circuit 12 and the gate driving circuit 13 using an external power source and supplies a high potential driving voltage V _DD , The voltage V _SS and the initializing voltage V _INI are generated and applied to the display panel 10 so that the high potential driving voltage V _DD and the low potential driving voltage V _SS are generated and output as fixed values , The initializing voltage V _INI can be varied and output.

That is, when the initialization voltage control signal IVC is transferred from the timing controller 11 to, for example, logic high, the power generation unit 16 raises the initialization voltage V _INI from the reference initial voltage, (IVC) is transferred to the logic low, the initialization voltage (V _INI ) can be lowered again to the reference initial voltage. The power generator 16 may increase the initialization voltage V _INI by a predetermined level and decrease the initialization voltage V _INI back to the reference initial voltage after a predetermined time has elapsed.

Fig. 5 shows an equivalent circuit of a pixel to which the present invention is applied. The pixel circuit of Fig. 5 is composed of seven transistors and one capacitor. The present invention is not limited to the one applied to the pixel circuit of Fig. 5 but may be applied to any pixel circuit that initializes the electrode of the OLED and / or the gate electrode of the driving transistor before applying the data voltage to be displayed to the pixel to the pixel circuit can do.

The organic light emitting element OLED emits light by a driving current supplied from the driving transistor DT.

The driving transistor DT controls the driving current applied to the OLED according to its source-gate voltage V _SG . The gate electrode of the driving transistor DT is connected to the node A, the source electrode thereof is connected to the node D, and the drain electrode thereof is connected to the node B.

The first transistor T1 includes a source electrode connected to the data line DL, a drain electrode connected to the node A, and a gate electrode connected to the nth gate line GL (n). The first transistor T1 applies a data voltage VDATA supplied from the data line DL to the node A in response to the scan signal SCAN (n).

The second transistor T2 includes a source electrode connected to the high potential voltage line V _DD , a drain electrode connected to the node A, and a gate electrode connected to the emission line EL (n) And applies a high potential voltage (V _DD ) to node A in response to the emission signal EM (n).

The third transistor T3 includes a source electrode connected to the node B, a drain electrode connected to the node C, and a gate electrode connected to the n-th gate line GL (n). The third transistor T3 may be formed of a dual gate transistor so as to reduce the leakage current when the third transistor T3 is turned off.

The fourth transistor T4 includes a source electrode connected to the node C, a drain electrode connected to the node D, and a gate electrode connected to the nth emission line EL (n) n)) to form a current path between node C and node D.

The fifth transistor T5 includes a gate electrode connected to a drain electrode connected to the node B, a source electrode connected to an initialization voltage V _INI input terminal, and an (n-1) th gate line GL (n-1) (V _INI ) to the node B in response to the (n-1) -th scan signal SCAN (n-1). The fifth transistor T5 may also be formed of a dual gate transistor.

The sixth transistor T6 includes a source electrode connected to the initialization voltage V _INI input terminal, a drain electrode connected to the node D, and a gate electrode connected to the nth gate line GL (n) (V _INI ) to node D, i.e., one electrode of the OLED, e.g., the anode electrode, in response to the initialization signal SCAN (n).

The storage capacitor C _ST includes a first electrode coupled to node B and a second electrode coupled to a high potential voltage line (V _DD ). The storage capacitor C _ST can maintain the voltage level of the gate electrode of the driving transistor DT while the scan signal SCAN is inactive.

FIG. 6 shows the waveform of the driving signal applied to the pixel of FIG. 5 and the voltage change of the main node.

Referring to FIGS. 5 and 6, one frame period in the OLED display to which the present invention is applied can be divided into an initialization period T _I , a sampling period T _S , and an emission period T _E. The initialization period T _I is a period for initializing the voltage of the gate electrode of the driving transistor DT. The sampling period T _s is a period for initializing the voltage of the anode electrode of the organic light emitting diode OLED and sampling the threshold voltage of the driving transistor DT and storing it in the node B. The emission period T _E includes the sampled threshold voltage to program the source-gate voltage of the driving transistor DT, and the organic light emitting element OLED emits light with the driving current according to the programmed source- .

the initialization period T _I of the nth pixel line may overlap with the sampling period of the (n-1) th pixel line. That is, the sampling period T _S can be sufficiently secured, and the compensation of the threshold voltage can be more accurately performed.

During the initialization period T _I , the fifth transistor T5 applies the initialization voltage V _INI to the node B in response to the n-th scan signal SCAN (n). As a result, the gate electrode of the driving transistor DT is initialized to the initializing voltage V _INI . The reference initializing voltage V _INI can be selected within a voltage range sufficiently lower than the operating voltage of the organic light emitting diode OLED and can be set to a voltage equal to or lower than the low potential driving voltage V _SS . The data voltage (V _DATA ) of the previous frame is held in the node B in the initialization period (T _I ).

During the sampling period T _S , the sixth transistor T6 applies the initializing voltage V _INI to the node D in response to the nth scan signal SCAN (n). As a result, the node D which is the anode electrode of the organic light emitting diode OLED is initialized to the initializing voltage V _INI .

The first transistor T1 applies the data voltage V _DATA supplied from the data line DL to the node A in response to the nth scan signal SCAN (n). The third transistor T3 is turned on in response to the n-th scan signal SCAN (n), and the driving transistor DT is diode-connected (the gate electrode and the drain electrode are short- Operation).

During the sampling period T _S , a current Ids flows between the source and the drain of the driving transistor DT. Since the gate electrode and the drain electrode of the driving transistor DT are diode-connected, the voltage of the node B of the driving transistor DT gradually rises due to the current Ids flowing from the source electrode to the drain electrode. During the sampling period T _S , the voltage of the node B rises from the data voltage (V _DATA ) to the value (V _DATA - V _TH ) minus the threshold voltage (V _TH ) of the driving transistor (DT).

During the emission period T _E , the second transistor T2 applies the high potential voltage V _DD to the node A in response to the nth emission signal EM (n). The fourth transistor T4 forms a current path of the node C and the node D in response to the nth emission signal EM (n). As a result, the driving current I _OLED passing through the source electrode and the drain electrode of the driving transistor DT is applied to the organic light emitting diode OLED.

The relation for the driving current I _OLED flowing through the organic light emitting diode OLED during the emission period T _E is as shown in the following equation (2).

In Equation (2), k / 2 represents a proportional constant determined by the electron mobility, parasitic capacitance, channel capacity, and the like of the driving transistor DT.

The threshold voltage V _TH of the driving transistor DT is erased in the relation of the driving current I _OLED as shown in Equation 2. This is because the organic light emitting display according to the present invention has the threshold voltage V _TH The driving current I _OLED does not change even if it changes.

FIG. 7 shows the voltage of a main node when a data voltage of black to black to white gradation is applied to three consecutive frames. 7, it is assumed that the gradation data value is not 0 (G0) and the gradation data value with a very low luminance is, for example, 5 (G5) or less.

7, a black gradation data voltage V _{DATA_B} is applied to the node A in the sampling period T _S of the first frame (Frame # 1) and the second frame (Frame # 2) The data voltage (V _{DATA_W} ) of white gradation is applied to the node A in the sampling period (T _S )

when driving the organic light emitting diode (OLED) to the driving transistor (DT) of the p type, the driving current flowing through the organic light emitting device (OLED) as shown in Equation 2 (I _OLED) is the high-potential voltage (V _DD) and the data voltage (V _dATA) is proportional to the difference between the data voltage (V _{DATA_B)} corresponding to a black gradation is higher than the data voltage (V _{DATA_W)} corresponding to a white gray scale, the voltage of the node B to the emission period (T _E) is in The voltage of the organic light emitting diode OLED becomes higher than that of the white gray level when the organic light emitting diode OLED expresses the black gray level and the voltage of the nodes C and D becomes higher than when the organic light emitting diode OLED expresses the white gray level.

The anode electrode (node D) of the driving element OLED is _switched from the initializing voltage V _INI to the driving voltage V _{INI in the} emission period T _E so that the driving transistor DT hardly causes current to flow, The voltage gradually rises to a level (V _INI + V _{TH - O} ) at which the threshold voltage (V _{TH - O} ) of the organic light emitting diode (OLED) is barely exceeded to cause the driving element OLED to emit light at a low luminance.

In the emission period T _E , when the white gradation is expressed, the drive transistor DT makes a large current flow so that the anode electrode (node D) of the drive element OLED changes from the initialization voltage V _INI to the drive element It began to fall the light-emitting threshold voltage (V _{TH_O)} of OLED), and the driving device (OLED) due to the internal resistance, such as the voltage of the anode electrode (node D) of the more current flows much driving element (OLED) store further up the (V _INI + V _TH - _O + _留 ).

The voltage of the anode electrode (node D) exceeds the threshold voltage (V _{TH - O} ) more quickly than when the black gradation is expressed, because the current flows in the driving element (OLED) The time required for the voltage of the anode electrode (node D) to rise is longer.

That is, since much current must flow through the driving element OLED to the third frame (Frame # 3) representing the white gradation than the second frame (Frame # 2) representing the black gradation, The voltage at the drain electrode (node C) of the driving transistor DT or the anode electrode (node D) of the driving element OLED increases in the emission period T _E of the driving transistor DT.

In addition, when a black bias for turning off the driving transistor DT is formed between the source electrode and the gate electrode while expressing the black gradation, charge is trapped in the channel region of the driving transistor DT (Charge Trap). In this state, even if a data voltage corresponding to the white gradation is applied to the source electrode, the charge in the channel region does not drop quickly, and the voltages of the gate electrode and the drain electrode of the driving transistor DT are not quickly changed to a desired level, It takes time for the current to flow to the amount corresponding to the white gradation.

Figure 8 illustrates an embodiment of adjusting the initialization voltage in accordance with the present invention.

6 and 7, in the sampling period T _S , the node B rises by the data voltage V _DATA applied to the node A of the current frame at the initializing voltage V _INI , This changing width is larger when the data voltage of black gradation is applied to the pixel than when the data voltage of white gradation is applied. That is, the difference between the black gradation data voltage V _{DATA_B} and the initializing voltage V _INI is greater than the difference between the white gradation data voltage V _{DATA_W} and the initializing voltage V _INI (| V _{DATA_B} V _INI |> | V _{DATA_W} V _INI |).

The voltage variation width (V _{DATA_B} > V _INI -> V _{DATA_W} ) of the node B is narrowed and the response speed of the driving transistor DT and the OLED is increased by _{increasing the} initialization voltage V _INI in the i- So that the white gradation can be properly expressed after the black gradation.

On the other hand, when the gradation change is small, since the voltage fluctuation width of the node B is not originally large, there is no problem in the reaction speed even if the initialization voltage (V _INI ) is lowered in the ii) direction, The OLED is not turned on in the state where the data voltage of the black gradation is applied and the current is hardly supplied to the driving transistor DT so that the black luminance can be properly ensured.

As shown in Fig. 8, the initialization voltage can be varied to improve the reaction speed of the pixel or secure the brightness of the black gradation.

FIG. 9 is a block diagram for generating a control signal for controlling an initialization voltage through image analysis according to an exemplary embodiment of the present invention. FIG. FIG. 4 is a flowchart illustrating a process of adjusting the temperature of the liquid.

Since the initialization voltage is generated by the power generator 16 and supplied to the display panel 10, one initialization voltage is provided to all the pixel circuits. Though it is practically possible to control the initialization voltage for each pixel differently, this is not practical because the circuit configuration becomes too complicated and the aperture ratio lowers because a voltage regulating circuit must be provided for each pixel. That is, the initialization voltage can only be adjusted in frame units.

As shown in FIG. 8, when the brightness level of the pixel is rapidly changed, the initialization voltage can be relatively increased to improve the response speed. Otherwise, the initialization voltage can be relatively lowered to accurately express the black brightness. It is necessary to analyze whether the brightness level of the pixels constituting the frame changes rapidly, that is, whether a sudden change of screen occurs, and to generate a signal for controlling the power generation unit based on the analysis.

The APL method, the histogram method, and the bitmap method can be used alone or in combination with each other to determine whether a sudden change of screen occurs or not. Hereinafter, the APL method will be mainly described.

The timing controller 11 may include an APL calculation unit 110, an APL difference calculation unit 120, and a voltage control signal generation unit 130 as an image analysis module.

The APL calculation unit 110 calculates the average image level (APL value), which is the average of the gray values of the entire image, for each frame by analyzing the image signal RGB input in frame units (Calculate APL). The APL difference calculator 120 calculates a difference between calculated APL values in two neighboring frames (Calculate APL difference).

The voltage control signal generation unit 130 can check whether the brightness of the screen changes rapidly by comparing the APL difference value calculated by the APL difference calculation unit 120 with a predetermined value delta. If the APL difference value is large, It can be judged that the switching, particularly the luminance level, is rapidly changed. If the APL difference value is small, it can be judged that there is no rapid screen switching.

The voltage control signal generating unit 130 generates an initialization voltage control signal IVC for raising the initialization voltage to a logic high level or a logic low level if the APL difference value is greater than a predetermined value, (Or logic high) for generating the initialization voltage control signal IVC for lowering the initialization voltage when the APL difference value is smaller than a predetermined value, and supplies the generated initialization voltage control signal IVC to the power generation unit 16, .

The power supply control unit 16 includes an operational amplifier and resistors (not shown) and receives the initialization voltage control signal IVC to vary the initialization voltage. For example, the initialization voltage control signal IVC of logic high, is input raise the initialization voltage _{(V INI) (raise V INI} ), when initializing voltage control signal (IVC) of the logic low is input it is possible to lower the initialization voltage (V _INI), based on the initialization voltage (lower V _INI).

The voltage control signal generator 130 generates the initialization voltage control signal IVC at a logic high level when the APL difference value is greater than the predetermined value, The initialization voltage control signal IVC is maintained at a logic high which raises the initialization voltage so that the initialization voltage V _INI does not change too rapidly and the change of the voltage or current of the driving transistor and the OLED can be smooth.

On the other hand, even if between the two frame APL differential value is less than the predetermined value, there APL value can raise is greater than the predetermined value, the initialization voltage (V _INI), the initialization voltage (V _INI) When the gray level of the screen increases the screen is bright enough There is no problem even if it is relatively high and there is an advantage that the variation speed of the voltage of the driving transistor or the OLED terminal is reduced to increase the reaction speed.

The voltage control signal generator 130 generates the initialization voltage control signal IVC at a logic high level when the APL value is less than the predetermined value even if the APL difference value is smaller than the predetermined value so that the power supply control unit 16 outputs the initialization voltage V _INI ).

(N + 1) -th frame when the APL difference value between the n-th frame and the (n + 1) -th frame is large, for example, before the data voltage of the frame in which the brightness of the screen largely changes is applied to the pixels of the panel. the initialization voltage up to (T _I) need to be applied to the pixel circuit, the voltage control signal generator 130 according to this timing generates the initialization voltage control signal (IVC), and the power generation portion 16 initializes the voltage .

The level at which the power generation unit 16 raises the initialization voltage may vary depending on the configuration of the pixel circuit, and may be determined through experimentation.

The image analysis module can use only the APL as shown in FIG. 9, but the histogram method and the bitmap method can be added, and the initialization voltage can be more effectively changed considering the luminance distribution of the image and the maximum gradation value. In other words, the APL can not extract the partial characteristics of the image with a simple average, but it can extract the partial characteristics using the bitmap method, and the actual maximum value of the image can be obtained through the histogram method.

Alternatively, the image analysis module may calculate the position (gradation) and peak height (the number or frequency of pixels expressing the gradation corresponding to the peak) of the peak and the interval between the peaks by the histogram method, The initialization voltage can be changed only when the pixels having the peak gradation are adjacent to each other by checking whether the brightness is abruptly changed by using the bitmap method.

By doing so, it is possible to improve the response speed by improving the dragging phenomenon that may appear only in a part of the image, and also to improve the phenomenon that the partial dark gradation such as the black box is expressed brightly.

According to the present invention, the initialization voltage is suitably adjusted through the image analysis in the pixel circuit configuration for initializing the driving transistor and / or the organic light emitting element between the frames, so that the sufficiently low luminance can be secured for the low gradation data, Accordingly, it is possible to solve the problem of defective product due to the optical compensation error, and it is also possible to improve the response speed which occurs when only the black luminance is considered.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: display panel 11: timing controller
12: Data driving circuit 13: Gate driving circuit
14: Data line 15: Gate line
16: power generation unit 110: APL calculation unit
120: APL difference calculation unit 130: Voltage control signal generation unit

Claims (12)

A display panel having a plurality of pixels including a light emitting element, a capacitor for storing a data voltage corresponding to the image data, and a driving transistor for causing a driving current corresponding to the data voltage to flow in the light emitting element;
A timing controller for generating a control signal for controlling driving of the display panel and analyzing the image data and generating a voltage control signal based on the analyzed data; And
And a power generator for varying an initialization voltage for initializing the plurality of pixels based on the voltage control signal and supplying the initialization voltage to the display panel. The method according to claim 1,
Wherein the initializing voltage initializes at least one of a gate electrode of the driving transistor and an anode electrode of the light emitting element before a data voltage corresponding to the image data is applied to the pixel. 3. The method of claim 2,
Wherein the timing controller comprises: a sampling period during which the initialization voltage is applied to the gate electrode of the driving transistor; a sampling period during which the initialization voltage is applied to the anode electrode of the light emitting device, the threshold voltage of the driving transistor is sampled, And one frame is driven in an emissive period in which the driving current flows to the light emitting element and the light emitting element emits light. The method according to claim 1,
Wherein the timing controller compares the video data of the n-th frame with the video data of the (n + 1) -th frame to increase the voltage control signal to the level of the initialization voltage when the luminance change is greater than a predetermined value And generates a second logic value that causes the voltage control signal to lower the level of the initialization voltage when the luminance change is smaller than the predetermined value. 5. The method of claim 4,
Wherein the timing controller comprises: an APL calculation section for calculating an average image level (APL) for each frame; an APL difference calculation section for calculating an APL difference value between successive two frames; And a voltage control signal generator for generating a voltage control signal of a logic value and generating a voltage control signal of the second logic value when the APL difference value is smaller than the first value. 6. The method of claim 5,
The voltage control signal generator generates the voltage control signal of the first logic value when the APL difference value is smaller than the first value and the APL of the nth frame and the (n + 1) th frame is larger than the second value And the display device. 6. The method of claim 5,
Wherein the power generation unit generates the power supply voltage to the pixel when the APL difference value between the nth frame and the (n + 1) th frame is greater than the first value, before the image data of the (n + The level of the display device is increased. 8. The method of claim 7,
Wherein the voltage control signal generator generates the voltage control signal as the first logic value for a predetermined number of frame periods when the APL difference value between the nth frame and the (n + 1) th frame is greater than the first value And the display device. 5. The method of claim 4,
Wherein the timing controller generates a histogram of the n-th frame and a histogram of the (n + 1) -th frame, calculates a position of the peak, an interval between the power and the peak with respect to each histogram, And comparing the two histograms to analyze a change in the peak, and based on the comparison, determines whether the luminance change between the two frames is greater than the predetermined value. The method of claim 3,
Wherein the pixel comprises:
A first transistor for applying the data voltage to a source electrode of the driving transistor;
A second transistor for applying a high potential voltage output from the power generator to a source electrode of the driving transistor;
A third transistor for connecting a gate electrode and a drain electrode of the driving transistor;
A fourth transistor for connecting the drain electrode of the driving transistor and the anode electrode of the light emitting element;
A fifth transistor for applying the initializing voltage to a gate electrode of the driving transistor; And
And a sixth transistor for applying an initialization voltage to the anode electrode of the light emitting element. 11. The method of claim 10,
A data driving circuit for applying the data voltage to the pixel; And
A first scan signal for activating the fifth transistor in the initialization period, a second scan signal for activating the first, third and sixth transistors during the sampling period, and a second scan signal for activating the second and third transistors in the emission period. 6. The display device according to claim 1, further comprising a gate driving circuit for generating an emission signal for activating the transistor. Analyzing image data to be displayed on a display panel including a plurality of pixels including a light emitting element and a driving transistor for driving current to the light emitting element to obtain a difference value of an average image level (APL) of two consecutive frames;
Generating a voltage control signal with an initialization voltage that initializes at least one of a gate electrode of the driving transistor and an anode electrode of the light emitting device to a first logic value when the APL difference value is greater than a first value;
Generating the voltage control signal with a second logic value when the APL difference value is less than a first value; And
Generating the initialization voltage based on the voltage control signal and raising the initialization voltage when the initialization voltage is the first logic value and decreasing the initialization voltage when the initialization voltage is the second logic value A method of adjusting an initialization voltage on a display device.

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