KR20170125670A - Array substrate and display device having the same - Google Patents

Abstract

 The present invention relates to an array substrate and a display device including the same. The present invention can increase the charging rate of the pixel electrode by precharging the driving pixel electrode using the gate signal of the front gate line in the array substrate sequentially providing the gate signal. In addition, the present invention may include a precharge transistor for precharging the pixel electrode. Thus, the present invention increases the filling rate of the pixel electrode, thereby increasing the average luminance and color reproduction rate of the display device and improving the luminance unevenness.

Description

[0001] ARRAY SUBSTRATE AND DISPLAY DEVICE HAVING THE SAME [0002]

The present invention relates to an array substrate and a display device including the same.

2. Description of the Related Art [0002] With the development of information electronic devices for realizing high-resolution and high-quality images of portable devices such as mobile phones and notebook computers and HDTVs, flat panel displays Devices are increasingly in demand. As such flat panel display devices, a liquid crystal display (LCD), a plasma display panel (PDP), a field emission display (FED), and an organic light emitting diode (OLED) have been actively studied. However, And realization of a large area screen, a liquid crystal display (LCD) is in the spotlight at present.

The liquid crystal display device includes a display panel, a data driver for supplying a data voltage to the plurality of data lines of the display panel, a gate driver for supplying gate pulses to the plurality of gate lines of the display panel, And a timing controller for controlling the timing controller. The display panel intersects a plurality of gate lines and a plurality of data lines to define pixel regions. The pixel region includes a driving transistor controlled by the gate pulse of the gate line and a pixel electrode charged by the data voltage of the data line.

In a liquid crystal display device, a gate signal is applied to a driving transistor connected to a gate line, and a data voltage is applied to the pixel electrode through the data line while the driving transistor is turned on. The pixel electrode completes the charging of the data voltage when the driving transistor is turned off.

However, the driving frequency of the gate pulse increases as the liquid crystal display device becomes high resolution, high speed driving, and large size. In addition, as the liquid crystal display device has become high resolution, high speed driving, and large size, RC delay (RC delay) has increased due to load increase of the display panel. Thus, in the liquid crystal display device, the charging time for charging the data voltage at the pixel electrode is reduced. Further, in the liquid crystal display device, there is a problem such as an average luminance reduction, a luminance unevenness, and a color reproduction rate decrease as the data voltage charging rate decreases in the pixel electrode.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide an array substrate and a display device including the same that can improve the filling rate of a pixel electrode by a data voltage.

An object of the present invention is to provide an array substrate capable of increasing the average luminance and color reproduction ratio and improving the luminance unevenness and a display device including the array substrate.

Other features and advantages of the invention will be set forth in the description which follows, or may be obvious to those skilled in the art from the description and the claims.

A pixel electrode disposed in a pixel region defined by intersecting the gate line and the data line; and a gate electrode connected to the gate electrode of the pixel electrode, And a driving transistor for supplying a data voltage of the data line to the pixel electrode based on the gate signal of the gate line once. Therefore, the present invention can improve the filling rate of the pixel electrode by the data voltage. Further, the present invention increases the charging rate of the pixel electrode at one time, so that the average luminance and the color recall rate of the display device can be increased and the luminance unevenness can be improved.

In the array substrate according to another embodiment of the present invention, the pixel electrode can be provided with an array substrate which is pre-charged by the gate signal of the previous-stage gate line and then charged by the data voltage.

In an array substrate according to another embodiment of the present invention, an array substrate having a charge amount preliminarily charged by the gate signal of the previous gate line of the pixel electrode is greater than a charge amount charged by the data voltage of the pixel electrode .

In the array substrate according to another embodiment of the present invention, the pre-charged charge amount by the gate signal of the preceding gate line of the pixel electrode can be smaller than the charge amount charged by the data voltage of the pixel electrode .

In an array substrate according to another embodiment of the present invention, the pre-charge transistor may include an array substrate in which a gate electrode and a source electrode are electrically connected to a previous gate line, and a drain electrode is electrically connected to the pixel electrode .

In the array substrate according to another embodiment of the present invention, the gate electrode is electrically connected to the one-end gate line, the source electrode is electrically connected to one data line, and the drain electrode is electrically connected to the pixel electrode It is possible to provide an array substrate which is electrically connected.

As another solution to the above-mentioned problem, there is provided a liquid crystal display device including: an (n-1) th gate line, an n-th gate line, a gate electrode extended from an (n-1) th gate line, A pixel electrode arranged in a pixel region defined by intersecting the n-th gate line and the data line, and a gate electrode arranged in the gate electrode extending in the (n-1) -th gate line and electrically connected to the gate electrode extended in the A precharge transistor including a pre-charge source electrode electrically connected to the pixel electrode and a pre-charge source electrode connected to the data line, and a source electrode extending from the data line and electrically connected to the pixel electrode, And a drain electrode connected to the source electrode and the drain electrode. Therefore, the present invention can improve the filling rate of the pixel electrode by the data voltage. Further, the present invention increases the charging rate of the pixel electrode at one time, so that the average luminance and the color recall rate of the display device can be increased and the luminance unevenness can be improved.

In the array substrate according to another embodiment of the present invention, the pre-charge transistor may further include a first pre-charge electrode and a second pre-charge electrode, wherein the first pre- And the second preliminary charge electrode electrically connects the gate electrode extended in the (n-1) th gate line and the preliminary charge source electrode through the second and third contact holes, .

In the array substrate according to another embodiment of the present invention, the first and second pre-charged electrodes can provide an array substrate which is the same material as the pixel electrodes.

In the array substrate according to another embodiment of the present invention, the first and second pre-charged electrodes may be an array substrate of a transparent conductive material.

As another solution to the above-described problem, a display device including the above-described array substrate can be provided.

The array substrate according to the embodiment of the present invention can improve the filling rate of the pixel electrode by the data voltage.

In addition, since the array substrate according to the embodiment of the present invention increases the filling rate of the pixel electrode, it is possible to increase the average luminance and color reproduction ratio of the display device and improve the luminance unevenness.

In addition, other features and advantages of the present invention may be newly recognized through embodiments of the present invention.

1 is a block diagram of a display device according to an embodiment of the present invention.
2 is a circuit diagram illustrating a pixel region of an array substrate according to an embodiment of the present invention.
3 is a plan view illustrating an array substrate according to an embodiment of the present invention.
4 is a plan view illustrating a pre-charge transistor according to an embodiment of the present invention.
5 is a waveform diagram for explaining the charge rate of a pixel electrode of a display device according to the related art.
6 is a waveform diagram for explaining the pixel electrode filling rate of an array substrate according to an embodiment of the present invention.
7 is an example of an experiment for explaining the pixel electrode filling factor of an array substrate according to an embodiment of the present invention.
8 is another experimental example for explaining the pixel electrode filling rate of an array substrate according to an embodiment of the present invention.
9 is a waveform diagram for explaining the pixel electrode filling rate of an array substrate according to another embodiment of the present invention.

The following embodiments are provided by way of example so that those skilled in the art will be able to fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. Like reference numerals designate like elements throughout the specification.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be embodied in various forms. In addition, the present embodiments are provided so that the disclosure of the present invention is complete and that those skilled in the art will fully understand the scope of the present invention. Further, the present invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

The terms "under, below, beneath," "lower," "above," and "upper", which are spatially relative terms, Or may be used to easily describe the relationship of components to other components or components. Spatially relative terms should be understood to include, in addition to the orientation shown in the drawings, terms that include different orientations of the device during use or operation. For example, when inverting an element shown in the figures, an element described as "below" or "beneath" of another element may be placed "above" another element. Thus, the exemplary term "below" can include both downward and upward directions.

The terminology used herein is for the purpose of describing embodiments only and is not intended to be limiting of the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. &Quot; comprise "and / or" comprising ", as used in the specification, means that the presence of stated elements, Or additions.

1 is a block diagram of a display device according to an embodiment of the present invention.

1, the display panel 100 includes an array substrate 101 and a counter substrate (not shown) disposed corresponding to the array substrate 101, and liquid crystal molecules disposed between both substrates. In this display panel 100, m × k (where m and k are positive integers) pixels in a matrix form by the intersection structure of the data lines DL 1 to DL m and the gate lines GL 1 to GL k A region P is defined and liquid crystal cells are arranged in each of the pixel regions P. [

The pixel region P defined by the intersection of the plurality of gate lines and the plurality of data lines may include one or more sub-pixels. The pixel region P may include a first sub-pixel displaying a first color, a second sub-pixel displaying a second color, and a third sub-pixel displaying a third color. In addition, the pixel region P may further include a fourth sub-pixel that displays a fourth color. The first through third sub-pixels may display red, green, and blue colors, and the fourth sub-pixel may display a white color.

M data lines DL 1 to DL m, k gate lines GL 1 to GL k, a common line CL, a precharge transistor Tp, and a precharge transistor Tp are connected to the array substrate 101 of the display panel 100, The common electrode 120, the liquid crystal capacitor Clc, and the storage capacitor Cst of the liquid crystal cell connected to the driving transistor Tr, the pre-charging transistor Tp, and the driving transistor Tr, And the like can be formed. A black matrix may be formed on an opposing substrate (not shown) of the display panel 100. A polarizing plate may be attached to each of the counter substrate (not shown) of the display panel 100 and the array substrate 101, and an alignment layer may be formed on the inner surface of the counter substrate (not shown) and the array substrate 101 to set the pretilt angle of the liquid crystal. The display panel 100 may be an IPS (In-Plane Switching) mode in which the liquid crystal is aligned in the horizontal electric field direction according to the arrangement relationship of the pixel electrode 110 and the common electrode 120. The display panel 100 may be a TN (Twist Nematic) mode or a VA (Vertical Alignment) mode in which liquid crystals are aligned in a vertical electric field direction according to the arrangement relationship of the pixel electrode 110 and the common electrode 120 . In addition, the display panel 100 can be driven in a different mode according to the electric field direction for orienting the liquid crystal. The display panel 100 may have a structure in which the pixel electrode 110 and the common electrode 120 are connected to the array substrate 101 or the pixel electrode 110 in accordance with an IPS (In-Plane Switching) mode, a TN (Twist Nematic) mode, And may be disposed on an opposite substrate (not shown). The data driver 300 may comprise a plurality of data driver integrated circuits. The data driver 300 latches the digital video data mRGB under the control of the timing controller 200 and converts the digital video data into analog positive / negative gamma compensation voltages to generate positive / negative data voltages . Each of the plurality of data driver ICs may provide a data signal to each of a plurality of grouped data lines DL 1 to DL m. Therefore, the number of the data driver ICs may vary according to the degree of grouping of the data driver ICs according to the resolution of the display device. And the data driver 300 may supply a data voltage to the data lines DL 1 to DL m for each horizontal period during which the source output enable signal SOE is held in the low logic state. The data driver integrated circuits may be mounted on a TCP (Tape Carrier Package) and bonded to an array substrate 101 of a display panel 100 by a TAB (Tape Automated Bonding) process.

The gate driver 400 includes a level shifter for converting the output signal of the shift register and the shift register into a swing width suitable for driving the TFT of the liquid crystal cell and an output buffer connected between the level shifter and the gate lines GL 1 to GL k And the like. The gate driver 400 may sequentially supply gate signals having a pulse width of a predetermined horizontal period to the gate lines GL 1 to GL n under the control of the timing controller 200. The gate driver 400 is mounted on the TCP and bonded to the array substrate 101 of the display panel 100 by a TAB process or is connected to the array substrate 101 by a gate driver in panel (GIP) As shown in Fig.

The timing controller 200 converts digital video data (RGB) input from a system board (not shown) into mRGB video data, rearranges the mRGB video data according to the display panel 100, and supplies the rearranged data to the data driver 300. The timing controller 200 receives timing signals such as a vertical / horizontal synchronizing signal (Vsync, Hsync), a data enable signal and a clock signal (CLK) from the system board and supplies the timing signal to the data driver 300 and the gate driver 400 And generates control signals (GCS, DCS) for controlling the operation timings of the plurality of memory cells. When the display panel 100 includes a fourth sub-pixel for displaying white color, the digital video data RGB is converted into mRGBW video data, and the digital video data RGB is rearranged according to the display panel 100 and supplied to the data driver 300 .

The gate timing control signal GCS for controlling the gate driver 400 includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE ) And the like. The gate start pulse (GSP) is generated once at the same time as the start of the frame period for one frame period to generate the first gate pulse. The gate shift clock GSC shifts the gate start pulse GSP with a clock signal commonly inputted to a plurality of stages constituting the shift register. The gate output enable signal GOE controls the output of the gate driver 400.

The data timing control signal DCS for controlling the data driver 300 includes a source start pulse SSP, a source sampling clock SSC, a vertical polarity control signal POL, An output enable signal (SOE), and the like. The source start pulse SSP is a signal for controlling the data sampling start timing of the data driver 300. The source sampling clock SSC corresponds to the rising or falling edge of each of the data drivers 300, And is a clock signal for controlling the sampling timing. The vertical polarity control signal POL controls the vertical polarity inversion timing of the data voltage output from the data driver 300 for each of the gate lines GL1 to GLk and the source output enable signal SOE, The output timing of the data driver 300 is controlled. The data driving circuit 300 latches the input mRGB DATA under the control of the timing controller 200. And converts the vertical polarity control signal Pol to an analog positive or negative gamma compensation voltage GAMMA and outputs the same to the display panel 100 through all the data lines D1 to Dm. More specifically, the data driver 300 can set the polarity of the data voltage output from the data driver 300 to be positive when the vertical polarity control signal POL provided from the timing controller 200 is high logic, The polarity of the data voltage output from the data driver 300 can be negative. The polarity can be inverted in units of vertical lines by the vertical polarity control signal POL.

2 is a circuit diagram illustrating a pixel region of an array substrate according to an embodiment of the present invention.

Fig. 2 is a cross-sectional view of an array substrate 101 according to an embodiment of the present invention, which is defined by an n-th gate line GL n and a data line DL of the first to k- (N is an integer of 2 or more).

Referring to FIG. 2, the array substrate 101 according to the embodiment may include a common electrode 120 in an Nth pixel region P. The common electrode 120 may be disposed corresponding to the pixel electrode 110 and may be electrically connected to the common line CL.

The array substrate 101 according to the embodiment has the liquid crystal capacitor Clc and the common electrode 120 and the driving transistor Tr formed by the common electrode 120 and the pixel electrode 110 in the Nth pixel region P A storage capacitor Cst and other parasitic capacitors.

The array substrate 101 according to the embodiment may include a driving transistor Tr in an Nth pixel region P. The driving transistor Tr may provide a gate signal of the n-th gate line GL n to the N-th pixel electrode 110. In the driving transistor Tr, the gate electrode of the n-th gate driving transistor Tr is electrically connected to the nth gate line GL n, the source electrode thereof is connected to the data line DL, (Not shown).

The array substrate 101 according to the embodiment may include a precharge transistor Tp in the Nth pixel region P. [ The precharge transistor Tp may provide the gate signal of the (n-1) th gate line GL n-1 provided for the (N-1) th pixel electrode 110 to the N th pixel electrode 110. In the precharge transistor Tp, the gate electrode and the source electrode may be electrically connected to the (n-1) th gate line GL n-1, and the drain electrode may be connected to the pixel electrode 110. The pre-charge transistor Tp may be electrically connected to the gate electrode and the source electrode in a diode connection manner. The precharge transistor Tp may apply a gate signal to the (n-1) th gate line GL n-1 and simultaneously provide a gate signal to the N th pixel electrode 110.

The array substrate 101 according to the embodiment may include the pixel electrode 110 in the Nth pixel region P. [ The pixel electrode 110 can be charged by receiving a gate signal by the driving transistor Tr and the pre-charge transistor Tp. In addition, the pixel electrode 110 may be precharged by receiving the gate signal of the previous gate line before applying the gate signal for driving to display an image.

More specifically, a gate signal may be applied to the (n-1) th gate line GL n-1 in the Nth pixel region P to preliminarily charge the pixel electrode 110. The preliminary charge amount of the Nth pixel electrode 110 may be greater than the maximum charge amount due to the data voltage since a gate signal larger than the data voltage is applied. The pre-charge amount of the N-th pixel electrode 110 may be smaller than the final charge amount due to the data voltage. That is, the pre-charge amount of the N-th pixel electrode 110 can be changed according to the driving frequency of the gate signal, the RC delay caused by the load, and the like. The gate electrode GL of the Nth pixel region P is applied with a gate signal to turn on the driving transistor Tr while the data voltage of the data line DL is applied to the pixel electrode P, It is possible to complete the charging of the display unit 110 and display the image. That is, since the pixel electrode 110 is preliminarily charged before the image is displayed, the charging rate by the data voltage increases.

Therefore, the array substrate according to the embodiment of the present invention can improve the filling rate of the pixel electrode by the data voltage. In addition, since the array substrate according to the embodiment of the present invention increases the filling rate of the pixel electrode, it is possible to increase the average luminance and color reproduction ratio of the display device and improve the luminance unevenness.

FIG. 3 is a plan view illustrating an array substrate 101 according to an embodiment of the present invention, and FIG. 4 is a plan view illustrating a pre-charge transistor Tp according to an embodiment of the present invention.

Referring to FIG. 3, the embodiment of the present invention shown in FIG. 3 is an example in which the liquid crystal panel 100 is driven in the IPS mode.

The array substrate 101 may be a transparent insulating substrate. A data line DL extending along a first direction on the array substrate 101 and a data line DL extending along a second direction on the array substrate 101 and intersecting the data line DL, And nth gate lines GL n-1 and GL n. The area where the n-1th gate line GL n-1 and the data line DL intersect can be defined as the (N-1) th pixel area N-1, The region where the line DL intersects can be defined as the Nth pixel region N. [ The array substrate 101 may include a common line CL extending along the second direction and a common electrode 120 having a large area electrically connected to the common line CL. The common electrode 120 may correspond to the pixel electrode 110, which is a pattern electrode. The array substrate 101 may include a driving transistor Tr in the Nth pixel region N. [ The driving transistor Tr is electrically connected to the gate electrode GE and the active layer ACT extending from the nth gate line GL n and the source electrode SE and the pixel electrode 110 extending from the data line DL, And a drain electrode DE connected to the source electrode.

Referring to FIGS. 3 and 4, the array substrate 101 may include a pre-charge transistor Tp in the (N-1) th pixel region N-1. The pre-charge transistor Tp may be formed on the gate electrode GE extending from the n-1th gate line GL n-1. The pre-charge transistor (Tp) may comprise a pre-charge active layer (117). The pre-charge active layer 117 may be disposed on the gate electrode GE extending from the (n-1) th gate line GL n-1. The pre-charge transistor Tp may comprise a pre-charge source electrode 116. The pre-charge source electrode 116 may be disposed on the gate electrode GE extending from the n-1 gate line GL n-1. The pre-charge transistor Tp may comprise a first pre-charge electrode 112. The first pre-charging electrode 112 may be disposed on the gate electrode GE extending from the n-1 gate line GL n-1 and the pre-charge drain electrode 113. The second preliminary charge electrode 115 includes a first contact hole 114 for electrically connecting the gate electrode GE extending from the n-1 gate line GL n-1 and the pre-charge drain electrode 113, . ≪ / RTI > The second pre-charging electrode 115 may extend from the pixel electrode 110 of the Nth pixel region N. [ That is, the second pre-charging electrode 115 may extend from the pixel electrode connection portion 111 extending from the pixel electrode 110 of the Nth pixel region N. The pre-charge transistor Tp may comprise a second pre-charge electrode 115. The second pre-charge electrode 115 may be disposed on the gate electrode GE extending from the n-1 gate line GL n-1 and the pre-charge source electrode 116. The second preliminary charge electrode 115 is electrically connected to the third contact hole 118 or the preliminary charge source electrode 116 for electrically connecting to the gate electrode GE extending from the n-1 gate line GL n- And a second contact hole 118 for electrically connecting with the first contact hole. That is, FIG. 4 shows a state in which the preliminary charge source electrode 116 and the gate electrode GE extending from the (n-1) th gate line GL n-1 are electrically connected in a diode connection manner. The first pre-charging electrode 112 and the second pre-charging electrode 115 may be made of the same material as the pixel electrode 110. In addition, the first pre-charging electrode 112 and the second pre-charging electrode 115 may be made of ITO, IZO or ITZO which is a transparent conductive material.

Therefore, in the array substrate 101 according to the embodiment of the present invention, when a gate signal is applied to the (n-1) th gate line GL n-1 in the (N-1) th pixel region N-1, The pixel electrode 110 of the Nth pixel region N can be preliminarily charged.

FIG. 5 is a waveform diagram for explaining the pixel electrode filling rate of the display device according to the related art, and FIG. 6 is a waveform diagram illustrating the pixel electrode filling rate of the array substrate according to an embodiment of the present invention.

5, a data voltage Data and a gate signal Vgh input to the pixel electrode Nth PXL in the Nth pixel region in the conventional display device not precharging the pixel electrode are The data voltage is shown to be charged in synchronization. The conventional display device of FIG. 5 provides a gate signal (Vgh) of a gate high voltage having a pulse width of a horizontal period of 3H to the n-th gate line (GL n) in order to improve the charging rate. However, in the conventional display device of FIG. 5, the gate signal (Vgh) is changed from the gate high voltage to the gate low voltage so as to be applied to the pixel electrode (Nth PXL) in the Nth pixel region It can be confirmed that the charging rate is not good. That is, the conventional display device of FIG. 5 can not sufficiently charge the data voltage provided by the data driver in the pixel electrode, so that the luminance unevenness, the color recall ratio, and the like can be reduced.

Referring to FIG. 6, FIG. 6 illustrates a relationship between a data voltage Data input to the pixel electrode 110 (Nth PXL) of the Nth pixel region N in the display device according to the embodiment of FIG. 3, and the gate signals Vgh (GL n-1) and Vgh (GL n) provided to the nth gate line are synchronized to charge the data voltage. The display device according to the embodiment of FIG. 6 provides gate signals having a horizontal period of 1H with a lower pulse width than the prior art of FIG. The display device according to the embodiment of FIG. 6 applies the data voltage (Vg (GL n-1)) to the Nth pixel electrode 110 at the precharge point B by the gate signal Vgh Is charged to a charging amount larger than the maximum charging amount by The display device according to the embodiment of FIG. 6 sequentially applies the data voltage to the Nth pixel electrode 110 at the charge end point C by the gate signal Vgh (GL n) provided to the nth gate line You can see the charged state. The display device according to the embodiment of FIG. 6 exhibits a charge rate even when driven by a gate signal having a pulse width of a horizontal period lower than that of the conventional display device of FIG. That is, even if the gate signal operates at a high driving frequency, the display device according to the embodiment of FIG. 6 can charge a sufficient pixel electrode.

One reason why the pixel electrode filling rate of the display device according to an embodiment of the present invention is better than the pixel electrode filling rate of the display device according to the related art is related to the driving transistor Tr characteristics of the present invention. That is, the driving transistor Tr of the pixel electrode may be turned on to charge the data voltage supplied from the data line. At this time, the driving current I flowing from the source electrode to the drain electrode of the driving transistor Tr is proportional to the square of the voltage difference Vgs between the gate electrode and the source electrode of the driving transistor Tr (I? Vgs? 2) . The voltage difference (Vgs) between the gate electrode and the source electrode of the driving transistor Tr is reduced, and the driving current I is reduced to Decrease gradually. Therefore, in the display device according to the related art, since the charging speed is reduced as the pixel electrode is being charged, a sufficient charging time can not be secured at a high driving frequency. However, in the display device according to an embodiment of the present invention, a low voltage data voltage is input in a state where the pixel electrode is charged with a high voltage in advance, and the charge voltage of the pixel electrode is discharged to the input data voltage level. Therefore, in the display device according to the embodiment of the present invention, since the source electrode of the driving transistor is reduced, the voltage difference (Vgs) between the gate electrode and the source electrode of the driving transistor Tr increases, and the driving current I gradually increases do. Therefore, in the display device according to the present invention, since the charging speed increases as the charging end point of the pixel electrode approaches, a sufficient charging time can be secured even at a high driving frequency.

7 and 8 are experimental examples for explaining the pixel electrode filling rate of the array substrate according to an embodiment of the present invention.

Referring to FIG. 7, FIG. 7 illustrates a case where the data voltage Data is provided with a positive polarity in the data driver 300 of the display device as shown in FIG. The display device according to the embodiment of FIG. 7 sequentially applies the gate signal Vgh ((GL n-1)) supplied to the n-th gate line after precharging by the gate signal Vgh GL n) of the Nth pixel electrode 110 (Nth PXL) is sufficiently charged.

Referring to FIG. 8, FIG. 8 shows a case where the data voltage Data is provided in a negative polarity in the data driver 300 of the display device, unlike in FIG. The display device according to the embodiment of FIG. 8 sequentially applies the gate signal Vgh (GL n-1) supplied to the n-th gate line after the pre-charge by the gate signal Vgh (GL n-1) The data voltage is sufficiently charged at the negative data voltage level to the Nth pixel electrode 110 (Nth PXL) by the pixel electrode GL n. That is, even if the pixel electrode is precharged by the gate signal (Vgh), which is a high gate high voltage, the display device according to the embodiment of FIG. Can reach. This is because, as described above, even if the charging time is reduced due to the display device operating at a high driving frequency, the charging of the pixel electrode of the display device can be performed at high speed from a high level to a low level. Therefore, the display device according to the embodiment of the present invention can realize a sufficient charge rate of the pixel electrode even when operated in the inversion mode.

9 is a waveform diagram for explaining the pixel electrode filling rate of an array substrate according to another embodiment of the present invention.

9, in contrast to the display device according to an embodiment of the present invention shown in FIGS. 3 and 6, the Nth pixel electrode 110 at the pre-charging point D is the data of the charging end point E And can be charged to a charging amount smaller than the maximum charging amount by the voltage Data. 9, when the driving frequency of the gate signal Vgh provided by the gate driver 400 is significantly high, the Nth pixel electrode 110, Nth PXL Is charged at a charge amount smaller than the maximum charge amount by the data voltage Data. The display device according to another embodiment of FIG. 9 sequentially supplies the data to the Nth pixel electrode 110 at the charge end point E by the gate signal Vgh (GL n) provided to the nth gate line, You can see the voltage is fully charged. In other words, the display device according to another embodiment of FIG. 9 is charged to a predetermined level in advance when charging by the gate signal Vgh (GL n) provided to the n-th gate line to the N-th pixel electrode 110 starts The data voltage can be sufficiently charged even during the short charge period of the Nth pixel electrode 110. [ Accordingly, the display device according to the another embodiment of FIG. 9 can realize a sufficient charge of the pixel electrode even when the gate signal operates at a high driving frequency.

Therefore, the array substrate according to the embodiment of the present invention can improve the filling rate of the pixel electrode by the data voltage.

In addition, since the array substrate according to the embodiment of the present invention increases the filling rate of the pixel electrode, it is possible to increase the average luminance and color reproduction ratio of the display device and improve the luminance unevenness.

It will be understood by those skilled in the art that the present invention can be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

100 display panel
101 array substrate
110 pixel electrode
111 pixel electrode connection portion
112 first pre-charging electrode
113 pre-charge drain electrode
114 first contact hole
115 second pre-charging electrode
116 pre-charge source electrode
117 pre-charged active layer
118 second contact hole
119 third contact hole
120 common electrode
130 first insulating layer
140 second insulation layer
200 timing controller
300 data driver
400 gate driver

Claims (11)

Front gate line;
Gate line once;
A data line;
A pixel electrode arranged in a pixel region defined by intersecting the gate line and the data line;
A precharge transistor for providing a gate signal of the previous gate line to the pixel electrode; And
And a driving transistor for supplying a data voltage of the data line to the pixel electrode based on the gate signal of the one-time gate line. The method according to claim 1,
Wherein the pixel electrode is precharged by the gate signal of the previous gate line and then charged by the data voltage. 3. The method of claim 2,
Wherein a charge amount preliminarily charged by a gate signal of the previous gate line of the pixel electrode is greater than a charge amount charged by a data voltage of the pixel electrode. 3. The method of claim 2,
Wherein a charge amount preliminarily charged by a gate signal of the previous gate line of the pixel electrode is smaller than a charge amount charged by a data voltage of the pixel electrode. The method according to claim 1,
Wherein the precharge transistor has a gate electrode and a source electrode electrically connected to the front gate line, and a drain electrode electrically connected to the pixel electrode. The method according to claim 1,
Wherein the driving transistor has a gate electrode electrically connected to the one-end gate line, a source electrode electrically connected to the data line, and a drain electrode electrically connected to the pixel electrode. A (n-1) th gate line;
An n-th gate line;
A gate electrode extending from the (n-1) th gate line;
A gate electrode extending from the nth gate line;
A data line;
A pixel electrode arranged in a pixel region defined by intersecting the nth gate line and the data line;
And a pre-charge source electrode electrically connected to the gate electrode extended from the n-1 < th > gate line and a pre-charge drain electrode electrically connected to the pixel electrode, A pre-charge transistor; And
And a driving transistor disposed on the gate electrode extended from the nth gate line, the driving transistor including a source electrode extended from the data line and a drain electrode electrically connected to the pixel electrode. 8. The method of claim 7,
Wherein the pre-charge transistor further comprises a first pre-charge electrode and a second pre-charge electrode,
The first pre-charging electrode electrically connects the pre-charge drain electrode and the pixel electrode through a first contact hole,
And the second preliminary charge electrode electrically connects the gate electrode extended from the n-1th gate line and the preliminary charge source electrode through the second and third contact holes. 9. The method of claim 8,
Wherein the first and second pre-charged electrodes are made of the same material as the pixel electrode. 9. The method of claim 8,
Wherein the first and second pre-charging electrodes are transparent conductive materials. A display device comprising an array substrate according to any one of claims 1 to 10.

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