KR20160113001A - Ldpc decoder, semiconductor memory system and operating method thereof - Google Patents

Abstract

Disclosed is an operating method of an LDPC decoder, comprising: a first step of initially updating code word to a variable node; a second step of performing decoding based on an original parity check matrix; a third step of changing columns of the original parity check matrix corresponding to a partial check node selected among check nodes of a 2t^th level from a tree structure having an unsatisfied syndrome check (USC) node corresponding to USC as the most significant node, to dummy data if the number of the USC is not reduced while being performed for a threshold number of the decoding, so as to generate a corrected parity check matrix; a fourth step of performing node update consisting of check node update and variable node update based on the corrected parity check matrix; and a fifth step of configuring the second to the fourth step as one repetition cycle, and repeating the repetition cycle for a predetermined number until the decoding succeeds. According to one embodiment of the present invention, it is possible to accurately read data stored in a memory cell of a semiconductor memory device.

Description

TECHNICAL FIELD [0001] The present invention relates to an LDPC decoder, a semiconductor memory system, and a method of operating the same.

The present invention relates to an LDPC decoder, a semiconductor memory system and a method of operation thereof.

The semiconductor memory device includes a volatile memory device such as a dynamic random access memory (DRAM), a static random access memory (SRAM), and the like, a read only memory (ROM), a magnetic random access memory (MROM), a programmable ROM (PROM), an erasable ROM (EPROM) Volatile memory devices such as electrically erasable ROM, FRAM, PRAM, MRAM, RRAM, and flash memory.

Volatile memory devices lose stored data when power is turned off, but nonvolatile memories can preserve stored data even when the power is turned off. In particular, flash memory has been widely used as a storage medium in computer systems and the like because it has advantages of high programming speed, low power consumption, and large data storage.

Non-volatile memories, for example flash memories, can determine data states storable in each memory cell according to the number of bits stored in each memory cell. A memory cell storing one bit of data in one memory cell is a single-bit cell or a single-level cell (SLC). A memory cell that stores 2-bit data in one memory cell is a multi-bit cell, a multi-level cell (MLC), or a multi-state cell. A memory cell that stores 3-bit data in one memory cell is a triple-level cell (TLC). MLC and TLC have advantages advantageous for high integration of memory. However, as the number of bits programmed into one memory cell increases, the reliability decreases and the read failure rate increases.

For example, to program k bits in one memory cell, any one of 2 ** k threshold voltages is formed in the memory cell. Due to the difference in electrical characteristics between the memory cells, the threshold voltages of the memory cells in which the same data are programmed form a certain range of threshold voltage distributions. Each threshold voltage distribution corresponds to each of the 2 ** k data values that can be generated by k bits.

However, since the voltage window over which the threshold voltage distributions can be placed is limited, as k increases, the distance between adjacent threshold voltage distributions decreases and adjacent threshold voltage distributions can overlap each other. As adjacent threshold voltage distributions are superimposed, the read data may contain many error bits (e.g., several error bits or dozens of error bits).

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a threshold voltage dispersion graph showing the programmed and erased states of a 3 bit triple level cell (TLC) nonvolatile memory device.

2 is a threshold voltage scatter graph showing program states and erase states that may be modified due to characteristic degradation of a 3-bit triple level cell non-volatile memory device.

Programming three bits (i.e., k = 3) in a single memory cell of a TLC nonvolatile memory device, for example TLC flash memory, will cause 2 ** 3, i.e., one of the eight threshold voltage distributions, Lt; / RTI >

Due to the difference in electrical characteristics between the plurality of memory cells, each of the threshold voltages of each of the memory cells with the same data programmed forms a certain range of threshold voltage distributions. In the case of a 3-bit TLC, a threshold voltage distribution (E) of a threshold voltage distribution of seven program states (P1 to P7) and one erase state is formed as shown in the figure. FIG. 1 is an ideal scatter diagram, in which no state scatter is overlapped, and a lead voltage margin is within a certain range for each scatter of each threshold voltage.

As shown in FIG. 2, in the case of a flash memory, over time, a charge loss occurs in which electrons trapped in a floating gate or a tunnel oxide are emitted. . Further, the tunnel oxide is deteriorated while the program and erase are repeated, and the charge loss can be further increased. The charge loss can reduce the threshold voltage. For example, the dispersion of the threshold voltage can be shifted to the left.

Also, program disturbances, erasure disturbances, and / or back pattern dependency phenomena can increase the dispersion of the threshold voltage with each other. Therefore, due to the characteristic deterioration of the memory cell due to the above-described reason, the threshold voltage distributions of adjacent states E and P1 to P7 as shown in FIG. 1B can overlap each other.

If the threshold voltage spreads overlap, the data being read may contain many errors. For example, when the third read voltage Vread3 is applied, if the memory cell is on, it is determined that the memory cell is in the second program state P2 and the memory cell is off ), It is determined that the memory cell concerned has the third program state (P3). On the other hand, if the third read voltage Vread3 is applied in a period in which the second program state P2 and the third program state P3 overlap, the memory cell is turned on, State. Thus, as the threshold voltage spreads overlap, many bits of error may be included in the read data.

Therefore, there is a need for a technique capable of accurately reading data stored in a memory cell of a semiconductor memory device.

An embodiment of the present invention aims at providing an LDPC decoder, a semiconductor memory system and an operation method thereof that can accurately read data stored in a memory cell.

According to an embodiment of the present invention, there is provided a method of operating a low density parity check (LDPC) decoder, comprising: a first step of initially updating a codeword to a variable node; A second step of performing decoding based on the original parity check matrix; If the number of USC (Unsatisfied Syndrome Check) does not decrease during the threshold number of times of decoding, a USC node corresponding to the USC corresponds to a check node selected from among the check nodes at the 2t- A third step of generating a modified parity check matrix by replacing the rows of the original parity check matrix with dummy data; A fourth step of performing node update consisting of check node update and variable node update based on the modified parity check matrix; And a fifth step of repeating the one to one repetition a predetermined number of times until the decoding is succeeded by repeating the second to fourth steps by one iteration.

Preferably, a predetermined number of check nodes among the 2 < th > level check nodes connected to edges of the (2t-1) -th level variable nodes are randomly selected in the tree structure to generate a modified parity check matrix .

Preferably, one or more check nodes are randomly selected according to a predetermined probability among the 2 < th > -level check nodes connected to the (2t-1) -th level variable nodes in the tree structure to generate a modified parity check matrix can do.

Advantageously, the codeword may be hard-case data.

Advantageously, said codeword may be soft-devised data.

Preferably, if the USC does not exist in the vector generated by the syndrome check, it can be determined that the main decoding is successful.

According to an embodiment of the present invention, there is provided a low density parity check (LDPC) decoder, comprising: first means for initially updating a codeword to a variable node and performing decoding based on the original parity check matrix; Level check nodes in a tree structure having a USC node corresponding to the USC as a top node, if the number of USC (Unsatisfied Syndrome Check) does not decrease during the threshold number of times of decoding, And a second means for generating a modified parity check matrix by replacing the rows of the original parity check matrix with dummy data, wherein the first means comprises: a decoding means for performing a check node update based on the decoding and the modified parity check matrix, The LDPC decoder may repeat the one repetition a predetermined number of times until the main decoding is successful by repeating the node update to be performed once.

Preferably, a predetermined number of check nodes among the 2 < th > level check nodes connected to edges of the (2t-1) -th level variable nodes are randomly selected in the tree structure to generate a modified parity check matrix .

Preferably, one or more check nodes are randomly selected according to a predetermined probability among the 2 < th > -level check nodes connected to the (2t-1) -th level variable nodes in the tree structure to generate a modified parity check matrix can do.

Advantageously, the codeword may be hard-case data.

Advantageously, said codeword may be soft-devised data.

Preferably, if the USC does not exist in the vector generated by the syndrome check, it can be determined that the main decoding is successful.

According to an embodiment of the present invention, there is provided a semiconductor memory system comprising: a semiconductor memory device; And an LDPC decoder, the LDPC decoder comprising: first means for initially updating a codeword to a variable node, and performing decoding based on the original parity check matrix; Level check nodes in a tree structure having a USC node corresponding to the USC as a top node, if the number of USC (Unsatisfied Syndrome Check) does not decrease during the threshold number of times of decoding, And a second means for generating a modified parity check matrix by replacing the rows of the original parity check matrix with dummy data, wherein the first means comprises: a decoding means for performing a check node update based on the decoding and the modified parity check matrix, And repeating the one iteration a predetermined number of times until the main decoding is successful.

Preferably, a predetermined number of check nodes among the 2 < th > level check nodes connected to edges of the (2t-1) -th level variable nodes are randomly selected in the tree structure to generate a modified parity check matrix .

Preferably, one or more check nodes are randomly selected according to a predetermined probability among the 2 < th > -level check nodes connected to the (2t-1) -th level variable nodes in the tree structure to generate a modified parity check matrix can do.

Advantageously, the codeword may be hard-case data.

Advantageously, said codeword may be soft-devised data.

Preferably, if the USC does not exist in the vector generated by the syndrome check, it can be determined that the main decoding is successful.

According to an embodiment of the present invention, data stored in a memory cell of a semiconductor memory device can be accurately read.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a threshold voltage scatter graph showing the programmed and erased states of a 3 bit multi-level cell (MLC) non-volatile memory device, respectively.
2 is a threshold voltage scatter graph showing program states and erase states that may be modified due to characteristic degradation of a 3-bit multi-level cell nonvolatile memory device.
3 is a block diagram illustrating a semiconductor memory system in accordance with an embodiment of the present invention.
4A is a detailed block diagram showing the semiconductor memory system shown in FIG.
4B is a block diagram illustrating the memory block shown in FIG. 4A.
5 is a flowchart showing the operation of the memory controller shown in FIG. 4A.
6A is a conceptual diagram showing an LDPC decoding represented by a tenant graph.
6B is a conceptual diagram showing an LDPC code structure.
6C is a conceptual diagram illustrating a syndrome check process according to LDPC decoding.
FIG. 7A is a conceptual diagram showing a 2-bit soft-decision read operation as the soft-write read operation shown in FIG.
FIG. 7B is a conceptual diagram showing a 3-bit soft-decision read operation as the soft-write read operation shown in FIG.
8A is a detailed block diagram illustrating an LDPC decoder according to an embodiment of the present invention.
8B is a diagram showing two-level tree structures having each of the USC nodes as a top node.
8C is a conceptual diagram illustrating an operation for selecting check nodes according to an embodiment of the present invention.
8D is a conceptual diagram illustrating the operation of selecting check nodes in accordance with an embodiment of the present invention.
8E is a graph showing a result of an operation simulation of an LDPC decoder according to an embodiment of the present invention.
9 is a block diagram illustrating an electronic device including a semiconductor memory system in accordance with an embodiment of the present invention.
10 is a block diagram illustrating an electronic device including a semiconductor memory system according to another embodiment of the present invention.
11 is a block diagram illustrating an electronic device including a semiconductor memory system according to another embodiment of the present invention.
12 is a block diagram illustrating an electronic device including a semiconductor memory system according to another embodiment of the present invention.
13 is a block diagram illustrating an electronic device including a semiconductor memory system according to another embodiment of the present invention.
14 is a block diagram illustrating a data processing system including the electronic device shown in Fig.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory only and are not restrictive of the invention, .

3 is a block diagram illustrating a semiconductor memory system 10 in accordance with one embodiment of the present invention.

FIG. 4A is a detailed block diagram showing the semiconductor memory system 10 shown in FIG. 3, and FIG. 4B is a block diagram showing the memory block 211 shown in FIG. 4A.

5 is a flowchart showing the operation of the memory controller 100 included in the semiconductor memory system 10. As shown in FIG.

3 to 5, the semiconductor memory system 10 may include a semiconductor memory device 200 and the memory controller 100.

The semiconductor memory device 200 may perform erase, write, and read operations under the control of the memory controller 100. The semiconductor memory device 200 can receive the command CMD, the address ADDR, and the data DATA from the memory controller 100 through the input / output line. The semiconductor memory device 200 may also receive the power supply PWR from the memory controller 100 via the power supply line and receive the control signal CTRL from the memory controller 100 via the control line. The control signal CTRL may include a command latch enable CLE, an address latch enable ALE, a chip enable nCE, a write enable nWE, a read enable nRE, and the like.

The memory controller 100 can control operation of the semiconductor memory device 200 as a whole. The memory controller 200 may include an LDPC unit 130 for correcting error bits. The LDPC unit 130 may include an LDPC encoder 131 and an LDPC decoder 133.

The LDPC encoder 131 performs error correction encoding on the data to be programmed in the semiconductor memory device 1200 to form data to which a parity bit is added. The parity bit may be stored in semiconductor memory device 200.

The LDPC decoder 133 can perform error correction decoding on the data read from the semiconductor memory device 200. [ The LDPC decoder 133 determines whether or not the error correction decoding is successful and outputs an instruction signal according to the determination result. The LDPC decoder 133 can correct error bits of data using parity bits generated in the LDPC encoding process.

On the other hand, if the number of error bits exceeds the correctable error bit threshold value, the LDPC unit 130 can not correct the error bit. At this time, an error correction fail signal may be generated.

The LDPC unit 130 can perform error correction using a LDPC (Low Density Parity Check) code. The LDPC unit 130 may include all circuits, systems, or devices for error correction. Here, the LDPC code includes a binary LDPC code and a non-binary LDPC code.

According to an embodiment of the present invention, the LDPC unit 130 may perform error bit correction using hard-decoded data and soft-de-assured data.

The memory controller 100 and the semiconductor memory device 200 can be integrated into one semiconductor device. Illustratively, the memory controller 100 and the semiconductor memory device 200 may be integrated into a single semiconductor device to form a solid state drive (SSD). The solid state drive may include a storage device configured to store data in a semiconductor memory. When the semiconductor memory system 10 is used as a solid state drive (SSD), the operation speed of a host connected to the semiconductor memory system 10 can be remarkably improved.

The memory controller 100 and the semiconductor memory device 200 may be integrated into one semiconductor device to form a memory card. For example, the memory controller 100 and the semiconductor memory device 200 may be integrated into a single semiconductor device and may be a PC card (PCMCIA), a compact flash card (CF), a smart media card (SM) (SD), miniSD, microSD, SDHC), universal flash memory (UFS), and the like can be constituted by a memory card (SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro)

As another example, semiconductor device 10 may be a computer, a UMPC (Ultra Mobile PC), a workstation, a netbook, a PDA (Personal Digital Assistants), a portable computer, a web tablet, Such as a tablet computer, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game machine, Device, a black box, a digital camera, a DMB (Digital Multimedia Broadcasting) player, a 3-dimensional television, a smart television, a digital audio recorder, Digital audio players, digital picture recorders, digital picture players, digital video recorders, digital video players, and data centers. story One of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, an RFID Device, or one of various components that constitute a computing system, and so on.

4A, the memory controller 100 may include a storage unit 110, a CPU 120, an LDPC unit 130, a host interface 140, a memory interface 150, and a system bus 160 have. The storage unit 110 may be used as an operation memory of the CPU 120.

The host interface 140 may be a USB (Universal Serial Bus), a Multi-Media Card (MMC), a Peripheral Component Interconnect-Express (PCI-E), a Serial Attached SCSI (SAS), a Serial Advanced Technology Attachment Parallel Advanced Technology Attachment, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), and the like.

The LDPC unit 130 can detect and correct an error included in the data read from the semiconductor memory device 200 as described above. The memory interface 150 may interface with the semiconductor memory device 200. 4A shows an embodiment in which the LDPC unit 130 includes both the LDPC encoder 131 and the LDPC decoder 133. In reality, the LDPC encoder 131 and the LDPC decoder 133 are substantially As shown in FIG. The CPU 120 can perform overall control operations.

According to an embodiment of the present invention, in a program operation, the LDPC unit 130 may perform LDPC encoding on original data with respect to data to be programmed into the semiconductor memory device 200. [ In this case, in the read operation, the LDPC unit 130 performs LDPC decoding on the encoded data, that is, the codeword, programmed in the semiconductor memory device 200.

The LDPC unit 130 can recover the original data before being encoded by decoding the encoded data stored in the semiconductor memory device 200, that is, the codeword.

As described later with reference to FIG. 5, the read operation for the data stored in the semiconductor memory device 200 may include the hard-read read operation of step S511 and the soft-read read operation of step S531. The hard-decision read operation is an operation of reading data from the semiconductor memory device 200 at the hard-decision read voltage V _HD . The soft-decision read operation is an operation of reading data from the semiconductor memory device 200 with soft-decision read voltages V _SD having a level different from the hard-decision read voltage V _HD . For example, in the memory cells read using the hard-decision lead voltages V _HD , the soft-decision read operation may additionally be performed using the soft-decision read voltages V _SD .

The encoded data read from the semiconductor memory device 200 by the hard-decision read operation, that is, the codeword, can be decoded by the LDPC unit 130 into the original data.

The soft-decision read operation is not an operation of simply reading data stored in the semiconductor memory device 200, but rather a logic likelihood ratio log (log), which is information capable of adding reliability to the data read by the hard- quot; LLR ") by the soft-decision lead voltages V _SD .

The LLR may be LDPC decoded by the LDPC unit 130. [ The LDPC unit 130 can detect and correct errors of the encoded data read from the semiconductor memory device 200 using the LLR, that is, code words.

The semiconductor memory device 200 may include a cell array 210, a control circuit 220, a voltage supply 230, a voltage transfer portion 240, a read / write circuit 250, and a column select portion 260 have.

The cell array 210 may include a plurality of memory blocks 211. The memory block 211 may store user data.

Referring to FIG. 4B, the memory block 211 may include a plurality of cell strings 221 connected to bit lines BL0 to BLm-1, respectively. The cell string 221 of each column may include at least one drain select transistor (DST) and at least one source select transistor (SST). A plurality of memory cells or memory cell transistors MC0 to MCn-1 may be connected in series between the select transistors DST and SST. Each memory cell MC0 to MCn-1 may be constituted by an MLC storing a plurality of bits of data information per cell. Strings 221 may be electrically connected to corresponding bit lines BL0 to BLm-1, respectively.

FIG. 4B exemplarily shows a memory block 211 composed of NAND-type flash memory cells. However, the memory block 211 of the memory device of the present invention is not limited to the NAND flash memory but may be a NOR-type flash memory, a hybrid flash memory in which at least two types of memory cells are mixed, And a built-in One-NAND flash memory. The operation characteristics of the semiconductor device can be applied not only to a flash memory device in which the charge storage layer is made of a conductive floating gate but also to a charge trap flash (CTF) in which the charge storage layer is made of an insulating film.

Returning to Fig. 4A, the control circuit 220 may control all operations related to the program, erase, and read operations of the semiconductor memory device 200. Fig.

The voltage supply circuit 230 is connected to the word line voltages (e.g., program voltage, read voltage, pass voltage, etc.) to be supplied to the respective word lines in accordance with the operation mode, Lt; RTI ID = 0.0 > well region). ≪ / RTI > The voltage generating operation of the voltage supplying circuit 230 may be performed under the control of the control circuit 220. [

The voltage supply circuit 230 may generate a plurality of variable lead voltages to generate a plurality of lead data.

The voltage transfer unit 240 selects one of the memory blocks (or sectors) of the memory cell array 210 in response to the control of the control circuit 220 and selects one of the word lines of the selected memory block have. The voltage transfer portion 240 may provide the word line voltage generated from the voltage supply circuit 230 in response to the control of the control circuit 220 to selected word lines and unselected word lines, respectively.

The read / write circuit 250 is controlled by the control circuit 220 and may operate as a sense amplifier or as a write driver depending on the mode of operation. For example, in the case of a verify / normal read operation, the read / write circuit 250 may operate as a sense amplifier for reading data from the memory cell array 210. In a normal read operation, the column selection unit 260 may output data read from the read / write circuit 250 to the outside (for example, a controller) in response to column address information. Alternatively, the data read during the verify read operation may be provided to a pass / fail verify circuit (not shown) in the semiconductor memory device 200, and used to determine whether the memory cells are successfully programmed.

In the case of a program operation, the read / write circuit 250 may operate as a write driver that drives bit lines in accordance with data to be stored in the cell array 210. The read / write circuit 250 may receive data to be used for the cell array 210 during a program operation from a buffer (not shown), and may drive bit lines according to the input data. To this end, the read / write circuit 250 may comprise a plurality of page buffers (PB) 251, each corresponding to columns (or bit lines) or a pair of columns (or bit line pairs). A plurality of latches may be provided in each page buffer 251.

Referring to FIGS. 4A and 5, the method of operating the memory controller 100 may include a hard decoding decoding step (S510), and a soft decoding decoding step (S530) may be additionally configured. The object data of the hard and soft decode decoding steps S510 and S530, that is, the data stored in the semiconductor memory device 200, are LDPC encoded data encoded by the LDPC unit 130, That is, a codeword.

For example, the hard Decision decoding step (S510) is hard Decision on hard Decision read data of a predetermined length read from the memory cells of the memory block 211 to the hard Decision read voltage (V _HD) LDPC Decoding step. The hard decision decoding step S510 may include steps S511 to S515.

For example, in the soft decoding process (S530), when the hard decoding LDPC decoding finally fails in the hard decoding decoding process (S510), the soft decoding process is performed on the specific hard decoding read voltage (V _HD ) And a soft-decode LDPC decoding step of performing soft-decision read data to perform LDPC decoding. The soft-decision decoding step S530 may include steps S531 to S535.

As described above, hard-read lead data may be read from the semiconductor memory device 200 at hard-read lead voltages V _HD in step S511, which is a hard-read lead stage. The memory controller 100 may transmit a read command and an address to the semiconductor memory device 200. [ The semiconductor memory device 200 may read the hard-read lead data from the semiconductor memory device 200 with the hard-read lead voltages V _HD in response to the read command and the address. The read hard-read lead data may be transmitted to the memory controller 100.

In step S513, the hard-decoding LDPC decoding may be performed as the first LDPC decoding. The LDPC unit 130 performs hard discontinuous LDPC decoding using the error correction code using the hard-read lead voltages V _HD from the semiconductor memory device 200 can do.

In step S515, it is determined whether or not the hard-decision LDPC decoding is successful. That is, in step S515, it is determined in step S513 whether the error of the hard-decoded LDPC decoded hard-decision data is corrected. For example, the memory controller 100 may correct the error of the hard-decoded LDPC decoded hard-decoded data using the hard-decoded LDPC decoded hard-decision data and the parity check matrix, . For example, when the result of the hard-decision LDPC-decoded hard-decision data and the parity-check matrix is a zero matrix (' 0 '), the hard-decoded LDPC decoded hard- . On the other hand, when the result of the hard-decision LDPC decoded hard-decision data and the parity-check matrix is not a zero matrix (' 0 '), the hard-decoded LDPC decoded hard- Can be determined.

If it is determined in step S515 that the hard-decoded LDPC decoding in step S513 is successful, in step S520, the read operation based on the hard-read lead voltage V _{HD in} step S511 is evaluated as being successful, Decoding may be terminated. The hard-decoded LDPC decoded hard-decoded data of step S513 may be output to the outside of the memory controller 100 as error-corrected data, or may be used inside the memory controller 100. [

If it is determined in step S515 that the hard-decoding LDPC decoding in step S513 is unsuccessful, the soft-decoding decoding step (S530) may be performed.

As described above, the soft-decision lead data can be read out from the semiconductor memory device 200 with the soft-decision lead voltages V _SD in the step S531, which is the soft-decision read step. For example, in the memory cells read using the hard-decision lead voltages V _HD , an additional read can be performed using the soft-decision read voltages V _SD . The soft-decision lead voltages V _SD may have different levels from the hard-decision lead voltages V _HD .

In step S533, the soft-decoding LDPC decoding may be performed as the second LDPC decoding. The soft-decode LDPC decoding may be performed based on soft-read lead data including soft-read lead data and soft-read lead voltages (V _SD ). The hard-decision lead voltages V _HD and the soft-decision lead voltages V _SD may have different levels.

For example, each of the memory cells MC0 to MCn-1 of the semiconductor memory device 200 has a threshold voltage distribution (P1 to P7) of seven program states illustrated in FIG. 2 and one erase state state threshold voltage distribution (E).

Each of the hard-decision lead voltages V _HD may have a voltage level between two adjacent logic states among the plurality of states. Each of the soft-decision read voltages V _SD has a level between two adjacent logic states among the plurality of states, and may have a level different from the hard-decision lead voltages V _HD .

The hard default lead data value read from the memory cells MC0 to MCn-1 to the hard lead read voltage V _HD and the soft lead read data value read to the soft lead read voltage V _SD are different from each other can be different. For example, there may be tail cells with threshold voltages that are lower or higher than the voltage distribution of the normal logic state among the memory cells. The data value read to the hard decision lead voltage (V _HD ) in the tail cells and the data value read out to the soft decision lead voltage (V _SD ) may be different from each other. In addition to the lead according to the hard-decision lead voltage V _HD , when additional read according to the soft-decision lead voltages V _SD is performed, the threshold voltages of the memory cells MC 0 to MCn- LLR (e.g., information on tail cells), which is information that can add reliability to the data read by the hard-read lead operation, can be obtained.

If the additional information is obtained, the probability that the data stored by the memory cells MC0 to MCn-1 is a first state (e.g., '1') or a second state (e.g., '0' The accuracy of the likelihood ratio can be increased. That is, the reliability of the LDPC decoding can be increased. The memory controller 100 may perform the soft-decoding LDPC decoding using soft-read lead data read with the hard-read lead voltage V _HD and the soft-read lead voltage V _SD . The relationship between the hard-decision lead voltage V _HD and the soft-decision lead voltage V _SD will be described later with reference to FIGS. 7A and 7B.

In step S535, it is determined that the soft-decoding LDPC decoding is successful. That is, in step S535, it is determined in step S533 whether the error of the soft-devised LDPC decoded soft-decoded data is corrected. For example, the memory controller 100 corrects errors of the soft-devised LDPC decoded soft-decoded data using the soft-devised LDPC decoded soft-decision data and the parity check matrix . For example, when the operation result of the soft-decision LDPC decoded soft-decision data and the parity-check matrix is a zero matrix (' 0 '), the soft-devised LDPC decoded soft- . On the other hand, when the result of the soft-devised LDPC decoded soft-decoded data and the parity-check matrix is not a zero matrix (' 0 '), the soft-devised LDPC decoded soft- Can be determined.

The operation of the soft-devised LDPC decoded soft-decision data and the parity-check matrix, and the operation of the hard-decoded LDPC decoded hard-decision data and the parity-check matrix may be performed in the same manner.

If it is determined in step S535 that the soft-decoding LDPC decoding in step S533 is successful, in step S520, the read operation based on the soft-decision read voltage V _{SD in} step S531 is evaluated as being successful, The correction decoding can be ended. The soft-decoded LDPC decoded soft-decoded data of step S533 may be output to the outside of the memory controller 100 as error-corrected data, or may be used inside the memory controller 100. [

If it is determined in step S535 that the soft-decoding LDPC decoding in step S533 is unsuccessful, in step S540, the read operation based on the soft-decision read voltage V _{SD in} step S531 is evaluated as failure The error correction decoding can be ended.

6A is a conceptual diagram showing an LDPC decoding represented by a tanner graph.

6B is a conceptual diagram showing an LDPC code structure.

6C is a conceptual diagram illustrating a syndrome check process according to LDPC decoding.

ECC can be used routinely in storage systems. Various physical phenomena occurring in the storage device cause a noise effect that damages the stored information. The error correction coding scheme can be used to protect the stored information from the final error. This can be done by encoding the information prior to storage in the memory device. The encoding process converts the information bit sequence into a codeword by adding redundancy to the information. Such redundancy may be used to recover information from the corrupted codeword somehow through the decoding process.

In the iterative coding scheme, the code is composed of a series of some simple configuration codes, and can be decoded using an iterative decoding algorithm by exchanging information between the constituent decoders of the simple code. Typically, such code can be defined using a tanner graph or a bipartite graph that represents the interconnection between the configuration codes. In this case, the decoding can be seen as a repetitive message passing through the graph edge.

A popular kind of iterative code is the Low Density Parity Check (LDPC) code. The LDPC code is a linear binary block code formed by a low density (sparse) parity check matrix H.

Referring to FIG. 6A, the LDPC code is a code having a very small number of 1s in each row and column of a parity check matrix defining a code, and includes check nodes 610 and variable the structure may be defined by a tanner graph composed of nodes 620 and edges 615 connecting the check nodes 610 and the variable nodes 620. The value transferred from the check node 610 to the variable node 620 after the check node processing is a check node message 615A and the value transferred from the variable node 620 to the check node 610 after variable node processing Is a variable node message 615B.

The decoding of the LDPC code is generally iterative decoding by a sum-product algorithm. Decoding using a message-passing algorithm of a suboptimal method such as the Min-sum algorithm in which the sum-product algorithm is simplified.

For example, referring to FIG. 6B, a tanner graph of an LDPC code includes 5 check nodes 610 representing a parity check equation of a predetermined LDPC code, 10 variable nodes 620 representing each symbol, and their associativity And edges 615 representing the edges. The edges 615 may be connected to variable nodes 620 corresponding to the code symbols included in the parity check equation indicated by the check node 610 in each check node 610. 6B illustrates a regular LDPC code in which the number of variable nodes connected to each of all check nodes 610 is constant at four, and the number of check nodes connected to each variable node 620 is constant at two. The initial value of the variable node 620 may be hard-devised data or soft-devised data.

Referring to FIG. 6C, a parity check matrix H corresponding to the Tanner graph is shown. This is similar to the graphical representation of parity check matrices, so that each column and each row of the parity check matrix H has the same number of ones. That is, each column of the parity check matrix H has two 1s indicating the connection of the check nodes 610 in addition to the variable nodes 620, and each row is connected to each of the check nodes 610 1 < / RTI > representing the concatenation of the variable nodes 620 for < RTI ID = 0.0 >

In the LCPC decoding, the variable node 620 on the tanner graph and the check nodes 610 repeat the process of exchanging messages generated and updated for each node. At this time, each node can update the message using a sum-product algorithm or a similar suboptimal method.

The LDPC decoding of the predetermined length of hard-read lead data read from the memory cell of the memory block 211 with the first hard-read lead voltage V _HD is performed after the initial update of the variable node 620, An update, a variable node update, and a syndrome check may be composed of a plurality of circuits. After completion of the syndrome check, if the result of the syndrome check satisfies a predetermined condition, the LDPC decoding is terminated. If the result of the syndrome check does not satisfy the predetermined condition, the check node update, the variable node update, Lt; RTI ID = 0.0 > 1 < / RTI > The one repetition of the plurality of times is limited to the maximum number of repetitions. If the predetermined condition is not satisfied until the maximum number of repetitions is reached, the LDPC decoding for the codeword, that is, the LDPC decoding, can be evaluated as failed.

Referring to FIG. 6C, the syndrome check determines whether a product (H v ^t ) operation result of the vector ( v ) obtained as a result of the variable node update and the parity check matrix H satisfies the predetermined condition , And if the zero vector ( 0 ) is obtained as a result of the product operation, the predetermined condition is satisfied.

FIG. 6C shows the syndrome checking process. 6C illustratively shows a vector "01000" that is not a zero as a result of the product operation, and therefore the syndrome check shown in FIG. 6C does not satisfy the predetermined condition, .

As a result of the product operation, if the vector "01000" is not zero , the number of elements that do not satisfy the condition of the non-zero vector elements, that is, the zero vector of the syndrome check, is one. In this specification, an element that does not satisfy the zero vector ( 0 ) condition of the syndrome check on the product result of one iteration is defined as USC (Unsatisfied Syndrome Check). 6C shows the result of a syndrome check where the number of USCs is 1. FIG.

FIG. 7A is a conceptual diagram showing a 2-bit soft-decision read operation shown in FIG. 5, FIG. 7B is a soft-switched read operation shown in FIG. 5, FIG.

Referring to FIG. 7A, in the hard decision decoding step S510 described with reference to FIG. 5, when the hard decision read voltage V _HD is applied to the memory cell of the semiconductor memory device 200, The hard decision data (2-1) may have a value of either 1 or 0 depending on the on-off state of the cell.

In the soft-decode decoding step S530, the soft-decision read operation includes a plurality of soft-decision read voltages V _{SD1 and} V _SD2 having a constant voltage difference with respect to the hard-decision read voltage V _HD , May be applied to the memory cell to form reliability information, that is, LLR, to the hard-read lead data.

The 2-bit soft-Decision the case of the read operation, the memory cell a first read voltage Soft Decision (V _SD1) of said plurality of Soft Decision read voltage (V _{SD1, SD2} V) as shown in Figure 7a The first soft-decision read data value 2-2 may be "1000" in accordance with the on or off state of the memory cell. Similarly, the second soft-decision lead data value 2-3 is set to "1110" according to the second soft- _decision lead voltage V _SD2 of the plurality of soft-decision lead voltages V _{SD1 and} V _SD2 , .

For example, the LDPC unit 130 performs an exclusive NOR (XNOR) operation on the first and second soft read data values 2-2 and 2-3 to generate soft-devised data 2- 4), i.e., an LLR. The LLR 2-4 may add reliability to the hard-decision data 2-1.

For example, the soft-designation data 2-4 "1" indicates that the first state (e.g., '1') of the hard-decision data 2-1 or the second state 0 " indicates that the probability of occurrence of the hard decision data 2-1 is strong, and "0" indicates a probability that the first state (e.g., '1' '0') is weak (weak).

7B, in the hard decision decoding step S510 described with reference to FIG. 5, when the hard decision read voltage V _HD is applied to the memory cell of the semiconductor memory device 200, The hard decision data (3-1) may have a value of either 1 or 0 depending on the on-off state of the cell.

In the soft-decision decoding step S530, the soft-decision read operation includes a plurality of soft-decision read voltages V _SD1 to V _SD6 having a constant voltage difference with respect to the hard-decision read voltage V _HD , May be applied to the memory cell to form reliability information, that is, LLR, to the hard-read lead data.

7B, in the case of a 3-bit soft-decision read operation, the first and second soft-decision lead voltages V _{SD1 and} V _SD6 among the plurality of soft-decision lead voltages V _SD1 to V _{SD6 SD2} are applied to the memory cell, first and second soft-read lead data values are generated as described with reference to FIG. 7A, and XNOR (exclusive NOR ) Operation can be performed so that the first soft decision data (3-2) "1001" can be generated.

When the third to sixth soft decision lead voltages V _SD3 to V _SD6 having a constant voltage difference around the first and second soft decision lead voltages V _{SD1 and} V _SD2 are applied to the memory cell, The third to sixth soft decision lead data values are generated similarly to the case described with reference to FIG. 7A, and an exclusive NOR (XNOR) operation is performed on the third to sixth soft decision lead data values, The decryption data 3-3, that is, the LLR "10101" The LLR 3-3 may assign a weight to the first soft decision data 3-2.

For example, the second soft-designation data 3-3 "1" is very likely to be the first state (for example, "1") of the first soft-design data 3-2 quot; is very strong, and "0" may indicate that the probability of being the first state (e.g., '1') of the first soft decision data 3-2 is strong.

Likewise, the second soft-designation data 3-3 "1" has a very low probability of being the second state (eg, "0") of the first soft-design data 3-2 weak, and "0" indicates that the probability of being weak in the second state (e.g., '0') of the first soft decision data 3-2 is weak. That is, similarly to the case described in FIG. 7A, the LLR 3-3 may add more reliability to the hard-decision data 3-1.

8A is a detailed block diagram illustrating an LDPC decoder 133 according to an embodiment of the present invention.

8A, the LDPC decoder 133 includes an LDPC decoding unit 135 and a parity check matrix correction unit 137. [

The LDPC decoding unit 135 performs LDPC decoding on encoded data, i.e., a codeword, programmed in the semiconductor memory device 200 in the main LDPC decoding mode or the sub LDPC decoding mode, And outputs decoded data, that is, original data.

The LDPC decoding unit 135 decodes the encoded data, that is, the codeword programmed into the semiconductor memory device 200 in the main LDPC decoding mode, with reference to FIGS. 5 to 6C LDPC decoding can be performed. Specifically, after the initial update of the variable node 620, one iteration consisting of check node update and variable node update and syndrome check based on the original parity check matrix H is performed until LDPC decoding is successful A predetermined number of times. Here, the check node update and the variable node update based on the original parity check matrix H are updates between the check node 610 and the check node 620 connected in accordance with the original parity check matrix H. Here, the original parity check matrix H includes both a regular parity check matrix and an irregular parity check matrix.

If the number of USCs does not decrease any more despite the predetermined number of LDPC decoding, the LDPC decoding unit 135 determines that the number of USCs is trapped and stops the main LDPC decoding mode.

When the main LDPC decoding mode is interrupted, the LDPC decoding unit 135 provides the parity check matrix correction unit 137 with information on the USC.

The parity check matrix corrector 137 changes some of the rows of the original parity check matrix H to dummy data ("0") when the main LDPC decoding mode of the LDPC decoding unit 135 is stopped, H ').

The parity check matrix corrector 137 selects a predetermined number of check nodes from the 2 * t-th check nodes in the 2 * t level tree structure having the USC node corresponding to the USC as the root node , And the modified parity check matrix H 'is generated by changing the rows of the original parity check matrix H corresponding to the selected check node to dummy data ("0").

Here, the tree structure is a data structure in which an edge 615 path is developed with an arbitrary check node 610 or an arbitrary variable node 620 of the parity check matrix H represented by a tanner graph or a half graph as a top node. As described above, the edge 615 is a node-to-node message exchange path, the value that is passed from the check node 610 to the variable node 620 is the check node message 615A, The value delivered to node 610 is a variable node message 615B. Check node 610 and variable node 620 are updated based on the delivered variable node message 615B and check node message 615A.

8B is a diagram showing two-level tree structures having each of the USC nodes as a top node.

As shown in FIG. 8B, each tree structure that is a top-level node of a USC node corresponding to USC has variable node 620 connected to USC nodes c1 to cn and edge 615 at a first level, The variable node 620 disposed at the first level and the check node 610 connected to the edge 615 are disposed at the second level. According to one embodiment of the present invention, when check node 610 and variable node 620 are arranged at each level along the edge 615 path in this manner, check node 610 placed at 2 * do. Where t is set to the separation value of the trapping set if the information about the trapping set of the LDPC code is known and to 1 if the information about the trapping set of the LDPC code is unknown. In general, information about incorrect variable nodes and trapping sets in the parity check matrix can not be known a priori. Here, an incorrect variable node refers to a variable node that is not corrected to an accurate variable node despite repeated LDPC decoding, and a trapping set refers to an incorrect variable node and a set of check nodes connected to the variable nodes by edges do. Here, in a tree structure in which an incorrect variable node of a trapping set is a root node, at least one check node having an edge of 1 among the check nodes arranged at the first level is an inexact variable If the node is not a descendant node, the trapping set is s-separated, where the separation value of the trapping set is s.

According to one embodiment of the present invention, a predetermined number (d _f ) of 2 * t level check nodes 610 connected to the edge 615 at each variable node 620 of the 2 * And a row of the original parity check matrix H corresponding to the selected check node is changed to dummy data ("0") to generate a modified parity check matrix H '.

Here, the predetermined number d _f satisfies the following equation (1).

Where d _v is the number of edges 615 of the variable node of the 2 * t-1th level.

8C is a conceptual diagram illustrating an operation for selecting check nodes according to an embodiment of the present invention.

For example, referring to FIGS. 8B and 8C, the parity check matrix correcting unit 137 may perform a two-level tree structure (t = 1, 2, 3, 1, 2t = 2, 2t-1 = 1) of the check nodes 610 connected to the edge 615 at each variable node 620 of the first level as shown in FIG. 8C, (610) and changes the rows of the original parity check matrix (H) corresponding to the selected check node to dummy data ("0") to generate a modified parity check matrix H '.

According to an embodiment of the present invention, a check node among a check node of a 2 * t-th level is selected by applying a predetermined selection probability (p _r ), and a check matrix of a check matrix of a source parity check matrix H And changes the rows to dummy data ("0") to generate a modified parity check matrix H '. Specifically, the parity check matrix corrector 137 selects a check node among a plurality of check nodes by determining whether to select or not by applying a preset selection probability p _r to each 2 * t-th level check node, The modified parity check matrix H 'is generated by changing the rows of the original parity check matrix H corresponding to the check nodes to dummy data ("0").

Here, the predetermined probability (p _r ) satisfies the following formula (2).

8D is a conceptual diagram illustrating the operation of selecting check nodes in accordance with an embodiment of the present invention.

For example, referring to FIGS. 8B and 8D, the parity check matrix correcting unit 137 may calculate the parity check matrix C in the two-level tree structures having the top nodes of the USC nodes c1 to cn as shown in FIG. 8B 8d, a selected check node among the check nodes of the second level is selected by applying a preset selection probability (p _r ), and the rows of the original parity check matrix H corresponding to the selected check node are divided into dummy data Quot; 0 ") to generate a modified parity check matrix H '. As shown in FIG. 8D, the parity check matrix corrector 137 selects a check node by applying a preset selection probability (p _r ), so that the number of check nodes selected for each variable node of the first level may be different have.

As a result, the modified parity check matrix H 'is a matrix in which some rows of the original parity check matrix H are changed to dummy data ("0"). The check node 610 corresponding to the dummy data ("0") is no longer connected to the variable node 620 and the edge 615, The update differs from that of the original parity check matrix (H).

The parity check matrix corrector 137 may generate a plurality of different modified parity check matrices H '. The parity check matrix corrector 137 selects the check nodes and changes the rows of the original parity check matrix H corresponding to the selected check node to dummy data ("0") to generate a first modified parity check matrix H ' ), Reselects the check nodes, and changes the rows of the original parity check matrix H corresponding to the re-selected check nodes to dummy data ("0") to obtain a second modified parity check matrix H ' A plurality of different modified parity check matrices H 'can be generated in a generating manner. In this case, since the selected check node and the re-selected check node are selected differently, the first modified parity check matrix H 'and the second modified parity check matrix H' will also have different structures.

The parity check matrix corrector 137 provides the generated modified parity check matrix H 'to the LDPC decoding unit 135.

The LDPC decoding unit 135 starts the sub LDPC decoding mode when the modified parity check matrix H 'is input.

The LDPC decoding unit 135 repeats the check node update and the variable node update a predetermined number of times based on the modified parity check matrix H 'in the sub LDPC decoding mode. Here, the check node update and the variable node update based on the modified parity check matrix H 'are updated between the check node 610 and the check node 620 connected to the edge 615 according to the modified parity check matrix H' to be.

When a plurality of different first and second modified parity check matrices H 'are input, the LDPC decoding unit 135 repeats the check node update and the variable node update based on the order of the modified parity check matrices H' . That is, the LDPC decoding unit 135 repeats a predetermined number of check node update and variable node update based on the first modified parity check matrix H ', and then, based on the second modified parity check matrix H' And repeats a predetermined number of check node updates and variable node updates.

The LDPC decoding unit 135 terminates the sub LDPC decoding mode and resumes the main LDPC decoding mode when the check node update and the variable node update are performed a predetermined number of times. In the resumed main LDPC decoding mode, the LDPC decoding unit 135 does not proceed to initial update of the variable node 620, but performs check node update and variable node update based on the original parity check matrix H, And performs one iteration a plurality of times.

Since the LDPC decoding unit 135 performs variable node update and check node update on the basis of the modified parity check matrix H 'in the sub LDPC decoding mode, the LDPC decoding unit 135 updates the source LDPC decoding mode in the resumed main LDPC decoding mode, If variable node update and check node update are performed based on the parity check matrix H, the LDPC decoding in the resumed main LDPC decoding mode will proceed in a different manner from the LDPC decoding in the previous main LDPC decoding mode. In other words, the LDPC decoding unit 135 is able to successfully decode the codeword in the resumed main LDPC decoding mode since it is escaped from the trap through variable node update and check node update in the sub LDPC decoding mode.

8E is a graph showing a result of an operation simulation of the LDPC decoder 133 according to an embodiment of the present invention.

FIG. 8E shows an LDPC decoder (FNCR 50, FNCR 100) (a predetermined number (d _f )) of a scheme (first scheme) for arbitrarily selecting check nodes of a predetermined number (d _f ) according to an embodiment of the present invention 3), an LDPC decoder (VNCR 50, VNCR 100) (a preset probability (p _r ) of 0.7) of a scheme (second scheme) for arbitrarily selecting check nodes by applying a predetermined selection probability (p _r ) (Word Error Rate) according to Eb / N0 in the AWGNC of the LDPC decoder (Single 50, Single 100) according to FIG. The LDPC decoder according to the related art is a 5-bit uniform quantization (LDPC) decoder. 8E, when the number of repetition is 50, an LDPC decoder (Single 50), a first scheme LDPC decoder (FNCR 50), and a second scheme LDPC decoder (VNCR 50) The WER according to the same Eb / N0 is lowered. As shown in FIG. 8E, when the number of repetitions is 100, an LDPC decoder (Single 100), a first type LDPC decoder (FNCR 100), and a second type LDPC decoder (VNCR 100) The WER according to the same Eb / N0 is getting lower. Therefore, it can be seen that the performance of the LDPC decoder according to an embodiment of the present invention is better than that of the LDPC decoder according to the related art.

According to an embodiment of the present invention, when the LDPC decoder 135 is trapped, the LDPC decoder 133 performs check node update and variable node update a predetermined number of times using the modified parity check matrix H ' So that the LDPC decoding unit 135 can escape from the trap. Therefore, according to an embodiment of the present invention, data stored in the semiconductor memory device can be correctly read by performing LDPC decoding using the original parity check matrix H and the modified parity check matrix H '.

The LDPC decoder 133 according to an embodiment of the present invention as described above allows the disclosure of the present invention to be completed and uses the semiconductor memory system 10 to fully inform the person of ordinary skill in the art of the invention The LDPC decoder 133 according to an exemplary embodiment of the present invention is not limited to the semiconductor memory system 10 but may be used in other systems such as a communication system.

Figure 9 is an electronic device including a semiconductor memory system according to one embodiment of the present invention, including a memory controller 15000 and a semiconductor memory device 16000, according to one embodiment of the present invention. Block diagram.

9, an electronic device 10000, such as a cellular phone, a smart phone, or a tablet PC, may be coupled to a semiconductor memory device 16000, such as a flash memory device, And a memory controller 15000 capable of controlling the operation of the semiconductor memory device 16000. [

The semiconductor memory device 16000 corresponds to the semiconductor memory device 200 described with reference to Figs. 3 to 4B. The semiconductor memory device 16000 can store random data.

The memory controller 15000 corresponds to the memory controller 100 described with reference to Figs. 3 to 8E. Memory controller 15000 may be controlled by processor 11000 that controls the overall operation of the electronic device.

The data stored in the semiconductor memory device 16000 can be displayed through the display 13000 under the control of the memory controller 15000 operating under the control of the processor 11000. [

The wireless transceiver 12000 may provide or receive a wireless signal via the antenna ANT. For example, the wireless transceiver 12000 may convert the wireless signal received via the antenna ANT into a signal that the processor 11000 can process. The processor 11000 may therefore process the signal output from the wireless transceiver 12000 and store the processed signal in the semiconductor memory device 16000 via the memory controller 15000 or through the display 13000 .

The wireless transceiver 12000 may convert the signal output from the processor 11000 into a wireless signal and output the converted wireless signal to the outside through the antenna ANT.

The input device 14000 is a device that can input control signals for controlling the operation of the processor 11000 or data to be processed by the processor 11000 and includes a touch pad and a computer mouse May be implemented with the same pointing device, keypad, or keyboard.

The processor 11000 may be configured to display data output from the semiconductor memory device 16000, a wireless signal output from the wireless transceiver 12000, or data output from the input device 14000, 13000).

10 is an electronic device including a semiconductor memory system according to another embodiment of the present invention. The electronic device 20000 includes a memory controller 24000 and a semiconductor memory device 25000 according to an embodiment of the present invention. Block diagram.

The memory controller 24000 and the semiconductor memory device 25000 may correspond to the memory controller 100 and the semiconductor memory device 200 described with reference to Figs. 3 to 8E.

10, a personal computer (PC), a tablet computer, a netbook, an e-reader, a personal digital assistant (PDA), a portable multimedia player (PMP) , An MP3 player, or an MP4 player, includes a semiconductor memory device 25000 such as a flash memory device, a memory capable of controlling the operation of the semiconductor memory device 25000, And may include a controller 24000.

The electronic device 20000 may include a processor 21000 for controlling the overall operation of the electronic device 20000. The memory controller 24000 can be controlled by the processor 21000.

The processor 21000 can display data stored in the semiconductor memory device through a display according to an input signal generated by the input device 22000. For example, the input device 22000 may be implemented as a pointing device such as a touch pad or a computer mouse, a keypad, or a keyboard.

11 is an electronic device including a semiconductor memory system according to still another embodiment of the present invention. The electronic device includes a memory controller 32000 and a semiconductor memory device 34000 according to another embodiment of the present invention 30000).

The memory controller 32000 and the semiconductor memory device 34000 may correspond to the memory controller 100 and the semiconductor memory device 200 described with reference to Figs. 3 to 8E.

11, an electronic device 30000 may include a card interface 31000, a memory controller 32000, and a semiconductor memory device 34000, such as a flash memory device.

The electronic device 30000 can issue or receive data with the host (HOST) through the card interface 31000. According to one embodiment, card interface 31000 may be, but is not limited to, a secure digital (SD) card interface or a multi-media card (MMC) interface. Card interface 31000 may interface data exchange between host (HOST) and memory controller 32000 in accordance with the communication protocol of the host (HOST) capable of communicating with electronic device 30000.

The memory controller 32000 controls the overall operation of the electronic device 30000 and can control the exchange of data between the card interface 31000 and the semiconductor memory device 34000. In addition, the buffer memory 325 of the memory controller 32000 can buffer data exchanged between the card interface 31000 and the semiconductor memory device 34000.

The memory controller 32000 can be connected to the card interface 31000 and the semiconductor memory device 34000 via the data bus DATA and the address bus ADDRESS. According to one embodiment, the memory controller 32000 can receive the address of the data to be read or written from the card interface 31000 via the address bus ADDRESS and transmit it to the semiconductor memory device 34000.

In addition, the memory controller 32000 can receive or transmit data to be read or written via the data bus (DATA) connected to the card interface 31000 or the semiconductor memory device 34000, respectively.

When the electronic device 30000 of Fig. 11 is connected to a host (HOST) such as a PC, a tablet PC, a digital camera, a digital audio player, a mobile phone, a console video game hardware, or a digital set- May receive or receive data stored in the semiconductor memory device 34000 via the card interface 31000 and the memory controller 32000.

12 is an electronic device including a semiconductor memory system according to still another embodiment of the present invention. The electronic device includes a memory controller 44000 and a semiconductor memory device 45000 according to another embodiment of the present invention. Fig.

The memory controller 44000 and the semiconductor memory device 45000 may correspond to the memory controller 100 and the semiconductor memory device 200 described with reference to Figs. 3 to 8E.

12, the electronic device 40000 includes a semiconductor memory device 45000 such as a flash memory device, a memory controller 44000 for controlling data processing operations of the semiconductor memory device 45000, and an electronic device 40000, And an image sensor 41000 that can control the overall operation of the image sensor.

The image sensor 42000 of the electronic device 40000 converts the optical signal to a digital signal and the converted digital signal is stored in the semiconductor memory device 45000 under the control of the image sensor 41000 or is read out through the display 43000 Can be displayed. In addition, the digital signal stored in the semiconductor memory device 45000 can be displayed through the display 43000 under the control of the image sensor 41000.

13 is an electronic device including a semiconductor memory system according to another embodiment of the present invention, including a memory controller 61000 and semiconductor memory devices 62000A, 62000B, and 62000C according to another embodiment of the present invention Gt; 60000 < / RTI >

The memory controller 61000 and the semiconductor memory devices 62000A, 62000B and 62000C may correspond to the memory controller 100 and the semiconductor memory device 200 described with reference to Figs. 3 to 8E.

Referring to FIG. 13, the electronic device 60000 may be implemented as a data storage device such as a solid state drive (SSD).

The electronic device 60000 includes a plurality of semiconductor memory devices 62000A, 62000B and 62000C and a memory controller 61000 capable of controlling the data processing operation of each of the plurality of semiconductor memory devices 62000A, 62000B and 62000C .

The electronic device 60000 may be implemented as a memory system or a memory module.

According to one embodiment, the memory controller 61000 may be implemented inside or outside the electronic device 60000.

14 is a block diagram of a data processing system including the electronic device 60000 shown in FIG.

13 and 14, a data storage device 70000, which can be implemented as a RAID (Redundant Array of Independent Disks) system, includes a RAID controller 71000 and a plurality of memory systems 72000A, 72999B to 72000N .

Each of the plurality of memory systems 72000A, 72999B to 72000N may be the electronic device 60000 shown in Fig. A plurality of memory systems (72000A, 72999B to 72000N) may constitute a RAID array. The data storage device 70000 can be implemented as an SSD.

During the program operation, the RAID controller 71000 transmits the program data output from the host to a plurality of memory systems 72000A, 72999B (in accordance with one RAID level selected based on the RAID level information output from the host among the plurality of RAID levels) to 72000N) to any one of the memory systems.

During the read operation, the RAID controller 71000 acquires, from among a plurality of RAID levels, one of a plurality of memory systems (72000A, 72999B to 72000N) in accordance with one selected RAID level based on the RAID level information output from the host The data read from one memory system can be transferred to the host.

Although the present invention has been described in detail with reference to the exemplary embodiments, it is to be understood that various changes and modifications may be made without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited by the above-described embodiments, but should be determined by the claims equivalent to the claims of the present invention as well as the claims of the following.

10: Semiconductor memory system
100: Memory controller
110:
120: CPU
130: LDPC section
131: LDPC encoder
133: LDPC decoder
135: LDPC decoding unit
137: Parity check matrix correction
140: Host interface
150: Memory interface
160: System bus
200: semiconductor memory device
210: cell array
211: memory block
220: control circuit
230:
240:
250: Read / write circuit
260: Column selector

Claims (18)

A method of operating an LDPC (Low Density Parity Check) decoder,
A first step of initially updating a codeword to a variable node;
A second step of performing decoding based on the original parity check matrix;
If the number of USC (Unsatisfied Syndrome Check) does not decrease during the threshold number of times of decoding, a USC node corresponding to the USC corresponds to a check node selected from among the check nodes at the 2t- A third step of generating a modified parity check matrix by replacing the rows of the original parity check matrix with dummy data;
A fourth step of performing node update consisting of check node update and variable node update based on the modified parity check matrix;
A fifth step of repeating the one or more iterations a predetermined number of times until the decoding is successful,
≪ / RTI >
The method according to claim 1,
In the third step,
The fixed parity check matrix is generated by randomly selecting a predetermined number of check nodes from the 2t-th level check nodes connected edge to the (2t-1) -th level variable nodes in the tree structure
A method of operating an LDPC decoder.
The method according to claim 1,
In the third step,
Level nodes of the (2t-1) -th level in the tree structure, one or more check nodes are randomly selected according to a preset probability among the 2 < th > -level check nodes connected to the variable nodes to generate the modified parity check matrix
A method of operating an LDPC decoder.
The method according to claim 1,
The code word
Hard decibel data
A method of operating an LDPC decoder.
The method according to claim 1,
The code word
Soft Decision data in
A method of operating an LDPC decoder.
The method according to claim 1,
The second step comprises:
If the USC does not exist in the vector generated by the syndrome check, it is determined that the main decoding is successful
A method of operating an LDPC decoder.
A Low Density Parity Check (LDPC) decoder,
First means for initially updating the codeword to the variable node and performing decoding based on the original parity check matrix; And
If the number of USC (Unsatisfied Syndrome Check) does not decrease during the threshold number of times of decoding, the USC node corresponding to the USC is set as the highest node, And a second means for modifying the rows of the parity check matrix into dummy data to generate a modified parity check matrix,
Wherein the first means repeats the one iteration a predetermined number of times until the main decoding is successful by repeating the decoding and the node update consisting of the check node update and the variable node update based on the modified parity check matrix
LDPC decoder.
8. The method of claim 7,
The second means comprises:
The fixed parity check matrix is generated by randomly selecting a predetermined number of check nodes from the 2t-th level check nodes connected edge to the (2t-1) -th level variable nodes in the tree structure
LDPC decoder.
8. The method of claim 7,
The second means comprises:
Level nodes of the (2t-1) -th level in the tree structure, one or more check nodes are randomly selected according to a preset probability among the 2 < th > -level check nodes connected to the variable nodes to generate the modified parity check matrix
LDPC decoder. 8. The method of claim 7,
The code word
Hard decibel data
LDPC decoder.
8. The method of claim 7,
The code word
Soft Decision data in
LDPC decoder.
8. The method of claim 7,
Wherein the first means comprises:
If the USC does not exist in the vector generated by the syndrome check, it is determined that the main decoding is successful
LDPC decoder.
In a semiconductor memory system,
A semiconductor memory device; And
An LDPC decoder,
The LDPC decoder
First means for initially updating the codeword to the variable node and performing decoding based on the original parity check matrix; And
If the number of USC (Unsatisfied Syndrome Check) does not decrease during the threshold number of times of decoding, the USC node corresponding to the USC is set as the highest node, And a second means for modifying the rows of the parity check matrix into dummy data to generate a modified parity check matrix,
Wherein the first means repeats the one iteration a predetermined number of times until the main decoding is successful by repeating the decoding and the node update consisting of the check node update and the variable node update based on the modified parity check matrix
Semiconductor memory system.
14. The method of claim 13,
The second means comprises:
The predetermined number of check nodes are randomly selected from the 2t-th level check nodes connected to the (2t-1) -th level variable nodes in the tree structure to generate a modified parity check matrix
Semiconductor memory system.
14. The method of claim 13,
The second means comprises:
In the tree structure, one or more check nodes are randomly selected according to a preset probability among the 2 < th > -level check nodes connected edge to the (2t-1) -th level variable nodes to generate a modified parity check matrix
Semiconductor memory system.
14. The method of claim 13,
The code word
Hard decibel data
Semiconductor memory system.
14. The method of claim 13,
The code word
Soft Decision data in
Semiconductor memory system.
14. The method of claim 13,
Wherein the first means comprises:
If the USC does not exist in the vector generated by the syndrome check, it is determined that the main decoding is successful
Semiconductor memory system.

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