KR20160081861A - Gate driver and display device including thereof - Google Patents

Abstract

A shift register including an N-th stage connected to one end of a gate line, and a compensation circuit portion connected to the other end of the gate line, wherein the N-th stage is controlled by a voltage of a Q- And the compensation circuit portion is controlled by a second gate driving signal output from a next stage of the Nth stage to discharge the first gate driving signal.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a gate driver circuit and a display device including the gate driver circuit,

The present invention relates to a gate driving circuit and a display device including the same.

2. Description of the Related Art [0002] With the development of information electronic devices for realizing high-resolution and high-quality images such as portable telephones (portable phones), notebooks, computers, and HDTVs, flat panel displays Devices are increasingly in demand. As such flat panel display devices, a liquid crystal display (LCD), a plasma display panel (PDP), a field emission display (FED), and an organic light emitting diode (OLED) have been actively studied. However, And realization of a large area screen, a liquid crystal display (LCD) is in the spotlight at present.

The liquid crystal display device includes a liquid crystal display panel, a data driving circuit for supplying data to the data lines of the liquid crystal display panel, a gate driving circuit for supplying gate pulses to the gate lines of the liquid crystal display panel, And a timing controller for controlling the signal line. Such a liquid crystal display device generally has a gate and a data driver circuit formed in the form of an integrated circuit and attached to a liquid crystal display panel such as TCP or COF tape. As a result, the number of component elements is increased and the process cost is increased due to an increase in the number of component elements. This leads to a problem of weight reduction and miniaturization of the liquid crystal display device. Thus, a gate driver -IC in panel) type liquid crystal display device has been proposed.

In a liquid crystal display device having a built-in circuit, a data driver circuit is formed in a chip form and attached to a liquid crystal display panel such as a TCP or a COF tape. A display region of the liquid crystal display panel includes a plurality of gates and data And a gate driving circuit of a GIP system including a plurality of thin film transistors is provided outside the display area.

The gate driving circuit may include a shift register for driving a gate wiring, and the shift register includes a plurality of stages connected in cascade.

FIG. 1 is a view showing a conventional liquid crystal display panel having a gate driving circuit, and FIG. 2 is a view showing a plurality of liquid crystal display panels connected to display a large screen. And FIG. 3 is a view showing a large screen of a two-side GIP structure as shown in FIG.

Since the conventional gate drive circuits 21 and 22 are both-side GIP structures attached to both sides of the liquid crystal display panel 10, both bezels are designed to have the same width. In this case, when a plurality of liquid crystal display panels 10 are connected to display a large screen such as a billboard, as shown in FIG. 3, there is a problem that the connection area between the liquid crystal display panels 10 becomes twice as large as the bezel. In order to solve such a problem, in the one-side GIP structure in which the gate driving circuit is mounted on only one side of one liquid crystal display panel, the GIP characteristic is weakened due to a different signal delay in the panel load which is weighted on one side, .

The gate driving circuit and the display device including the gate driving circuit according to the embodiment of the present invention have a delay characteristic when the waveform of the gate driving signal reaches the terminal end of the panel from the entrance end, In order to solve the problem of getting out of specification and increasing the bezel of a large screen product, a signal is applied on the opposite side of the single side GIP driving to reduce the signal delay while driving the single side GIP, The present invention can provide a gate driving circuit capable of lowering a polling time of a waveform of a gate driving signal different from a signal delay by using a minimum transistor and a clock signal that pulls a waveform to a low potential voltage and a display device including the gate driving circuit.

A shift register including an N-th stage connected to one end of a gate line, and a compensation circuit portion connected to the other end of the gate line, wherein the N-th stage is controlled by a voltage of a Q- And the compensation circuit portion is controlled by a second gate driving signal output from the next stage of the Nth stage to discharge the first gate driving signal and a display device including the gate driving circuit. , The bezel of the panel is lowered by driving the unilateral GIP and the signal is applied on the opposite side of the gate driving circuit to pull the gate driving signal waveform with a delay to a low potential voltage to compensate the signal delay by lowering the polling time, In a large-sized image display apparatus which displays divided images, a bezel Cattle and can increase the quality of the image.

The gate driving circuit and the display device including the same according to the embodiment of the present invention can reduce the bezel of the panel by driving the unilateral GIP.

Also, the gate driving circuit and the display device including the same according to the present invention can apply a signal at the opposite side of the gate driving circuit to pull the gate driving signal waveform with a large delay to a low potential voltage, thereby compensating the signal delay by lowering the polling time It is effective.

Further, the gate driving circuit and the display device including the same according to the present invention can reduce the bezel at the connecting portion of the display panel in the large-sized image display device which displays one image by dividing one image, thereby improving the quality of the image.

In addition, the gate driving circuit and the display device including the same according to the present invention are provided with different low potential power sources in the compensation circuit portion, so that the ripple generated at the gate output can be removed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a view showing a conventional liquid crystal display panel having a gate driving circuit. FIG.
2 is a view showing a plurality of liquid crystal display panels connected to each other to display a large screen;
Fig. 3 is a diagram showing a large screen of a two-side GIP structure as shown in Fig.
4 is a block diagram of a display device including a display panel having a one-sided gate drive circuit according to the first embodiment;
5 is a diagram of a compensation circuit section of a display panel;
6 is a diagram showing a connection relationship of a plurality of stages constituting a shift register according to the first embodiment;
7 is a circuit diagram of the N stage.
8 is a diagram showing a start signal and a clock signal for driving a circuit of an Nth stage and accordingly a Q and a QB node voltage;
9 is a circuit diagram showing an N stage of the gate driving circuit according to the first embodiment and a compensation circuit portion.
10 is a waveform diagram showing an n-th gate driving signal of the N-th stage, (n + 2) th gate driving signal, and a first clock signal and a fifth clock signal;
11 is a waveform diagram showing a waveform of a gate driving signal in a conventional unilateral GIP structure and a waveform of a gate driving signal in a unidirectional GIP and compensation circuit structure according to the embodiment.
FIG. 12 is a waveform chart comparing a holding voltage of a pixel through a voltage difference between the entrance of the gate line and the end of the gate line in the conventional unilateral GIP structure. FIG.
13 is a waveform chart comparing a holding voltage of a pixel through a voltage difference between a gate line end portion and a gate line end portion in a unilateral GIP and compensation circuit structure according to the embodiment.
Fig. 14 is a diagram showing a screen in which a large-sized display device is constructed by connecting display panels with a bezel reduced. Fig.
15 is a circuit diagram showing a Nth stage and a compensation circuit portion of a gate driving circuit according to a second embodiment;
16 is a graph showing a gate output waveform according to the second embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the size and thickness of an apparatus may be exaggerated for convenience. Like reference numerals designate like elements throughout the specification.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. However, it should be understood that the present invention is not limited to the embodiments disclosed herein but may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification. The dimensions and relative sizes of the layers and regions in the figures may be exaggerated for clarity of illustration.

It will be understood that when an element or layer is referred to as being another element or "on" or "on ", it includes both intervening layers or other elements in the middle, do. On the other hand, when a device is referred to as "directly on" or "directly above ", it does not intervene another device or layer in the middle.

The terms spatially relative, "below," "lower," "above," "upper," and the like, And may be used to easily describe the correlation with other elements or components. Spatially relative terms should be understood to include, in addition to the orientation shown in the drawings, terms that include different orientations of the device during use or operation. For example, when inverting an element shown in the figures, an element described as "below" or "beneath" of another element may be placed "above" another element. Thus, the exemplary term "below" can include both downward and upward directions.

The terminology used herein is for the purpose of describing embodiments only and is not intended to be limiting of the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. &Quot; comprise "and / or" comprising ", as used in the specification, means that the presence of stated elements, Or additions.

<Display device>

FIG. 4 is a block diagram of a display device including a display panel having a one-side gate driving circuit according to an embodiment of the present invention, and FIG. 5 illustrates a compensation circuit portion of the display panel.

4, the display device of the present invention includes a display panel 100 for displaying an image, a timing controller 400 for receiving various timing signals from an external system to generate various control signals, And a gate driving circuit 200 for controlling the display panel 100. The gate driving circuit 200 includes a compensation circuit part 500 for compensating for a signal delay of the gate driving circuit 200 .

The gate driving circuit 200 may include a shift register 210 having a plurality of stages.

The display panel 100 has a structure in which K (K is a natural number) gate lines GL and a plurality of data lines DL are crossed in a matrix form on a substrate using a glass and a plurality of pixels 110 define. Each pixel 110 is provided with a thin film transistor (TFT), a liquid crystal capacitor Clc and a storage capacitor Cst, and all the pixels 110 constitute one display area A / A. A region where the pixel 110 is not defined may be divided into a non-display region N and a gate driving circuit may be disposed in the non-display region N. In another non-display region N_C, Can be disposed.

The timing controller 400 outputs a timing signal such as a video signal RGB transmitted from an external system and a clock signal DCLK, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and a data enable signal DE And generates a control signal for the gate drive circuit 200 and the data drive circuit 300.

Here, the horizontal synchronization signal Hsync is a signal indicating the time taken to display one horizontal line of the screen, and the vertical synchronization signal Vsync is a signal indicating the time taken to display a frame of one frame. The data enable signal DE is a signal indicating a period during which the data voltage is supplied to the pixel defined in the display panel 100.

Also, though not shown, the timing controller 400 is designed to receive image related signals and timing signals output from the external system through a predetermined interface, without noise, at a high speed. Such interfaces include a low voltage differential signal (LVDS) method or a transistor-transistor logic (TTL) interface method.

The timing controller 400 generates the control signal GCS of the gate driving circuit 200 and the control signal DCS of the data driving circuit 300 in synchronization with the input timing signal.

In addition, the timing controller 400 generates a plurality of clock signals for determining the driving timings of the respective stages of the gate driving circuit 200, and supplies them to the gate driving circuit 200 and the compensation circuit unit 500. The timing controller 400 arranges and modulates the received image data (RGB DATA) in a form that the data driving circuit 300 can process. Here, the aligned image data may be a form in which a color coordinate correction algorithm for improving image quality is applied. A gate start pulse, a gate shift clock, and a gate output enable are used as the control signal GCS of the gate driving circuit 200.

Next, the data driving circuit 300 generates a sampling signal by shifting a source start pulse (SSP) from the timing controller 400 according to a source shift clock (SSC). The data driving circuit 300 latches the image data input according to the source shift clock SSC according to the sampling signal and changes the data into a data signal and then outputs the data signal to the data driver 300 in response to a source output enable And supplies a data signal to the data lines DL in units of horizontal lines. To this end, the data driving circuit 300 may include a data sampling unit, a latch unit, a digital-analog converting unit, and an output buffer.

Next, the gate driving circuit 200 shifts a gate start pulse (GSP) transmitted from the timing controller 400 according to a gate shift clock (GSC) GL1 to GLn to the gate lines GL1 to GLn during the rest of the period in which the scan pulse of the gate high voltage VGH is not supplied, (VGL).

The gate driving circuit 200 may be formed independently of the panel and may be electrically connected to the panel in various ways. The gate driving circuit 200 may include a display panel (not shown) (GIP) method on the non-display area N in the form of a thin film pattern during the fabrication of the substrate of the TFT array substrate 100 shown in FIG. In this case, the gate control signal GCS for controlling the gate drive circuit 200 may be a clock signal CLK and a gate start pulse VST for driving the first driven stage of the shift register have.

Also, the gate driving circuit 200 may be configured as a double output stage of a Qb node sharing one outputting two gate driving signals (Vg), but is not limited thereto.

<Compensation Circuit Section>

5, a display panel 100 according to an embodiment of the present invention includes a gate driving circuit 200 disposed on one side and a compensation circuit portion 500 disposed on the other side. The gate driving circuit 200 And the compensation circuit part 500 may be connected through a gate line GL. That is, one side of the gate line GL may be connected to the gate driving circuit 200 and the other side may be connected to the compensation circuit unit 500 with reference to the gate line GL.

The compensation circuit unit 500 may include a plurality of compensation units 501 and each of the compensation units 501 may include first to third thin film transistors Ta, Tb, and Tc.

The first thin film transistor Ta is controlled by the voltage on the N-node, the drain terminal is connected to the gate line GL, and the source terminal is connected to the low potential power supply VSS so that the N-node is at the high logic level The potential of the gate line GL can be lowered to the low potential power supply VSS. The second thin film transistor Tb is operated by the gate driving signal Vg (m) on an arbitrary gate line G (m) and outputs an arbitrary clock signal CLKB on the drain terminal to the N source terminal N nodes can be provided. Therefore, when the gate drive signal Vg (m) on the arbitrary gate line G (m) is at the high logic level, the second thin film transistor Tb is turned on, and the arbitrary clock signal CLKB at that time is turned on. The voltage of the N-node may be a high logic level. The third thin film transistor Tc is operated by an arbitrary clock signal CLK and can function to vary the voltage on the N-node which is the drain terminal to the low potential power supply VSS which is the source terminal.

The clock signal CLKB supplied to the drain terminal of the second thin film transistor Tb and the clock signal CLK supplied to the gate terminal of the third thin film transistor Tc may have opposite logic levels . The clock signal CLK supplied to the gate terminal of the third thin film transistor Tc is referred to as a first clock signal CLK and the clock signal CLK supplied to the drain terminal of the second thin film transistor Tb (CLKB) may be a second logic level when the first clock signal CLK is at a high logic level, if the second clock signal CLKB is a second clock signal CLKB. The first clock signal CLK is not fixed to the low logic level when the second clock signal CLKB is at the high logic level and the gate driving signal G (m) Vg (m)) is a low logic level, the first clock signal CLK may be a high logic level.

The gate driving signal outputted from the gate driving circuit 200 turns on the thin film transistor TFT of the pixel 110 through the gate line GL so that the data signal on the data line DL is applied to the storage capacitor The compensation circuit unit 500 discharges the remaining gate driving signal on the gate line GL so that the thin film transistor TFT is turned on when the data signal is charged to the storage capacitor Cst And can be turned off at the required time.

<Connection relation of stage>

6 is a diagram illustrating a connection relationship between a plurality of stages constituting a shift register according to an embodiment of the present invention.

For convenience of explanation, N (N is a natural number, Nth stage means Nth stage) of the plurality of stages is referred to as a first stage, and Nth + 1 and N + 2 stages are referred to as second and third Look at the stage and explain.

Referring to FIG. 6, the shift register 210 according to the embodiment is a shift register included in the gate driving circuit 200 according to the embodiment shown in FIG.

The N, N + 1, N + 2 stages are shown as a plurality of stages constituting the shift register 210 according to the above embodiment.

Each of the N, N + 1, and N + 2 stages may receive at least a plurality of clock signals from the clock signal line CLK.

The eight clock signals CLK1 to CLK8 are formed in the clock signal line CLK to provide eight clock signals CLK1 to CLK8 so that the gate drive circuit 200 may have an eight- But the technical idea of the present invention can be applied to a gate driver of a two-phase, four-phase or six-phase structure.

Although not shown, a normal high voltage power source VDD and a low potential power source VSS for driving the gate driving circuit 200 may be supplied to the stages N, N + 1, N + have. The stages N, N + 1 and N + 2 share a predetermined number of thin film transistors in one stage, and divide the QB node (not shown) into the even and odd-numbered stages, And a double output structure for outputting the gate driving signals Vg (n) to Vg (n + 1).

The first and second start signals VST1 and VST2 are input as a start signal to the Nth stage which is the first stage and the first and second gate driving signals VST1 and VST2 are inputted in synchronization with the first and second clock signals CLK1 and CLK2, (Vg (n), Vg (n + 1)). Also, the Nth stage can receive the (n + 5) th gate drive signal Vg (n + 5) of the (N + 2) th stage as a reset signal. In the (N + 1) th stage, which is the second stage, the clock signal provided from the clock signal wiring may be the first and second start signals VST1 and VST2. In the (N + 2) Can function as the first and second start signals VST1 and VST2. That is, each stage receives the second gate driving signal of the next stage in the next stage as a reset signal, outputs the gate signal of the low logic level, and supplies the gate driving signal to the start signal of the next stage of the next stage.

The (N + 2) -th stage outputs the (n + 4) th and (n + 5) th gate driving signals Vg +5) to the reset signal of the N-th stage.

&Lt; Schematic diagram of stage and operation relationship of stage >

FIG. 7 is a circuit diagram of the N-th stage, and FIG. 8 is a diagram showing a start signal and a clock signal for driving the circuit of the N-th stage and corresponding Q and QB node voltages.

8, the gate driving signal Vg may have two voltage levels of a high logic level and a low logic level, and may have one to four horizontal periods (1 to 4H ) To the gate line GL sequentially. Here, the gate driving signal Vg output to the adjacent gate line GL is overlapped by 1 to 3 horizontal periods (1 to 3H), and the data signal Vdata is supplied to the pixels on one horizontal line in one horizontal period (1H).

6, 7 and 8, the N stage N included in the gate driving circuit of the present invention includes an odd stage (ODD) for outputting an n-th gate driving signal Vg (n) And a radix EVEN for outputting one gate driving signal Vg (n + 1). In particular, the QB1_ODD node of the odd stage ODD and the QB2_ODD node of the odd stage EVEN of the exemplified N stage N share each other, and the QB1_EVEN node of the odd stage ODD and the QB2_EVEN node of the odd stage EVEN share each other The number of thin film transistors provided in the odd stage and the odd stage EVEN is twenty-four, for example, 13, respectively. In addition, the ODD and EVEN may have the same structure in addition to the connection structure of the shared QB1 and 2_ODD nodes and the QB1 and 2_EVEN nodes.

The first_1T thin film transistor T1_1 is turned on by the first start signal VST1 to charge the node Q1 with the power source voltage VDD and the first thin film transistor T1_2 is turned on by the second start signal VST2 The node Q2 can be charged with the power supply voltage VDD.

The second thin film transistor T2_1 can discharge the node Q1 to the ground voltage VSS by receiving the next next gate driving signal VNEXT = Vg (n + 5), and the second thin film transistor T2_2 can It is possible to discharge the node Q2 to the ground voltage VSS by receiving the next stage gate driving signal VNEXT = Vg (n + 5).

The 4-1 thin film transistor T4_1 is turned on when the QB1_ODD node is charged to discharge the nodes Q1 and Q2 and the 4-2 thin film transistor T4_2 becomes conductive as the QB2_ODD node is charged, Can be discharged.

The 3_1th thin film transistor T3_1 may conduct as the QB1_EVEN node is charged to discharge the Q1 and Q2 nodes and the 3_2 thin film transistor T3_2 may conduct as the QB2_EVEN node is charged to discharge the Q1 and Q2 nodes have.

The sixth and sixth_2 thin film transistors T6_1 and T6_2 turn on the seventh and seventh thin film transistors T7_1 and T7_2 as the good power supply voltage VDD_O and the odd power source voltage VDD_E alternately go high level - Turn it on.

The 7_1 and 7_2 thin film transistors T7_1 and T7_2 are charged with the QB1 and 2_ODD nodes or the QB1 and 2_EVEN nodes through the high level power source voltage VDD_O or the power source voltage VDD_E.

The fifth transistor T5_1 may discharge the Q2 node Q2 when the Q1 node Q1 is charged and the Q2 node Q1 may discharge the Q2 node Q2 when the fifth transistor T5_2 is charged. Thereby discharging the battery.

The ninth thin film transistor T9_1 discharges the QB1 and 2_ODD nodes to the ground voltage VSS as the first start signal VST1 is applied and the ninth thin film transistor T9_2 discharges the second start signal VST2 As it is applied, the QB1, 2_EVEN node can be discharged to the ground voltage (VSS). The 10_1th and 2th thin film transistors T10_1 and T2_1 can discharge the QB1 and 2_ODD nodes or the QB1 and 2_EVEN nodes as the Q1 node or the Q2 node is charged. The 8_1 and the 2-thin film transistors T8_1 and T2 may function to turn off the seventh and the second transistors T7_1 and T2 as the Q1 node or the Q2 node is charged.

The first pull-up transistor Tup_1 functions as a pull-up buffer and is turned on as the node Q1 is charged to output the first clock signal CLK1 of high level to the nth gate driving signal Vg (n)). At this time, the voltage of the node Q1 may be bootstrapped by the high logic level of the first clock signal CLK1. The second pull-up transistor Tup_2 is turned on as the node Q2 is charged to output the high-level second clock signal CLK2 as the (n + 1) -th gate driving signal Vg (n + 1) have. At this time, the voltage of the node Q2 may be bootstrapped by the high logic level of the second clock signal CLK2.

The 11th and 11th thin film transistors T11_1 and T112 function as a pull-up buffer and output the n-th gate driving signal Vg (n) to a low level as the QB1_ODD node is charged And at the same time, the n-th gate driving signal Vg (n + 1) can be maintained at the low level. The ninth gate driving signal Vg (n) is maintained at a low level as the QB1 and 2_EVEN nodes are charged, and the (n + 1) th gate driving signal Vg (Vg (n + 1)) can be output at a low level.

The driving of the stage of the gate driving circuit according to the above structure will be described as follows.

As the first start signal VST1 of high level is inputted, the first 1_1th thin film transistor T1_1 of the odd stage is turned on to charge the node Q1 to the high logic level, T5_1 and the ninth transistor T9_1 are turned on so that the nodes QB1 and 2_ODD and the nodes QB1 and 2_EVEN are discharged. At this time, the even-numbered power source voltage VDD_O is a high logic level state, and the 6_1th thin film transistor T6_1 is in a diode state, and the 7_1th and 7th thin film transistors T7_1 and T7_2 Is maintained in the turn-off state.

Next, when the first clock signal CLK1 of the high logic level is applied, the gate-source voltage of the first pull-up transistor Tup_1 is changed to output the nth gate driving signal Vg (n) of the high logic level do.

Then, as the second start signal VST2 of the high logic level is input, the first thin film transistor T1_2 of the odd stage EVEN is turned on to charge the node Q2 to the high logic level, and the fifth thin film transistor T5_2 and the 9_2 th thin film transistor T9_2 are turned on so that the discharge states of the QB1 and 2_ODD nodes and the QB1 and 2_EVEN nodes are maintained. When the second clock signal CLK2 of the high logic level is applied, the gate-source voltage of the second pull-up transistor Tup_2 fluctuates and the (n + 1) th gate drive signal Vg (n + Is output. Here, the second start signal VST2 and the second clock signal CLK2 are delayed by one horizontal period (1H) period with the first start signal VST1 and the first clock signal CLK1, The nth gate driving signal Vg (n) and the (n + 1) th gate driving signal Vg (n + 1) are outputted so that the three horizontal periods 3H overlap each other .

(N + 5) from the (N + 2) th stage to the (n + 5) th gate driving signal Vg (T2_1), and the node Q1 can be discharged. At this time, since the even supply voltage VDD_O is in the high logic level state and the eighth transistor T8_1 is turned off, the seventh thin film transistor T7_1 is turned on to turn the QB1_ODD node to the good power supply voltage VDD_O Charging. Thus, the 11 &lt; 11 &gt; th thin film transistor T11_1 is turned on to transition the nth gate driving signal Vg (n) to a low logic level. Further, (Vg (n + 5)) is also applied to the second thin film transistor T2_2 as the next next stage signal Vnext, and the Q2 node can be discharged. At this time, since the ninth power source voltage VDD_E is in the high logic level state and the eighth transistor T8_2 is turned off, the seventh transistor T7_2 is turned on to turn the QB2_ODD node to the ninth power source voltage VDD_E Charging. Thus, the 11_2 th thin film transistor T11_2 is turned on to transition the (n + 1) th gate driving signal Vg (n + 1) to a low logic level. The 11th and 11th thin film transistors T11_1 and 2 and the 12th and 2th thin film transistors T12_1 and T23 are turned on and off at the turn-on and turn-off timings by the unipolar power supply voltage VDD_O and the radix power supply voltage VDD_E Is determined.

&Lt; Operation relationship between gate drive circuit and compensation circuit part >

9 is a circuit diagram showing the N stage of the gate driving circuit and the compensation circuit portion according to the embodiment of the present invention. And FIG. 10 is a waveform diagram showing an n-th gate driving signal of the N-th stage, an (n + 2) th gate driving signal, and a first clock signal and a fifth clock signal.

8, 9, and 10, when the first clock signal CLK1 becomes a high logic level, the Q1 node of the odd stage ODD is bootstrapped and the nth gate driving signal Vg (n) The first clock signal CLK1 is output to the gate terminal of the third thin film transistor Tc of the first compensator 501 constituting the compensation circuit unit 500 And the N-node is discharged to the low potential power source (VSS), the n-gate driving signal Vg (n) on the gate line is not discharged due to the turn-on of the first thin film transistor Ta by the partially charged voltage of the N-node When the fifth clock signal CLK5 supplied to the (N + 2) th stage transitions to the high logic level, the Q1 node of the (N + 2) stage is bootstrapped, And the (n + 4) -th gate driving signal Vg (n + 4) is output as the first compensation signal Vg The second thin film transistor Tb is turned on while being supplied to the gate terminal of the second thin film transistor Tb of the second thin film transistor Tb, The first thin film transistor Ta is turned on and the nth gate line GL n of the N stage is discharged while the signal CLK5 is supplied to the Nth node. Thus, the nth gate driving signal Vg (n) The second compensator 502 can shift the sixth clock signal CLK6 supplied to the (N + 2) th stage in the manner described in the first compensator 501 to the Nth (N + 5) of the second compensator 502 by the (n + 5) th gate drive signal Vg (n + 5) while being the (n + When the thin film transistor Tb is turned on and the sixth clock signal CLK6 of the high logic level is turned on by the first thin film transistor T a) is turned on so that the (n + 1) th gate line GL n + 1 of the N stage is discharged. Thus, the (n + 1) -th gate driving signal Vg (n + 1) can quickly change to the low potential power supply.

The relationship between the first clock signal (CLK) supplied to the Nth stage and the second clock signal (CLKB) supplied to the drain terminal of the second thin film transistor (Tb) included in the compensator connected to the Nth stage , The second clock signal (CLKB) maintains a low logic level when the first clock signal (CLK) becomes a high logic level, and when the first clock signal (CLK) transitions to a low logic level, 2 clock signal CLKB has a relationship of transitioning to a high logic level. The gate driving signal Vg is output through the timing of the clock signal, and then discharged rapidly at the time of discharging. In this case, the clock signal supplied to the gate terminal of the second thin film transistor Tb is not limited to the gate driving signal which becomes the high level logic in synchronization with the second clock signal CLKB at the high logic level, , A gate driving signal side (CLK) having a high logic level between a time period during which the first clock signal (CLK) becomes high logic and a time period (T) between a time period during which the second clock signal (CLKB) The compensation circuit unit 500 of the present invention can operate normally.

11 is a waveform diagram showing waveforms of gate drive signals in a conventional unipolar GIP structure and waveforms of gate drive signals in a unidirectional GIP and compensation circuit structure according to the embodiment. 12 is a graph comparing the holding voltage of a pixel through a voltage difference between a gate line end portion and a gate line end portion in a conventional unilateral GIP structure, and FIG. 13 is a graph showing the relationship between a unidirectional GIP and a compensation circuit structure And compares the holding voltage of the pixel with the voltage difference between the entrance of the gate line and the end of the gate line. Fig. 14 is a diagram showing a screen in which a large-sized display device is constituted by connecting display panels in which a bezel is reduced.

11, the polling time of the gate driving signal of the conventional unidirectional GIP is 2.49 us while the polling time of the gate driving signal outputted from the gate driving circuit 200 according to the embodiment is 1.75 us . 12 and 13, the gate drive circuit 200 and the compensation circuit unit 500 according to the embodiment of the present invention have a voltage difference of 188 mV between the entrance of the gate line and the end of the gate line in the conventional unilateral GIP structure, It can be seen that the voltage difference between the entrance of the gate line and the end of the gate line is reduced to 51 mV. The luminance difference between the left and right sides of the display panel 100 is reduced. As shown in FIG. 14, compared with the conventional FIG. 3, a bezel at a connection portion between a plurality of display panels 100 that divide and display one image according to the reduction of the bezel is reduced to display a large image Can be realized. That is, the compensation circuit portion 500 having only three transistors T1, Tb and T3 is required to have a narrow bezel compared to the GIP structure. By arranging the compensation circuit portion 500 on one side of the display panel 100, The bezel of the panel 100 can be reduced.

As described above, the gate driving circuit 200 and the display device including the gate driving circuit 200 according to the embodiment of the present invention have a delay characteristic when the waveform of the gate driving signal reaches from the entrance end to the end of the panel, It is possible to solve the problem that the polling time becomes long due to the delay of the gate driving signal Vg through the compensation circuit part 500 disposed at the end of the gate line GL, , The increase of the bezel of the large screen product can be solved at the same time by driving the unidirectional GIP, and the deviation of the signal delay of the left and right of the display panel 100 can be reduced to improve the image quality.

Meanwhile, in the embodiment of the present invention, instead of doubling the number of gate lines compared to the prior art, the number of data lines is reduced by a factor of 1/2 to reduce the number of data drive ICs required by half, Double Rate Driving) driving method.

FIG. 15 is a circuit diagram showing the Nth stage and the compensation circuit of the gate driving circuit according to the second embodiment, and FIG. 16 is a graph showing a gate output waveform according to the second embodiment.

Referring to FIG. 15, the display panel 100 according to the second embodiment of the present invention may include compensation circuit portions 501 and 502 disposed on the other side of the gate driving circuit. The gate driving circuit and the compensation circuit portions 501 and 502 may be connected through gate lines GLn and GLn + 1.

Each of the compensators 501 and 502 may include first to third thin film transistors Ta, Tb and Tc.

The first thin film transistor Ta is controlled by the voltage on the N-node, the drain terminal is connected to the gate line GL, and the source terminal is connected to the third low potential power supply VSS3, Level, the potential on the gate lines GLn and GLn + 1 can be lowered to the first low potential power source VSS1. The second thin film transistor Tb is operated by the gate driving signal Vg (m) on an arbitrary gate line G (m) and outputs an arbitrary clock signal CLKB on the drain terminal to the N source terminal N nodes can be provided. Therefore, when the gate drive signal Vg (m) on the arbitrary gate line G (m) is at the high logic level, the second thin film transistor Tb is turned on, and the arbitrary clock signal CLKB at that time is turned on. The voltage of the N-node may be a high logic level. The third thin film transistor Tc is operated by an arbitrary clock signal CLK and can function to vary the voltage on the N-node which is the drain terminal to the second low potential power supply VSS2 which is the source terminal.

The clock signal CLKB supplied to the drain terminal of the second thin film transistor Tb and the clock signal CLK supplied to the gate terminal of the third thin film transistor Tc may have opposite logic levels . The clock signal CLK supplied to the gate terminal of the third thin film transistor Tc is referred to as a first clock signal CLK and the clock signal CLK supplied to the drain terminal of the second thin film transistor Tb (CLKB) may be a second logic level when the first clock signal CLK is at a high logic level, if the second clock signal CLKB is a second clock signal CLKB. The first clock signal CLK is not fixed to the low logic level when the second clock signal CLKB is at the high logic level and the gate driving signal G (m) Vg (m)) is a low logic level, the first clock signal CLK may be a high logic level.

The gate driving signal outputted from the gate driving circuit turns on the TFT of the pixel 110 through the gate lines GLn and GLn + 1 so that the data signal on the data line DL is applied to the storage capacitor The compensation circuit unit 500 discharges the remaining gate driving signals on the gate lines GLn and GLn + 1 to charge the storage capacitor Cst to the storage capacitor Cst, And can be turned off at the time when the transistor TFT is required.

The compensation circuit according to the second embodiment can be constructed by using two low potential power sources having different voltages. And the second low potential power supply VSS2 may have about -15 V or so. The voltage value of the second low potential power supply VSS2 is not limited thereto. The third low potential power supply VSS3 may have a voltage of -6V to -13V and may have a voltage of about -7V. The voltage value of the third low potential power supply VSS3 is not limited thereto.

The third low potential power supply VSS3 may be formed to be larger than the second low potential power supply VSS2. The third low potential power supply VSS3 may be formed between the first low potential power supply VSS1 and the second low potential power supply VSS2. The voltage value of the first low potential power supply VSS1 may be -5 V, but is not limited thereto. The first low potential power supply VSS1 may be applied to the gate driver, but the second low potential power supply VSS2 may be applied. The third low potential power supply VSS3 can prevent ripple of the gate output.

16, when only the second low potential power supply VSS2 is connected to the compensation circuit portion as in the first embodiment, the voltage difference between the first low potential power supply VSS1 and the first low potential power supply VSS1 of the gate driving circuit, . Therefore, when the third low potential power supply VSS3 having the voltage value between the first low potential power supply VSS1 and the second low potential power supply VSS2 is applied to the compensation circuit as in the second embodiment, There is an effect that the ripple generated in the embodiment can be removed more effectively.

The first low potential power supply VSS1 may be used instead of the third low potential power supply VSS3 because the first low potential power supply VSS1 is larger than the voltage value of the second low potential power supply VSS2. The potential of the thin film transistor Ta can not be drawn quickly.

15, when the first clock signal CLK1 becomes the high logic level, the Q1 node of the odd stage ODD is bootstrapped and the nth gate driving signal The first clock signal CLK1 is output to the nth gate line GLn and the third thin film transistor Tc of the first compensator 501 constituting the compensation circuit unit 500, And the N-node is discharged to the second low-potential power supply VSS2. Therefore, the n-gate driving signal Vg (n) on the gate line due to the turn-on of the first thin film transistor Ta due to the partially charged voltage of the N- (n) is not discharged. When the fifth clock signal CLK5 supplied to the (N + 2) th stage transitions to the high logic level, the Q1 node of the (N + 2) stage is bootstrapped and the (n + And the n + 4th gate driving signal Vg (n + 4) is supplied to the gate terminal of the second thin film transistor Tb of the first compensator 501, The second thin film transistor Tb is turned on and the fifth thin film transistor Ta is supplied with the fifth clock signal CLK5 of high logic level supplied to the drain terminal of the second thin film transistor Tb to the Nth node, Is turned on and the nth gate line GL n of the Nth stage is discharged. Thus, the n-th gate driving signal Vg (n) can quickly transit to the second low potential power supply VSS2. The second compensator 502 receives the (n + 5) -th gate drive signal of the (N + 2) -th stage from the sixth clock signal CLK6 supplied to the (N + 2) The second thin film transistor Tb of the second compensator 502 is turned on by the (n + 5) th gate driving signal Vg (n + 5) The sixth clock signal CLK6 of the logic level turns on the first thin film transistor Ta of the second compensator 502 and the n + 1th gate line GL n + 1 of the Nth stage discharges . Thus, the (n + 1) -th gate driving signal Vg (n + 1) can quickly shift to the third low potential power supply VSS3.

The relationship between the first clock signal (CLK) supplied to the Nth stage and the second clock signal (CLKB) supplied to the drain terminal of the second thin film transistor (Tb) included in the compensator connected to the Nth stage , The second clock signal (CLKB) maintains a low logic level when the first clock signal (CLK) becomes a high logic level, and when the first clock signal (CLK) transitions to a low logic level, 2 clock signal CLKB has a relationship of transitioning to a high logic level. The gate driving signal Vg is output through the timing of the clock signal, and then discharged rapidly at the time of discharging. In this case, the clock signal supplied to the gate terminal of the second thin film transistor Tb is not limited to the gate driving signal which becomes the high level logic in synchronization with the second clock signal CLKB at the high logic level, , A gate driving signal side (CLK) having a high logic level between a time period during which the first clock signal (CLK) becomes high logic and a time period (T) between a time period during which the second clock signal (CLKB) The compensation circuit unit 500 of the present invention can operate normally.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10 Conventional liquid crystal display panel
100 display panel
110 pixels
200 gate drive circuit
210 Shift registers
300 data drive circuit
400 timing controller
500 compensation circuit portion
501 first compensation unit
502 Second compensator

Claims (14)

A shift register including an N-th stage connected to one end of a gate line; And
And a compensation circuit part connected to the other end of the gate line,
Wherein the N stage is controlled by a voltage of a Q node to output a first clock signal as a first gate driving signal,
Wherein the compensation circuit part is controlled by a second gate driving signal output by a next stage of the Nth stage to discharge the first gate driving signal. The method according to claim 1,
Wherein the second clock signal transitions from a low logic level to a high logic level when the first clock signal transitions from a high logic level to a low logic level. 3. The method of claim 2,
Wherein the second gate driving signal has a high logic level between a time interval in which the first clock signal maintains a high logic level and a time interval in which the second clock signal maintains a high logic level. The method according to claim 1,
Wherein the compensation circuit section comprises:
A first transistor including a first transistor and a second transistor,
Wherein the first transistor is controlled by a voltage on an N-node to supply a third low potential power to the gate line,
And the second transistor is controlled by the second gate driving signal to supply the second clock signal to the N-node. 5. The method of claim 4,
Wherein the compensation circuit section comprises:
Further comprising a third transistor,
And the third transistor is controlled by the first clock signal to supply the second low potential power to the N-node. 6. The method of claim 5,
And the voltage value of the third low potential power supply is larger than the voltage value of the second low potential power supply. The method according to claim 6,
Wherein the gate driving circuit further comprises a first low potential power supply, and the third low potential power supply has a voltage value between the first low potential power supply and the second low potential power supply. 8. The method of claim 7,
And the third low potential power source is a gate drive circuit having -6V to -13V. A gate driving circuit according to claim 1; And
And a display panel in which the shift register is disposed on one side and the compensation circuit section is disposed on the other side. 10. The method of claim 9,
Wherein the second clock signal transitions from a low logic level to a high logic level when the first clock signal transitions from a high logic level to a low logic level. 11. The method of claim 10,
Wherein the second gate driving signal has a high logic level between a time interval in which the first clock signal maintains a high logic level and a time interval in which the second clock signal maintains a high logic level. 10. The method of claim 9,
Wherein the compensation circuit section comprises:
A first transistor including a first transistor and a second transistor,
Wherein the first transistor is controlled by a voltage on an N-node to supply a third low potential power to the gate line,
And the second transistor is controlled by the second gate driving signal to supply the second clock signal to the N-node. 13. The method of claim 12,
Wherein the compensation circuit section comprises:
Further comprising a third transistor,
And the third transistor is controlled by the first clock signal to supply the second low potential power to the N-node. 10. The method of claim 9,
A plurality of display panels are provided,
Wherein the display panel divides and displays one image.

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