KR20150142741A - Light emitting device and lighting system - Google Patents

Abstract

Embodiments relate to a light emitting device, a method of manufacturing a light emitting device, a light emitting device package, and an illumination system.
A light emitting device according to an embodiment includes a first conductive semiconductor layer; A second conductive semiconductor layer disposed under the first conductive semiconductor layer; An active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer; A plurality of holes exposing a part of the second conductivity type semiconductor layer and the first conductivity type semiconductor layer of the active layer layered layer from a bottom surface of the second conductivity type semiconductor layer; A first contact electrode electrically connected to the first conductivity type semiconductor layer from the bottom surface of the second conductivity type semiconductor layer through the plurality of holes; A first ion implantation region of the first conductivity type semiconductor layer above the first contact electrode; A first electrode layer electrically connected to the insulating layer layer electrode disposed between the first contact electrode and the plurality of holes; And a second contact electrode connected to the second conductive semiconductor layer layer.

Description

[0001] LIGHT EMITTING DEVICE AND LIGHTING SYSTEM [0002]

Embodiments relate to a light emitting device, a method of manufacturing a light emitting device, a light emitting device package, and an illumination system.

Light Emitting Device is a pn junction diode whose electrical energy is converted into light energy. It can be produced from compound semiconductor such as group III and group V on the periodic table and by controlling the composition ratio of compound semiconductor, It is possible.

When a forward voltage is applied to the light emitting device, electrons in the n-layer and holes in the p-layer are coupled to emit energy corresponding to the band gap energy of the conduction band and the valance band. Is mainly emitted in the form of heat or light, and when emitted in the form of light, becomes a light emitting element.

For example, nitride semiconductors have received great interest in the development of optical devices and high power electronic devices due to their high thermal stability and wide bandgap energy. Particularly, blue light emitting devices, green light emitting devices, ultraviolet (UV) light emitting devices, and the like using nitride semiconductors have been commercialized and widely used.

There is a lateral type light emitting device in which an electrode layer is arranged in one direction of an epilayer in a light emitting device according to the prior art. Such a horizontal type light emitting device has a problem that the operating voltage VF ) Is increased, the current efficiency is lowered, and there is a problem that it is vulnerable to electrostatic discharge.

In order to solve such a problem, a conventional via hole type vertical light emitting device in which a via hole is formed under the epi layer and an electrode is disposed has been developed.

In order to manufacture a via-hole type vertical light emitting device in the prior art, a plurality of mesa etching processes for an n-contact are performed and insulation between an n-contact and a mesa etching hole Layer.

Meanwhile, according to the related art, a plurality of mesa etching processes for n-contact are performed in order to fabricate a via-hole type vertical light emitting device, and there is a problem that the VF increases depending on the N-contact region.

In addition, according to the related art, electrons injected through a via hole cause electron clouding around a via hole, electrons flow mainly around a via hole, and light is generated only in a part of the active layer, have.

Embodiments provide a light emitting device having improved electrical characteristics, a method of manufacturing a light emitting device, a light emitting device package, and an illumination system.

Also, according to the embodiments, there is provided a light emitting device, a method of manufacturing a light emitting device, a light emitting device package, and an illumination system having improved light emitting efficiency by improving carrier injection efficiency.

The light emitting device according to the embodiment includes a first conductive semiconductor layer 112; A second conductive semiconductor layer (116) disposed under the first conductive semiconductor layer (112); An active layer 114 disposed between the first conductive semiconductor layer 112 and the second conductive semiconductor layer 116; The second conductivity type semiconductor layer 116 and the second conductivity type semiconductor layer 116. The second conductivity type semiconductor layer 116 may include a plurality of holes (H); A first contact electrode (160) electrically connected to the first conductive type semiconductor layer (112) through the plurality of holes (H) from a bottom surface of the second conductive type semiconductor layer (116); A first ion implantation region 191 disposed on the first conductivity type semiconductor layer 112 on the first contact electrode 160; An insulating layer 140 disposed between the first contact electrode 160 and the plurality of holes H; A first electrode layer 150 electrically connected to the first contact electrode 160; And a second contact electrode 132 electrically connected to the second conductive type semiconductor layer 116.

 The illumination system according to the embodiment may include a light emitting unit having the light emitting element.

According to embodiments, a light emitting device having improved electrical characteristics, a method of manufacturing a light emitting device, a light emitting device package, and an illumination system can be provided.

Further, according to the embodiment, it is possible to provide a light emitting device, a method of manufacturing a light emitting device, a light emitting device package, and an illumination system in which the light emitting efficiency is improved by improving the carrier injection efficiency.

1 is a planar projection view of a light emitting device according to an embodiment.
2A is a partially enlarged cross-sectional view of a light emitting device according to an embodiment;
2B is a partially enlarged cross-sectional view of a light emitting device according to another embodiment.
3 to 11 are process sectional views of a method of manufacturing a light emitting device according to an embodiment.
12 is a sectional view of a light emitting device package according to an embodiment.
13 is an exploded perspective view of a lighting apparatus according to an embodiment.

In the description of the embodiments, each layer (film), region, pattern or structure is referred to as being "on" or "under" the substrate, each layer (film) Quot; on "and" under "are intended to include both" directly "or" indirectly " do. Also, the criteria for top, bottom, or bottom of each layer will be described with reference to the drawings.

(Example)

FIG. 1 is a plan view of a light emitting device 100 according to an embodiment, and FIGS. 2A and 2B are enlarged cross-sectional views taken along line A-A 'of FIG.

The light emitting device 100 according to the embodiment includes a first conductive semiconductor layer 112, a second conductive semiconductor layer 116 disposed under the first conductive semiconductor layer 112, The active layer 114 is disposed between the first conductivity type semiconductor layer 112 and the second conductivity type semiconductor layer 116 and the second conductivity type semiconductor layer 116 is formed from the bottom surface of the second conductivity type semiconductor layer 116, A plurality of holes H extending through the active layer 114 to expose a part of the first conductivity type semiconductor layer 112 and a plurality of holes H extending from the bottom of the second conductivity type semiconductor layer 116, A first contact electrode 160 electrically connected to the first conductivity type semiconductor layer 112 through the first contact electrode 160 and a second contact electrode 160 electrically connected to the first conductivity type semiconductor layer 112 on the first contact electrode 160, An insulating layer 140 disposed between the first contact electrode 160 and the plurality of holes H and a second contact electrode 160 electrically connected to the first contact electrode 160 1, electrode layer 150 and the first may include a second conductive type semiconductor layer 116 and electrically contacts the second electrode 132 connected to the.

The first ion implantation region 191 may be implanted with the first conductivity type ions. For example, when the first conductivity type ion is an n-type ion, a Group 5 element such as Si is ion-implanted to reduce the resistance with the first contact electrode 160 to lower the VF, thereby improving the electrical characteristics .

In addition, according to the embodiment, the horizontal width of the first ion-implanted region 191 is wider than the horizontal width of the first contact electrode 160, so that the contact resistance can be reduced and the electrical characteristics can be improved.

In addition, according to the embodiment, as shown in FIG. 2B, the first contact electrode 160 may further include a second ion implantation region 192 formed on the first conductivity type semiconductor layer 112 on both sides of the first contact electrode 160. According to the embodiment, the ion implantation is also performed on the side surfaces of the plurality of holes during the ion implantation to form the second ion implantation region 192 to spread the carrier, thereby enhancing the carrier injection efficiency and increasing the light flux .

Thus, according to the embodiment, it is possible to provide the light emitting area in which the light flux is improved by improving the carrier injection efficiency.

Hereinafter, a method of manufacturing a light emitting device according to an embodiment will be described with reference to FIGS. 3 to 11, and the features of the present invention will be described in detail. 2A for the first ion implanted region 191 in the description of the manufacturing method, but the embodiment is not limited thereto.

First, the light emitting structure layer 110 may be formed on the growth substrate 105 as shown in FIG. The light emitting structure layer 110 may include a first conductive semiconductor layer 112, an active layer 114, and a second conductive semiconductor layer 116.

The growth substrate 105 may be loaded into the growth equipment, and formed thereon in the form of a layer or a pattern using a compound semiconductor of group II to VI elements.

The growth equipment may be an electron beam evaporator, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual-type thermal evaporator sputtering, metal organic chemical vapor deposition, etc. may be employed and are not limited to such equipment.

The growth substrate 105 may be a conductive substrate, an insulating substrate, or the like. For example, the growth substrate 105 may be selected from the group consisting of a sapphire substrate (Al ₂ O ₃ ), GaN, SiC, ZnO, Si, GaP, InP, Ga ₂ O ₃ , and GaAs.

A buffer layer (not shown) may be formed on the growth substrate 105. The buffer layer reduces the difference in lattice constant between the growth substrate 105 and the nitride semiconductor layer. The material of the buffer layer may be GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP ≪ / RTI >

An undoped semiconductor layer (not shown) may be formed on the buffer layer. The undoped semiconductor layer may be formed of a GaN-based semiconductor that is not doped, and may be formed of a semiconductor layer that is lower in conductivity than the n- .

Thereafter, the first conductive semiconductor layer 112 is formed on the buffer layer or the on-state semiconductor layer. An active layer 114 may be formed on the first conductive semiconductor layer 112 and a second conductive semiconductor layer 116 may be sequentially stacked on the active layer 114.

Other layers may be further disposed on or under the respective semiconductor layers. For example, the semiconductor layer may be formed in a superlattice structure using a Group III-V compound semiconductor layer, but the present invention is not limited thereto.

The first conductive semiconductor layer 112 may be a compound semiconductor of a group III-V element doped with a first conductive dopant, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, and the like. For example, the first conductive semiconductor layer 112 may have a composition formula of In _x Al _y Ga _{1 -x- y} N (0? X? 1, 0? _Y? 1, 0? _X + As shown in Fig.

The first conductive semiconductor layer 112 may be an n-type semiconductor layer, and the first conductive dopant may include n-type dopants such as Si, Ge, Sn, Se, and Te.

The first conductive semiconductor layer 112 may be formed as a single layer or a multilayer and may alternate between two layers of GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, Lt; RTI ID = 0.0 > lattice < / RTI >

The active layer 114 may include a single quantum well structure, a multiple quantum well structure, a quantum wire structure, or a quantum dot structure. The active layer 114 may be formed with a period of a well layer and a barrier layer using a compound semiconductor material of group III-V elements. _Wherein the well layer comprises a semiconductor layer having a composition formula of In _x Al _y Ga _{1 -x- y} N (0? X? 1, 0? _Y? 1, 0? _X + y? 1) _X , y, and _{l, respectively, of the} In _x Al _y Ga _{1 -x- y} N (0? X? 1, 0? _Y ? The barrier layer may be formed of a material having a band gap higher than the band gap of the well layer.

The active layer 114 may include at least one period of, for example, the period of the InGaN well layer / GaN barrier layer, the period of the InGaN well layer / AlGaN barrier layer, and the period of the InGaN well layer / InGaN barrier layer .

The second conductivity type semiconductor layer 116 is formed on the active layer 114 and the second conductivity type semiconductor layer 116 is a compound semiconductor of a group III-V element doped with the second conductivity type dopant, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP and the like. The second conductive semiconductor layer 116 is formed of a semiconductor layer having a composition formula of In _x Al _y Ga _1-xy N (0? X? 1, 0? _Y? 1, 0? _X + y? .

The second conductive semiconductor layer 116 may be a p-type semiconductor layer, and the second conductive dopant may include a p-type dopant such as Mg, Zn, or the like. The second conductive semiconductor layer 116 may be formed as a single layer or a multilayer, but is not limited thereto.

The second conductive semiconductor layer 116 may include a superlattice structure in which two different layers of GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, and AlGaInP are alternately arranged .

The first conductive semiconductor layer 112, the active layer 114, and the second conductive semiconductor layer 116 may be defined as a light emitting structure layer 110. A third conductive semiconductor layer (not shown), for example, a semiconductor layer having a polarity opposite to that of the second conductive type may be formed on the second conductive semiconductor layer 116.

Accordingly, the light emitting structure layer 110 may include at least one of an n-p junction, a p-n junction, an n-p-n junction, and a p-n-p junction structure. In the following description, the structure in which the second conductivity type semiconductor layer 116 is disposed on the uppermost layer of the light emitting structure layer 110 will be described as an example.

Next, as shown in FIG. 4, a mesa etching process for removing a part of the light emitting structure may be performed.

For example, a plurality of holes H may be formed through the second conductive semiconductor layer 116 and the active layer 114 to expose a portion of the first conductive semiconductor layer 112.

The plurality of holes H may be formed at a predetermined angle from the first conductivity type semiconductor layer 112 to the top surface of the second conductivity type semiconductor layer 116, May be formed at an obtuse angle.

In the embodiment, the horizontal width of the plurality of holes H may be reduced toward the lower side. 2A, the horizontal width of the plurality of holes H may decrease toward the upper side.

2A, the active layer 114 and the first conductivity type semiconductor layer 112 are removed by decreasing the horizontal width of the plurality of holes H toward the upper side, . ≪ / RTI >

The first ion implantation region 191 may be formed in the first conductive semiconductor layer 112 exposed by the plurality of holes H. [

The first ion implantation region 191 may be implanted with the first conductivity type ions. For example, when the first conductivity type ion is an n-type ion, a Group 5 element such as Si is ion-implanted to reduce the resistance with the first contact electrode 160 to lower the VF, thereby improving the electrical characteristics .

As the ion implantation source, an arc discharge, a high frequency type, a double plasmatron, a cold cathode type, and the like can be used. As the ion to be implanted, a Group 5 element such as Si, C, Ge and the like can be used.

After the ion implantation, annealing may be performed at a predetermined temperature.

According to the embodiment, since the horizontal width of the first ion-implanted region 191 is larger than the horizontal width of the first contact electrode 160, the contact resistance can be reduced and the electrical characteristics can be improved.

In addition, according to the embodiment, as shown in FIG. 2B, the first contact electrode 160 may further include a second ion implantation region 192 formed on the first conductivity type semiconductor layer 112 on both sides of the first contact electrode 160. According to the embodiment, the ion implantation is also performed on the side surfaces of the plurality of holes during the ion implantation to form the second ion implantation region 192 to spread the carrier, thereby enhancing the carrier injection efficiency and increasing the light flux .

Thus, according to the embodiment, it is possible to provide a light emitting device in which the light emitting efficiency is improved and the light flux is improved.

Next, as shown in FIG. 5, the channel layer 120 may be formed on the plurality of holes H. FIG. The channel layer 120 may not be formed in a region where the first contact electrode 160 to be formed later is to be formed. Thus, a part of the first conductive type semiconductor layer 112 can be exposed.

The channel layer 120 may serve as an electrical insulating layer between the first contact electrode 160, the active layer 114, and the second conductive semiconductor layer 116, which will be formed later.

The channel layer 120 may be formed of one or more materials selected from SiO _x , SiO _x N _y , Al ₂ O ₃ , and TiO ₂ .

Also, in an embodiment, the channel layer 120 may have a reflectivity greater than 50%. For example, the channel layer 120 may be formed of a material selected from SiO ₂ , SiO _x , SiO _x N _y , Si ₃ N ₄ , Al ₂ O ₃ , TiO ₂ , And may be formed in a mixed form.

For example, the channel layer 120 may be formed of a mixture of at least one of Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au, .

According to the embodiment, when the emitted light returns to the lower side, the light is also reflected from the channel layer 120, thereby minimizing the light absorption and increasing the light efficiency.

Next, a second contact electrode 132 may be formed on the second conductive type semiconductor layer 116.

The second contact electrode 132 is in ohmic contact with the second conductive semiconductor layer 116 and includes at least one conductive material, and may be a single layer or a multi-layer structure.

For example, the second contact electrode 132 may include at least one of a metal, a metal oxide, and a metal nitride material.

The second contact electrode 132 includes a transparent material such as ITO (indium tin oxide), IZO (indium zinc oxide), IZON (indium zinc nitride), IZTO (indium zinc tin oxide), IAZO zinc oxide (IGZO), indium gallium tin oxide (IGTO), aluminum zinc oxide (AZO), antimony tin oxide (ATO), gallium zinc oxide (GZO), IrOx, RuOx, RuOx / / IrOx / Au, Ni / IrOx / Au / ITO, Pt, Ni, Au, Rh or Pd.

Next, a reflective layer 134 may be formed on the second contact electrode 132.

The reflective layer 134 is disposed on the second contact electrode 132 and may reflect light incident through the second contact electrode 132.

The reflective layer 134 may include one or more layers of materials selected from the group consisting of Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au, Hf, Layer.

Next, a capping layer 136 may be formed on the reflective layer 134. The second electrode layer 130 may include a second contact electrode 132, a reflective layer 134 and a capping layer 136. The second electrode layer 130 may be referred to as a power source Can be supplied to the second conductivity type semiconductor layer (116).

The capping layer 136 may be disposed on the reflective layer 134 and may supply power to the reflective layer 134 from the pad electrode 180. The capping layer 136 may function as a current diffusion layer.

The capping layer 136 may be made of a material having high electrical conductivity such as Sn, Ga, In, Bi, Cu, Ni, Ag, Mo, Al, Au, Nb, W, Ti, Al, Pd, Pt, Si and an optional alloy thereof.

Next, as shown in FIG. 6, an insulating layer 140 may be formed on the capping layer 136 and the channel layer 120.

The insulating layer 140 may be formed to expose the first contact electrode 160.

The insulating layer 140 electrically isolates the first contact electrode 160 from the other semiconductor layer.

The insulating layer 140 may be disposed between the first electrode layer 150 and the channel layer 120 to prevent electrical contact.

The insulating layer 140 may be formed of a material selected from SiO ₂ , SiO _x , SiO _x N _y , Si ₃ N ₄ , Al ₂ O ₃ , and TiO ₂ .

The insulating layer 140 may have a reflectance of more than 50%. For example, the insulating layer 140 may be formed of a material selected from SiO ₂ , SiO _x , SiO _x N _y , Si ₃ N ₄ , Al ₂ O ₃ , TiO ₂ , And may be formed in a mixed form.

For example, one or more of Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au or Hf may be mixed with the insulating layer 140 .

The insulating layer 140 formed between the first contact electrode 160 and the plurality of holes H may be formed of a reflective layer material so that light absorption in the insulating layer 140 that functions as a passivation layer So that the light efficiency can be increased.

Next, a first contact electrode 160 may be formed on the exposed first conductive semiconductor layer 112.

The first contact electrode 160 may be in ohmic contact with the exposed first conductive semiconductor layer 112. The first contact electrode 160 may have a circular or polygonal shape when viewed from above, but is not limited thereto.

The upper surface of the first contact electrode 160 may be disposed between the upper surface of the active layer 114 and the upper surface of the first conductive semiconductor layer 112.

The surface of the first conductivity type semiconductor layer 112 to which the first contact electrode 160 contacts is a Ga-face, and may be formed in a flat structure, but is not limited thereto.

Referring to FIG. 6, in the embodiment, the width of the first contact electrode 160 may increase from the bottom surface to the top surface. On the other hand, the width of the first contact electrode 160 can be reduced from the top surface to the bottom surface with reference to FIG.

As a result, the possibility that the first contact electrode 160 is short-circuited with the second electrode layer 130, which is formed later, is lowered, and the region in which the first contact electrode 160 contacts the first conductive semiconductor layer 112 is maximized The area occupied by the first contact electrode 160 can be reduced and the light efficiency can be increased.

2A, the horizontal width of the bottom surface of the first contact electrode 160 and the horizontal width of the diffusion preventing layer 154 in contact with the first contact electrode 160 coincide with each other, The first contact electrode 160 and the second contact electrode 154 may be minimized, but the electrical characteristics may not be deteriorated.

A first ion implantation region 191 may be formed in the first conductive semiconductor layer 112 which overlaps with the first contact electrode 160 to reduce the resistance with the first contact electrode 160, By lowering the VF, the electrical characteristics can be improved.

In addition, according to the embodiment, the horizontal width of the first ion-implanted region 191 is wider than the horizontal width of the first contact electrode 160, so that the contact resistance can be reduced and the electrical characteristics can be improved.

2B, a second ion implantation region 192 is formed on the first conductivity type semiconductor layer 112 on both sides of the first contact electrode 160 to spread the carriers. The carrier injection efficiency can be improved and the light flux can be increased.

7, a diffusion preventing layer 154 is formed on the insulating layer 140 and the first contact electrode 160, and a bonding layer 156 is formed on the diffusion preventing layer 154 .

The diffusion preventing layer 154 or the bonding layer 156 may include at least one of Ti, Au, Sn, Ni, Cr, Ga, In, Bi, Cu,

The diffusion preventing layer 154 or the bonding layer 156 may be formed of at least one of a deposition method, a sputtering method, and a plating method, or may be attached with a conductive sheet.

The bonding layer 156 may not be formed, but the bonding layer 156 is not limited thereto.

Next, a supporting member 158 may be formed on the bonding layer 156 as shown in FIG.

The first electrode layer 150 may be referred to as a first electrode layer 150 including the diffusion preventing layer 154, the bonding layer 156 and the supporting member 158. The first electrode layer 150 may be referred to as a power supply 1 conductivity type semiconductor layer 112. In addition,

The support member 158 may be bonded to the bonding layer 156, but is not limited thereto.

The support member 158 may be a conductive support member and may be formed of at least one of copper (Cu), gold (Au), nickel (Ni), molybdenum (Mo), copper-tungsten It can be one.

The support member 158 may be formed of a carrier wafer (e.g., Si, Ge, GaAs, ZnO, SiC, SiGe, Ga ₂ O ₃ , GaN or the like) As shown in Fig.

Next, as shown in FIG. 9, the growth substrate 105 can be removed. At this time, the surface of the first conductivity type semiconductor layer 112 may be exposed by removing the remaining undoped semiconductor layer (not shown) after removing the growth substrate 105.

The growth substrate 105 may be removed by physical and / or chemical methods. For example, the method of removing the growth substrate 105 may be removed by a laser lift off (LLO) process. For example, the growth substrate 105 is lifted off by irradiating the growth substrate 105 with a laser having a wavelength in a predetermined region.

Alternatively, a buffer layer (not shown) disposed between the growth substrate 105 and the first conductive type semiconductor layer 112 may be removed using a wet etching solution to separate the growth substrate 105.

The upper surface of the first conductivity type semiconductor layer 112 may be exposed by removing the growth substrate 105 and etching or polishing the buffer layer.

The upper surface of the first conductive semiconductor layer 112 may be an N-face, which is closer to the growth substrate.

The upper surface of the first conductive semiconductor layer 112 may be etched by an ICP / RIE (Inductively Coupled Plasma / Reactive Ion Etching) method or may be polished by a polishing apparatus.

Next, as shown in FIG. 10, a part of the light emitting structure layer 110 may be removed and a part of the channel layer 120 may be exposed.

For example, portions of the first conductivity type semiconductor layer 112, the active layer 114, and the second conductivity type semiconductor layer 116 in the region where the pad electrode 180 is to be formed may be removed.

For example, wet etching or dry etching may be performed to remove the periphery of the light emitting structure layer 110, that is, the channel region or the isolation region, which is a boundary region between the chip and the chip, .

The upper surface of the first conductive semiconductor layer 112 may have a light extracting structure, and the light extracting structure may be formed of a roughness or a pattern. The light extracting structure may be formed by a wet or dry etching method.

Next, as shown in FIG. 11, a passivation layer 170 may be formed on the exposed channel layer 120 and the light emitting structure layer 110.

A portion of the capping layer 136 may be exposed by removing a part of the passivation layer 170 and the channel layer 120 in the region where the pad electrode 180 is to be formed.

Next, the pad electrode 180 may be formed on the exposed capping layer 136.

The pad electrode 180 may be formed of Ti / Au or the like, but is not limited thereto.

The pad electrode 180 is a portion to be bonded with a wire and may be disposed on a predetermined portion of the light emitting structure layer 110 and may be formed of one or more.

2A, a first electrode 159 may be formed under the first electrode layer 150. The first electrode 159 may be formed of a material having high conductivity, such as Ti, Al, Ni, etc. Materials may be employed, but are not limited thereto.

According to embodiments, a light emitting device having improved electrical characteristics, a method of manufacturing a light emitting device, a light emitting device package, and an illumination system can be provided.

Further, according to the embodiment, it is possible to provide a light emitting device, a method of manufacturing a light emitting device, a light emitting device package, and an illumination system in which the light emitting efficiency is improved by improving the carrier injection efficiency.

12 is a view illustrating a light emitting device package to which the light emitting device according to the embodiment is applied.

12, a light emitting device package according to an embodiment includes a body 205, a first lead electrode 213 and a second lead electrode 214 disposed on the body 205, a body 205, And a molding member 240 surrounding the light emitting device 100. The light emitting device 100 may include a light emitting device 100 that is provided on the first lead electrode 213 and the second lead electrode 214 and is electrically connected to the first lead electrode 213 and the second lead electrode 214, .

The body 205 may be formed of a silicon material, a synthetic resin material, or a metal material, and an inclined surface may be formed around the light emitting device 100.

The first lead electrode 213 and the second lead electrode 214 are electrically isolated from each other and provide power to the light emitting device 100. [ The first lead electrode 213 and the second lead electrode 214 may increase the light efficiency by reflecting the light generated from the light emitting device 100. The heat generated from the light emitting device 100 To the outside.

The light emitting device 100 may be disposed on the body 205 or may be disposed on the first lead electrode 213 or the second lead electrode 214.

The light emitting device 100 may be electrically connected to the first lead electrode 213 and the second lead electrode 214 by a wire, flip chip, or die bonding method.

The light emitting device 100 may be mounted on the second lead electrode 214 and connected to the first lead electrode 213 by the wire 250. However, the embodiment is not limited thereto.

The molding member 240 surrounds the light emitting device 100 to protect the light emitting device 100. In addition, the molding member 240 may include a phosphor 232 to change the wavelength of light emitted from the light emitting device 100.

A plurality of light emitting devices or light emitting device packages according to the embodiments may be arrayed on a substrate, and a lens, a light guide plate, a prism sheet, a diffusion sheet, etc., which are optical members, may be disposed on the light path of the light emitting device package. Such a light emitting device package, a substrate, and an optical member can function as a light unit. The light unit may be implemented as a top view or a side view type and may be provided in a display device such as a portable terminal and a notebook computer, or may be variously applied to a lighting device and a pointing device. Still another embodiment may be embodied as a lighting device including the light emitting device or the light emitting device package described in the above embodiments. For example, the lighting device may include a lamp, a streetlight, an electric signboard, and a headlight.

13 is an exploded perspective view of a lighting apparatus according to an embodiment.

13, the lighting apparatus according to the embodiment includes a cover 2100, a light source module 2200, a heat discharger 2400, a power supply unit 2600, an inner case 2700, and a socket 2800 . Further, the illumination device according to the embodiment may further include at least one of the member 2300 and the holder 2500. The light source module 2200 may include a light emitting device package according to an embodiment.

For example, the cover 2100 may have a shape of a bulb or a hemisphere, and may be provided in a shape in which the hollow is hollow and a part is opened. The cover 2100 may be optically coupled to the light source module 2200. For example, the cover 2100 may diffuse, scatter, or excite light provided from the light source module 2200. The cover 2100 may be a kind of optical member. The cover 2100 may be coupled to the heat discharging body 2400. The cover 2100 may have an engaging portion that engages with the heat discharging body 2400.

The inner surface of the cover 2100 may be coated with a milky white paint. Milky white paints may contain a diffusing agent to diffuse light. The surface roughness of the inner surface of the cover 2100 may be larger than the surface roughness of the outer surface of the cover 2100. This is for sufficiently diffusing and diffusing the light from the light source module 2200 and emitting it to the outside.

The cover 2100 may be made of glass, plastic, polypropylene (PP), polyethylene (PE), polycarbonate (PC), or the like. Here, polycarbonate is excellent in light resistance, heat resistance and strength. The cover 2100 may be transparent so that the light source module 2200 is visible from the outside, and may be opaque. The cover 2100 may be formed by blow molding.

The light source module 2200 may be disposed on one side of the heat discharging body 2400. Accordingly, heat from the light source module 2200 is conducted to the heat discharger 2400. The light source module 2200 may include a light source unit 2210, a connection plate 2230, and a connector 2250.

The member 2300 is disposed on the upper surface of the heat discharging body 2400 and has guide grooves 2310 through which the plurality of light source portions 2210 and the connector 2250 are inserted. The guide groove 2310 corresponds to the substrate of the light source unit 2210 and the connector 2250.

The surface of the member 2300 may be coated or coated with a light reflecting material. For example, the surface of the member 2300 may be coated or coated with a white paint. The member 2300 reflects the light reflected by the inner surface of the cover 2100 toward the cover 2100 in the direction toward the light source module 2200. Therefore, the light efficiency of the illumination device according to the embodiment can be improved.

The member 2300 may be made of an insulating material, for example. The connection plate 2230 of the light source module 2200 may include an electrically conductive material. Therefore, electrical contact can be made between the heat discharging body 2400 and the connecting plate 2230. The member 2300 may be formed of an insulating material to prevent an electrical short circuit between the connection plate 2230 and the heat discharging body 2400. The heat discharger 2400 receives heat from the light source module 2200 and heat from the power supply unit 2600 to dissipate heat.

The holder 2500 blocks the receiving groove 2719 of the insulating portion 2710 of the inner case 2700. Therefore, the power supply unit 2600 housed in the insulating portion 2710 of the inner case 2700 is sealed. The holder 2500 has a guide protrusion 2510. The guide protrusion 2510 has a hole through which the protrusion 2610 of the power supply unit 2600 passes.

The power supply unit 2600 processes or converts an electrical signal provided from the outside and provides the electrical signal to the light source module 2200. The power supply unit 2600 is housed in the receiving groove 2719 of the inner case 2700 and is sealed inside the inner case 2700 by the holder 2500.

The power supply unit 2600 may include a protrusion 2610, a guide 2630, a base 2650, and an extension 2670.

The guide portion 2630 has a shape protruding outward from one side of the base 2650. The guide portion 2630 may be inserted into the holder 2500. A plurality of components may be disposed on one side of the base 2650. The plurality of components include, for example, a DC converter for converting AC power supplied from an external power source into DC power, a driving chip for controlling driving of the light source module 2200, an ESD (ElectroStatic discharge) protective device, and the like, but the present invention is not limited thereto.

The extension portion 2670 has a shape protruding outward from the other side of the base 2650. The extension portion 2670 is inserted into the connection portion 2750 of the inner case 2700 and receives an external electrical signal. For example, the extension portion 2670 may be provided to be equal to or smaller than the width of the connection portion 2750 of the inner case 2700. One end of each of the positive wire and the negative wire is electrically connected to the extension portion 2670 and the other end of the positive wire and the negative wire are electrically connected to the socket 2800 .

The inner case 2700 may include a molding part together with the power supply part 2600. The molding part is a hardened portion of the molding liquid so that the power supply unit 2600 can be fixed inside the inner case 2700.

The features, structures, effects and the like described in the embodiments are included in at least one embodiment and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects and the like illustrated in the embodiments can be combined and modified by other persons skilled in the art to which the embodiments belong. Accordingly, the contents of such combinations and modifications should be construed as being included in the scope of the embodiments.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. It can be seen that the modification and application of branches are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that the present invention may be embodied in many other specific forms without departing from the spirit or essential characteristics thereof.

The first conductive semiconductor layer 112, the second conductive semiconductor layer 116, the active layer 114,
A plurality of holes H, a first contact electrode 160, an insulating layer 140,
The bonding layer 156, the supporting member 158, the second contact electrode 132,
The first ion implantation region 191, the second ion implantation region 192,

Claims (10)

A first conductive semiconductor layer;
A second conductive semiconductor layer disposed under the first conductive semiconductor layer;
An active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer;
A plurality of holes penetrating the second conductivity type semiconductor layer and the active layer from the bottom surface of the second conductivity type semiconductor layer to expose a part of the first conductivity type semiconductor layer;
A first contact electrode electrically connected to the first conductivity type semiconductor layer from the bottom surface of the second conductivity type semiconductor layer through the plurality of holes;
A first ion implantation region disposed in the first conductivity type semiconductor layer above the first contact electrode;
An insulating layer disposed between the first contact electrode and the plurality of holes;
A first electrode layer electrically connected to the first contact electrode;
And a second contact electrode electrically connected to the second conductive semiconductor layer. The method according to claim 1,
The first ion implantation region
Wherein the first conductivity type ion is implanted. The method according to claim 1,
The horizontal width of the first ion implantation region
Wherein the first contact electrode is larger than the horizontal width of the first contact electrode. The method according to claim 1,
And a second ion-implanted region formed on the first conductivity-type semiconductor layer on both sides of the first contact electrode. The method according to claim 1,
Wherein the insulating layer comprises a reflective material. The method according to claim 1,
And a channel layer surrounding the first contact electrode,
And the channel layered material. The method according to claim 1,
The first electrode layer
A diffusion barrier layer on the first contact electrode,
And a bonding layer is formed on the diffusion preventing layer. 8. The method of claim 7,
The first contact electrode
And the width decreases from the top surface to the bottom surface. The method according to claim 1,
And the horizontal width of the plurality of holes decreases toward the upper side. A lighting system comprising a light-emitting unit comprising the light-emitting element according to any one of claims 1 to 9.

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