KR20140090300A - Latency control circuit and semiconductor memory device including the same - Google Patents

Abstract

A semiconductor memory device comprising: an internal command generator for generating an internal command in response to an external command; an internal clock generator for delaying an external clock by an operation delay amount of the internal command generator, A command synchronization unit for sequentially generating a synchronization command by synchronizing an internal command with an internal clock and an external clock to compensate an operation delay amount of the internal command generation unit; And a latency shifter for shifting the latency by a predetermined number of times of latency.

Description

TECHNICAL FIELD [0001] The present invention relates to a latency control circuit and a semiconductor memory device including the latency control circuit.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design technology, and more specifically, to a circuit for controlling latency and a semiconductor memory device including the same.

A semiconductor memory device used as a main memory in a computer system inputs data into a memory cell or outputs data from a memory cell. The data input / output speed of a semiconductor memory device is a very important factor in determining the operating speed of a computer system. In order to improve the operation speed of a semiconductor memory device, a synchronous dynamic random access memory (SDRAM) in which internal circuits are controlled in synchronization with a clock signal generated from a computer system has been used.

Generally, synchronous semiconductor memory devices (SDRAMs) use a column address strobe (CAS) latency function to increase the operating frequency. The cache latency represents the number of cycles of the external clock until data is output to the outside after a read command is applied to the synchronous semiconductor memory device. The synchronous semiconductor memory device internally reads data in response to a read command, and then outputs data after a clock cycle corresponding to the cache latency. For example, when the cache latency is 8, the data is output to the outside in synchronization with the external clock after 8 clock cycles from the external clock to which the read command is applied.

The latency control circuit generates a latency control signal, which is an output control signal, in order to control output data in the synchronous semiconductor memory device to be output after a set clock cycle. That is, the latency control circuit serves as an output control circuit. The data output buffer of the synchronous semiconductor memory device outputs data in response to the output clock signal while the latency control signal is active. Therefore, after the read command is applied, the latency control circuit must provide a latency control signal before a predetermined cycle of the output clock signal according to the cache latency.

The latency control signal is generated when the internal read command signal generated by decoding the read command is latched by the output clock signal and the clock signals delayed by the output clock signal. Typically, the pulse width of the internal read command signal corresponds to one period of the external clock, and the output clock signal is generated in response to a delay locked loop (DLL) clock generated through the delay locked loop, Have the same frequency.

1 is a block diagram showing a latency control circuit of a semiconductor memory device according to the prior art.

1, a latency control circuit of a semiconductor memory device according to the related art includes a delay locked loop 100, an internal command generator 110, a command variable delay unit 150, a latency shifter 160 A buffer unit 170, and an output control unit 180. [0035] Here, the delay locked loop 100 includes a delayed copy model unit 102, a phase comparison unit 104, a delay amount control unit 106, and a DLL variable delay unit 108. The internal command generation section 110 includes a command decoding section 114 and an additional latency shifting section 116. The buffer unit 170 includes a clock buffer unit 172 and a command buffer unit 174. [

The buffer unit 170 buffers the externally applied clock CLK and the command CMD to generate an external clock ICLK and an external command ICMD. At this time, the externally applied clock CLK and the external clock ICLK have a phase difference by the buffering delay amount tD1. Likewise, the external command CMD and the external command ICMD have a phase difference by the buffering delay amount tD1.

The delay locked loop 100 includes an external clock LCLK for delay fixing between the feedback clock FBCLK generated by reflecting the delay amount tD1 + tD6 of the clock delay path to the delay locked clock DLLCLK and the external clock ICLK, (ICLK) as a delay locked clock DLLCLK.

The internal command generation unit 110 generates the internal command ICMD_A in response to the external command ICMD. The command decoding unit 114 among the constituent elements of the internal command generating unit 110 decodes the external command ICMD to generate a decoding command ICMD_C. The additional latency shifting unit 116 of the internal command generating unit 110 shifts the internal command ICMD_C by an additive latency (AL) based on the external clock ICLK, ICMD_A. At this time, the external command ICMD and the internal command ICMD_A have a phase difference of the operation delay amount tD2 of the internal command generation unit 110. [

The command variable delay unit 150 delays the internal command ICMD_A by the variable delay amount tD3 of the delay locked loop 100 and outputs the delayed command as the variable delay command ICMD_R.

The latency shifter 160 shifts the variable delay command ICMD_R by a CAS latency (CL) or a CAS write latency (CWL) based on the delay locked clock DLLCLK to generate a latency control signal LT_CON).

The output controller 180 controls the data output (IN_DATA -> TX_DATA) in response to the latency control signal LT_CON and the delay locked clock DLLCLK.

FIG. 2 is a timing diagram illustrating the operation of the latency control circuit of the semiconductor memory device according to the prior art shown in FIG. 1 and its problem.

Referring to FIG. 2, it can be seen that the latency control circuit of the semiconductor memory device according to the related art has a smaller latency margin as the operating frequency of an external clock CLK increases.

First, the operation of the latency control circuit of the semiconductor memory device according to the related art will be described below in a state where the operating frequency of the clock CLK applied from the outside is relatively low (Low Frequency).

The external clock (CLK) and the external clock (ICLK) are phase-shifted by the buffering delay amount (tD1).

The command CMD and the external command ICMD applied from the outside have a phase difference by the buffering delay amount tD1.

The external clock ICLK and the delay locked clock DLLCLK have a phase difference by a variable delay amount tD3.

The external command ICMD and the internal command ICMD_A have a phase difference by an operation delay amount tD2 of the internal command generation unit 110. [ At this time, the internal command generation unit 110 includes the command decoding unit 114 and the additional latency shifting unit 116. However, since the internal command generation unit 110 has assumed the additional latency (AL) The operation delay amount tD2 of the command decoder 114 can be regarded as a delay amount generated due to the decoding operation of the command decoder 114. [

The internal command ICMD_A and the variable delay command ICMD_R have phase differences by the variable delay amount tD3.

The latency control signal LT_CON is generated by shifting the variable delay command ICMD_R by the cascade CL or the cascade latency CWL on the basis of the delay locked clock DLLCLK. At this time, shifting the variable delay command ICMD_R based on the delay locked clock DLLCLK means that the logic level of the variable delay command ICMD_R is detected and transmitted in the logic high period of the delay locked clock DLLCLK .

Therefore, as shown in the figure, the frequency of the externally applied clock CLK becomes low and the logic high period of the delay locked clock DLLCLK and the period of the variable delayed command ICMD_R The latency shift operation can be performed without any problem in a state in which the logic 'low' section is sufficiently overlapped.

The operation of the latency control circuit of the semiconductor memory device according to the prior art will be described below in a state where the operating frequency of the clock CLK applied from the outside is relatively high.

The external clock (CLK) and the external clock (ICLK) are phase-shifted by the buffering delay amount (tD1).

The command CMD and the external command ICMD applied from the outside have a phase difference by the buffering delay amount tD1.

The external clock ICLK and the delay locked clock DLLCLK have a phase difference by a variable delay amount tD3.

The external command ICMD and the internal command ICMD_A have a phase difference by an operation delay amount tD2 of the internal command generation unit 110. [ At this time, the internal command generation unit 110 includes the command decoding unit 114 and the additional latency shifting unit 116. However, since the internal command generation unit 110 has assumed the additional latency (AL) The operation delay amount tD2 of the command decoder 114 can be regarded as a delay amount generated due to the decoding operation of the command decoder 114. [

The internal command ICMD_A and the variable delay command ICMD_R have phase differences by the variable delay amount tD3.

The latency control signal LT_CON is generated by shifting the variable delay command ICMD_R by the cascade CL or the cascade latency CWL on the basis of the delay locked clock DLLCLK. At this time, shifting the variable delay command ICMD_R based on the delay locked clock DLLCLK means that the logic level of the variable delay command ICMD_R is detected and transmitted in the logic high period of the delay locked clock DLLCLK .

However, as shown in the figure, the frequency of the externally applied clock CLK is high and the logic high period of the delay locked clock DLLCLK and the period of the variable delayed command ICMD_R There may arise a problem that the latency shift operation can not be normally performed in a state in which the logic 'low' section can not sufficiently overlap.

As described above, the margin between the variable delay command ICMD_R and the delay locked clock DLLCLK applied to the latency shifter 160 decreases as the frequency of the externally applied clock CLK increases, . That is, when the frequency of the externally applied clock CLK is increased, the pulse width of the variable delay command ICMD_R corresponding to one period (1 tck) of the clock CLK is also made smaller, The phase of the clock DLLCLK may be ahead of the variable delay command ICMD_R. In view of the fact that the variable delay command ICMD_R is a clock (CLK) domain and skew occurs due to the influence of frequency, ambient pressure, temperature, etc. due to difference in the delay locked clock (DLLCLK) domain, The likelihood of occurrence of the same problem can also increase significantly.

If the margin between the variable delay command ICMD_R and the delay locked clock DLLCLK becomes small or the phase of the delay locked clock DLLCLK becomes higher than the pulse width of the variable delay command ICMD_R, (ICMD_R) can not be normally latched, so that it is not possible to perform appropriate shifting according to the cascade (CL) or the cascade latency (CWL).

The present invention relates to a circuit for controlling a latency that can stably perform a latency shifting operation irrespective of frequency variations and a semiconductor memory device including the same.

That is, the present invention relates to a circuit for controlling latency capable of stably performing a latency shifting operation not only in a case where a clock frequency is relatively low but also in a relatively high clock frequency, and a semiconductor memory device including the same.

According to an aspect of the present invention, there is provided an apparatus including: an internal command generation unit for generating an internal command in response to an external command; A clock delay unit for generating an internal clock by delaying an external clock by an operation delay amount of the internal command generation unit; A command synchronizer for sequentially synchronizing the internal command with the internal clock and the external clock to generate a synchronization command to compensate for an operation delay amount of the internal command generator; And a latency shifter for shifting the synchronization command by a predetermined number of latency times based on the external clock.

According to another aspect of the present invention, there is provided a delay locked loop circuit including a variable delay circuit for delaying the external clock by a predetermined delay time in order to establish a delay lock between an external clock and a feedback clock generated by reflecting a delay amount of the clock delay path, And outputting the delay locked loop as the delay locked clock; An internal command generation unit for generating an internal command in response to an external command; A clock delay unit for generating an internal clock by delaying the external clock by an operation delay amount of the internal command generator; A command synchronizer for sequentially synchronizing the internal command with the internal clock and the external clock to generate a synchronization command to compensate for an operation delay amount of the internal command generator; A command variable delay unit for delaying the synchronization command by a variable delay amount of the delay locked loop; A latency shifter for generating a latency control signal by shifting an output command of the variable delay unit by a predetermined latency based on the delay locked clock; And an output control unit for controlling data output in response to the latency control signal and the delay locked clock.

According to another aspect of the present invention, there is provided a method of controlling a delay locked loop, the method comprising: A delay locked loop for delaying and outputting the delayed fixed clock; A duty correction unit for correcting the duty ratio of the delay locked clock and outputting the duty correction clock as a duty correction clock; An internal command generation unit for generating an internal command in response to an external command; A command variable delay unit for delaying the internal command by a variable delay amount of the delay locked loop to generate a variable delay command; A clock delay unit for generating the internal clock by delaying the duty correction clock by a delay amount by subtracting the operation delay amount of the duty correction unit from the operation delay amount of the internal command generation unit; A command synchronization unit for sequentially generating a synchronization command by sequentially synchronizing the variable delay command with the internal clock and the duty correction clock to compensate for an operation delay amount of the internal command generator; A latency shifter for generating a latency control signal by shifting the synchronization command by a predetermined latency based on the duty correction clock; And an output control unit for controlling data output in response to the latency control signal and the duty correction clock.

The above-described present invention adds a circuit for compensating the delay amount of the command decoder, which is an asynchronous element to the clock among the command delivery paths, so that the interval between the clock and the command used for latency shifting is always based on the period of the clock There is an effect of maintaining a constant spacing.

Thus, there is an effect that the latency shifting operation can be performed stably regardless of whether the frequency of the clock fluctuates, that is, not only when the frequency of the clock is relatively low but also relatively high.

1 is a block diagram showing a latency control circuit of a semiconductor memory device according to the prior art.
FIG. 2 is a timing diagram illustrating the operation of the latency control circuit of the semiconductor memory device according to the prior art shown in FIG. 1 and its problem.
3 is a block diagram illustrating a latency control circuit according to an embodiment of the present invention.
FIG. 4 is a detailed circuit diagram of a clock delay unit and a command synchronization unit of the components of the latency control circuit according to the embodiment of the present invention shown in FIG.
FIG. 5 is a timing diagram illustrating the operation of the latency control circuit according to the embodiment of the present invention shown in FIG.
6 is a block diagram illustrating a semiconductor memory device including a latency control circuit according to the first embodiment of the present invention.
FIG. 7 is a detailed circuit diagram of a clock delay unit and a command synchronization unit of the semiconductor memory device including the latency control circuit according to the first embodiment of the present invention shown in FIG.
FIG. 8 is a timing diagram illustrating the operation of the semiconductor memory device including the latency control circuit according to the first embodiment of the present invention shown in FIG.
9 is a block diagram illustrating a semiconductor memory device including a latency control circuit according to a second embodiment of the present invention.
FIG. 10 is a detailed circuit diagram of a clock delay unit and a command synchronization unit in the semiconductor memory device including the latency control circuit according to the second embodiment of the present invention shown in FIG.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that the present invention is not limited to the disclosed embodiments, but may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein, Is provided to fully inform the user.

3 is a block diagram illustrating a latency control circuit according to an embodiment of the present invention.

3, the latency control circuit according to the embodiment of the present invention includes an internal command generation unit 310, a clock delay unit 320, a command synchronization unit 340, a latency shifting unit 360, And a buffer unit 370. Here, the buffer unit 370 includes a clock buffer unit 372 and a command buffer unit 374. In addition, the internal command generation unit 310 includes a command decoding unit 314 and an additional latency shifting unit 316.

The buffer unit 370 buffers the externally applied clock CLK and the command CMD to generate an external clock ICLK and an external command ICMD. More specifically, the buffer unit 370 includes an external clock ICLK buffered by an externally applied clock CLK, a clock delay unit 320, an additional latency shifter 316, and a latency shifter 360 And a command buffer unit 374 for transferring an external command (ICMD) generated by buffering the command (CMD) applied from the outside to the internal command generation unit 310 . At this time, the externally applied clock CLK and the external clock ICLK have a phase difference by the buffering delay amount tD1. Likewise, the external command CMD and the external command ICMD have a phase difference by the buffering delay amount tD1. That is, the clock buffer unit 372 and the command buffer unit 374 each have an operation delay amount equal to the buffering delay amount tD1.

The command generating unit 310 generates an internal command ICMD_A in response to an external command ICMD. The command decoding unit 314 among the constituent elements of the command generating unit 310 decodes the external command ICMD to generate a decoding command ICMD_C. The additional latency shifting unit 316 among the components of the command generating unit 310 shifts the internal command ICMD_A by adding additional latency (AL) to the decoding command ICMD_C based on the external clock ICLK ). At this time, the external command ICMD and the internal command ICMD_A have a phase difference of the operation delay amount tD2 of the command generation unit 310. [ For reference, the additional latency (AL) generally refers to the time until the column address is input after the row address is input in the semiconductor memory device. However, the latency control circuit according to the embodiment of the present invention can be applied not only to a general semiconductor memory device but also to a semiconductor device which operates synchronously. Therefore, the additional latency shifter 316 shown in FIG. 3 is only a structure for applying a latency value, which can be arbitrarily added by the designer according to the operation of the semiconductor device, to the operation of the latency control circuit, You can choose.

The clock delay unit 320 generates the internal clock DCLK [1: N] by delaying the external clock ICLK by the operation delay amount tD2 of the internal command generation unit 310. [ Here, it is understood that there is only one external clock applied to the clock delay unit 320, but the internal clock DCLK [1: N] output from the clock delay unit 320 is N. [ This is because the clock delay unit 320 delays the external clock ICLK step by step to generate N internal clocks DCLK [1: N]. For example, if the external clock ICLK is the same clock as the first internal clock DCLK [1], the first internal clock DCLK [1] is delayed by the set first delay amount and the second internal clock DCLK [ 2], and generates the third internal clock DCLK [3] by delaying the second internal clock DCLK [2] by a second delay amount that has been set, thereby generating the third internal clock DCLK [ ). The phase difference between the external clock ICLK and the N-th internal clock DCLK [N] is set to be a natural number greater than 2, regardless of the value of N, It should correspond to the operation delay amount tD2. That is, the delay amount of the clock delay unit 320 should be the same as the operation delay amount tD2 of the internal command generation unit 310. [

The command synchronization unit 340 sequentially outputs the internal command ICMD_A to the internal clock DCLK [1: N] and the external clock ICLK in order to compensate the operation delay amount tD2 of the internal command generation unit 310 To generate a synchronization command (ICMD_S). At this time, the command synchronizer 340 synchronizes the internal command ICMD_A with the N-th internal clock DCLK [N] of the N internal clocks DCLK [1: N] 1] having the same phase as the external clock ICLK in such a manner that the internal command ICMD_A synchronized to the N-1th internal clock DCLK [N] is synchronized with the N-1th internal clock DCLK [N-1] : N]) to generate a synchronization command (ICMD_S).

The latency shifter 360 generates the latency control signal LT_CON by shifting the synchronization command ICMD_S by the set number of latency LASHIFT based on the external clock ICLK. At this time, the set latency number (LASHIFT) becomes the number of times (TGSHIFT-N) obtained by subtracting N from the target latency number TGSHIFT. Here, the target number of times of latency TGSHIFT means a target latency value to be latency shifted by the latency control circuit. For example, it means a cache latency (CL) value or a cache write latency (CWL) value in a semiconductor memory device. The reason why the latency shifter 360 performs the latency shifting only by the number of latency times LASHIFT in which the synchronization command ICMD_S is set, that is, the number of times TGSHIFT-N obtained by subtracting N from the target latency times TGSHIFT, N times of latency shifting operations are performed in the process of compensating the delay amount of the internal command generation unit 310 in the synchronization unit 340. That is, the internal command ICMD_A and the synchronization command ICMD_S have a phase difference of N periods based on the external clock ICLK, and the latency shifter 360 compensates for the phase difference by the inverse compensation, The latency control signal LT_CON that is generated by the target latency control circuit LT_CON is latency shifted by the target latency number TGSHIFT as compared with the external command ICMD.

FIG. 4 is a detailed circuit diagram of a clock delay unit and a command synchronization unit of the components of the latency control circuit according to the embodiment of the present invention shown in FIG.

Referring to FIG. 4, the clock delay unit 320 of the components of the latency control circuit according to the embodiment of the present invention delays the external clock ICLK step by step to generate N internal clocks DCLK [1: N] As shown in FIG.

Specifically, since it is assumed that the first internal clock DCLK [1] of the N internal clocks DCLK [1: N] is the same clock as the external clock ICLK, (322 < 1: N-1 >) is N-1.

At this time, the N-1 delay elements 322 <1: N-1> included in the clock delay unit 320 may have the same delay amount or different delay amounts depending on the designer's selection have. but. The sum of the amounts of delay of the N-1 delay elements 322 <1: N-1> included in the clock delay section 320 must be the size of the operation delay amount tD2 of the command generation section 310 do.

The command synchronization unit 340 includes N flip-flops 342 < 1: N &gt;. The first flip-flop 342 <1> receives the internal command ICMD_A applied to the signal input terminal D in response to the N-th internal clock DCLK [N] applied to the clock input terminal C, To the output stage (Q). The second flip-flop 342 < 2 > is connected to the first input terminal C in response to the (N-1) -th internal clock DCLK [N-1] (FCM [1]) placed on the signal output terminal Q of the flip 342 <1> to the signal output terminal Q. The Nth flip-flop 342 is connected to the Nth flip-flop 342 in the same manner as the connection method of the first flip-flop 342 <1> and the second flip-flop 342 < The synchronizing command ICMD_S is outputted to the signal output terminal Q of the synchronizing signal generating circuit.

FIG. 5 is a timing diagram illustrating the operation of the latency control circuit according to the embodiment of the present invention shown in FIG.

5, the latency control circuit according to the embodiment of the present invention is configured such that the interval between the synchronization command ICMD_S applied to the latency shifter 360 and the external clock ICLK is always It can be seen that the half clock period (1 / 2tck) is obtained. For reference, the timing diagram shown in Fig. 5 shows that the operation of the latency control circuit is performed in a state where N is 3.

It can be seen that the external clock ICLK is delayed step by step to generate a total of three internal clocks DCLK [1: 3] with an interval of the operation delay amount tD2 of the command generator 310. [ That is, the first internal clock DCLK [1] having the same phase as the external clock ICLK, the second internal clock DCLK [2] delaying the external clock ICLK, and the second internal clock DCLK [ 2] is delayed. The third internal clock DCLK [3] is generated. At this time, the phase difference between the first internal clock DCLK [1] and the third internal clock DCLK [3] having the same phase as the external clock ICLK is the operation delay amount tD2 of the command generator 310, .

The internal command ICMD_A output from the command generation unit 310 is output as the first synchronization command FCM [1] in response to the third internal clock DCLK [3]. That is, it is outputted as the first synchronization command FCM [1] during one period (1 tck) at the time corresponding to the rising edge of the third internal clock (DCLK [3]) in the interval in which the internal command ICMD_A is input.

Then, the first synchronization command FCM [1] is output as the second synchronization command FCM [2] in response to the second internal clock DCLK [2]. That is, the second synchronization command FCM [2] for one period (1 tck) at the time corresponding to the rising edge of the second internal clock (DCLK [2]) in the interval in which the first synchronization command (FCM [ .

Finally, the second synchronization command FCM [2] is output as the third synchronization command ICMD_S in response to the first internal clock DCLK [1]. That is, as a third synchronization command (ICMD_S) for one period (1 tck) at a time corresponding to the rising edge of the first internal clock (DCLK [1]) in the interval in which the second synchronization command (FCM [ do.

At this time, since the first internal clock DCLK [1] is a clock having the same phase as the external clock ICLK, it can be seen that the third synchronization command ICMD_S is synchronized with the external clock ICLK.

Therefore, it can be seen that the interval between the synchronization command ICMD_S and the external clock ICLK applied to the latency shifter 360 is always a half clock cycle (1 / 2tck) on the basis of the external clock ICLK, , And the frequency of the external clock ICLK is kept constant even when the frequency becomes faster or slower.

To summarize, the latency control circuit according to the above-described embodiment of the present invention is characterized in that the operation for compensating the operation delay amount of the command generator 310, which is regarded as an element asynchronous to the clock in the command delivery path, By controlling the shifting operation to be performed before the shifting operation, it is possible to maintain a constant interval between the latency shifting clock and the command based on the period of the clock at the time when the layout shifting operation is performed. Therefore, the latency shifting operation can be performed stably regardless of whether the frequency of the clock fluctuates, that is, not only when the frequency of the clock is relatively low but also if it is relatively high.

6 is a block diagram illustrating a semiconductor memory device including a latency control circuit according to the first embodiment of the present invention.

6, a semiconductor memory device including a latency control circuit according to the first embodiment of the present invention includes a delay locked loop 600, an internal command generator 610, a clock delay unit 620, A command synchronization unit 640, a command variable delay unit 650, a latency shifting unit 660, a buffer unit 670, and an output control unit 680. The delay locked loop 600 includes a delayed replication model unit 602, a phase comparison unit 604, a delay amount control unit 606, and a DLL variable delay unit 608. The buffer unit 670 includes a clock buffer unit 672 and a command buffer unit 674. [ The internal command generation unit 610 includes a command decoding unit 614 and an additional latency shifting unit 616.

The buffer unit 670 buffers the externally applied clock CLK and the command CMD to generate an external clock ICLK and an external command ICMD. More specifically, the buffer unit 670 buffers an external clock (ICLK) generated by buffering an externally applied clock (CLK) to the clock delay unit 620, the additional latency shifter 616, and the latency shifter 660 And a command buffer unit 674 for transferring an external command (ICMD) generated by buffering the command (CMD) applied from the outside to the internal command generation unit 610 . At this time, the externally applied clock CLK and the external clock ICLK have a phase difference by the buffering delay amount tD1. Likewise, the external command CMD and the external command ICMD have a phase difference by the buffering delay amount tD1. That is, the clock buffer unit 672 and the command buffer unit 674 each have an operation delay amount equal to the buffering delay amount tD1.

The delay locked loop 100 includes an external clock LCLK for delay fixing between the feedback clock FBCLK generated by reflecting the delay amount tD1 + tD6 of the clock delay path to the delay locked clock DLLCLK and the external clock ICLK, (ICLK) as a delay locked clock DLLCLK. That is, the external clock ICLK and the delay locked clock DLLCLK have a phase difference of the variable delay amount tD3. For reference, the detailed configuration and operation of the delay locked loop 600 are well known and will not be described in detail here.

The command generation unit 610 generates an internal command ICMD_A in response to an external command ICMD. The command decoding unit 614 among the components of the command generating unit 610 decodes the external command ICMD to generate a decoding command ICMD_C. The additional latency shifting unit 616 among the components of the command generating unit 610 shifts the internal command ICMD_A by adding an additional latency (AL) to the decoding command ICMD_C based on the external clock ICLK ). At this time, the external command ICMD and the internal command ICMD_A have a phase difference of the operation delay amount tD2 of the command generating unit 610. [ For reference, the additional latency (AL) generally refers to the time until the column address is input after the row address is input in the semiconductor memory device.

The clock delay unit 620 generates the internal clock DCLK [1: N] by delaying the external clock ICLK by the operation delay amount tD2 of the internal command generation unit 610. [ Although it is assumed that there is only one external clock ICLK applied to the clock delay unit 620, the internal clock DCLK [1: N] output from the clock delay unit 620 is N. [ This is because the clock delay unit 620 delays the external clock ICLK step by step to generate N internal clocks DCLK [1: N]. For example, if the external clock ICLK is the same clock as the first internal clock DCLK [1], the first internal clock DCLK [1] is delayed by the set first delay amount and the second internal clock DCLK [ 2], and generates the third internal clock DCLK [3] by delaying the second internal clock DCLK [2] by a second delay amount that has been set, thereby generating the third internal clock DCLK [ ). The phase difference between the external clock ICLK and the N-th internal clock DCLK [N] is set to be a natural number greater than 2, regardless of the value of N, It should correspond to the operation delay amount tD2. That is, the delay amount of the clock delay unit 620 should be the same as the operation delay amount tD2 of the internal command generation unit 610. [

The command synchronizing unit 640 sequentially outputs the internal command ICMD_A to the internal clock DCLK [1: N] and the external clock ICLK in order to compensate for the operation delay amount tD2 of the internal command generating unit 610 To generate a synchronization command (ICMD_S). At this time, the command synchronizer 640 synchronizes the internal command ICMD_A with the N-th internal clock DCLK [N] of the N internal clocks DCLK [1: N], and then synchronizes the N-th internal clock DCLK [ 1] having the same phase as the external clock ICLK in such a manner that the internal command ICMD_A synchronized to the N-1th internal clock DCLK [N] is synchronized with the N-1th internal clock DCLK [N-1] : N]) to generate a synchronization command (ICMD_S).

The command variable delay unit 650 delays the synchronization command ICMD_S by the variable delay amount tD3 of the delay locked loop 600 and outputs the delayed command as the variable delay command ICMD_R. That is, the synchronization command ICMD_S is supplied to the variable delay amount tD3 to correspond to the delay locked clock DLLCLK generated by delaying the external clock ICLK by the variable delay amount tD3 while passing through the delay locked loop 600, And outputs it as the variable delay command ICMD_R.

The latency shifter 660 generates the latency control signal LT_CON by shifting the variable delay command ICMD_R by the set number of latency LASHIFT based on the delay locked clock DLLCLK. At this time, the set latency number (LASHIFT) becomes the number of times (CLSHIFT-N or CWLSHIFT-N) obtained by subtracting N from the target latency number (CLSHIFT or CWLSHIFT). Here, the target number of times of latency (CLSHIFT or CWLSHIFT) means a target latency value to be latency shifted by the latency control circuit. (CL) value (CLSHIFT) or a cache write latency (CWL) value (CWLSHIFT) used in a semiconductor memory device. The latency shifter 660 performs latency shifting only by the number of latency times (LASHIFT) of the internal command ICMD_A, that is, the number of times CLSHIFT-N or CWLSHIFT-N obtained by subtracting N from the target latency number CLSHIFT or CWLSHIFT This is because the N times latency shifting operation is performed in the process of compensating the delay amount of the internal command generating unit 610 in the command synchronizing unit 640. That is, the internal command ICMD_A and the synchronization command ICMD_S have a phase difference of N periods based on the external clock ICLK, and the latency shifter 660 compensates for the phase difference by the inverse compensation, The latency control signal LT_CON generated by the latch circuit is latency shifted by the target latency number (CLSHIFT or CWLSHIFT) as compared with the external command ICMD.

The output control unit 680 controls the data output (IN_DATA - > TX_DATA) in response to the latency control signal LT_CON and the delay locked clock DLLCLK. That is, the internal data IN_DATA output from the semiconductor memory device starts to be output as the external data TX_DATA in response to the latency control signal LT_CON, and the burst data is output in response to the delay locked clock DLLCLK. BL are sequentially output as external data TX_DATA.

FIG. 7 is a detailed circuit diagram of a clock delay unit and a command synchronization unit of the semiconductor memory device including the latency control circuit according to the first embodiment of the present invention shown in FIG.

Referring to FIG. 7, the clock delay unit 620 among the components of the semiconductor memory device including the latency control circuit according to the first embodiment of the present invention shown in FIG. 6 delays the external clock ICLK step by step To generate N internal clocks DCLK [1: N].

Specifically, since it is assumed that the first internal clock DCLK [1] of the N internal clocks DCLK [1: N] is the same clock as the external clock ICLK, the delay elements included in the clock delay unit 620 (622 < 1: N-1 >) is N-1.

At this time, the N-1 delay elements 622 <1: N-1> included in the clock delay unit 620 may have the same delay amount by the designer's choice, have. but. The sum of the amounts of delay of the N-1 delay elements 622 <1: N-1> included in the clock delay unit 620 must be the size of the operation delay amount tD2 of the command generation unit 610 do.

The command synchronization unit 640 includes N flip-flops 642 < 1: N &gt;. The first flip-flop 642 <1> receives the internal command ICMD_A applied to the signal input terminal D in response to the N-th internal clock DCLK [N] applied to the clock input terminal C, To the output stage (Q). The second flip-flop 642 < 2 > receives the first flip-flop 642 < 2 &gt;, which is applied to the signal input D in response to the (N-1) (FCM [1]) placed on the signal output terminal Q of the flip-flop 642 <1> to the signal output terminal Q. The Nth flip-flop 642 is connected to the Nth flip-flop 642 in the same manner as the connection method of the first flip-flop 642 <1> and the second flip-flop 642 < The synchronizing command ICMD_S is outputted to the signal output terminal Q of the synchronizing signal generating circuit.

FIG. 8 is a timing diagram illustrating the operation of the semiconductor memory device including the latency control circuit according to the first embodiment of the present invention shown in FIG.

8, a semiconductor memory device including a latency control circuit according to the first embodiment of the present invention includes a delay control circuit 660 and a delay control circuit 660. The semiconductor memory device according to the first embodiment of the present invention controls the interval between the variable delay command ICMD_R applied to the latency shifter 660 and the delay locked clock DLLCLK It can be seen that the half clock cycle (1 / 2tck) is always always based on the delay locked clock DLLCLK. Note that the timing diagram shown in Fig. 8 shows that the operation of the latency control circuit is performed in a state where N is 3.

It can be seen that the external clock ICLK is delayed stepwise to generate a total of three internal clocks DCLK [1: 3] at intervals of the operation delay amount tD2 of the command generator 610. [ That is, the first internal clock DCLK [1] having the same phase as the external clock ICLK, the second internal clock DCLK [2] delaying the external clock ICLK, and the second internal clock DCLK [ 2] is delayed. The third internal clock DCLK [3] is generated. At this time, the phase difference between the first internal clock DCLK [1] and the third internal clock DCLK [3] having the same phase as the delay locked clock DLLCLK is the operation delay amount tD2 of the command generator 610 ).

The internal command ICMD_A output from the command generation unit 610 is output as the first synchronization command FCM [1] in response to the third internal clock DCLK [3]. That is, it is outputted as the first synchronization command FCM [1] during one period (1 tck) at the time corresponding to the rising edge of the third internal clock (DCLK [3]) in the interval in which the internal command ICMD_A is input.

Then, the first synchronization command FCM [1] is output as the second synchronization command FCM [2] in response to the second internal clock DCLK [2]. That is, the second synchronization command FCM [2] for one period (1 tck) at the time corresponding to the rising edge of the second internal clock (DCLK [2]) in the interval in which the first synchronization command (FCM [ .

Finally, the second synchronization command FCM [2] is output as the third synchronization command ICMD_S in response to the first internal clock DCLK [1]. That is, as a third synchronization command (ICMD_S) for one period (1 tck) at a time corresponding to the rising edge of the first internal clock (DCLK [1]) in the interval in which the second synchronization command (FCM [ do.

At this time, since the first internal clock DCLK [1] is a clock having the same phase as the external clock ICLK, it can be seen that the third synchronization command ICMD_S is synchronized with the external clock ICLK.

The delay locked clock DLLCLK is generated by delaying the external clock ICLK by the variable delay amount tD3 and the variable delay command ICMD_R is delayed by the variable delay amount tD3 by the third synchronization command ICMD_S. The third synchronization command ICMD_S and the delay locked clock DLLCLK are also in a synchronized state.

Accordingly, it can be seen that the interval between the variable delay command ICMD_R and the delay locked clock DLLCLK applied to the latency shifter 660 is always a half clock cycle (1 / 2tck) on the basis of the delay locked clock DLLCLK , Which is a characteristic that is maintained constant even when the frequency of the delay locked clock DLLCLK is faster or slower.

To summarize, the latency control circuit according to the above-described embodiment of the present invention is characterized in that the operation for compensating the operation delay amount of the command generator 610, which is regarded as an element asynchronous to the clock among the command delivery paths, By controlling the shifting operation to be performed before the shifting operation, it is possible to maintain a constant interval between the latency shifting clock and the command based on the period of the clock at the time when the layout shifting operation is performed. Therefore, the latency shifting operation can be performed stably regardless of whether the frequency of the clock fluctuates, that is, not only when the frequency of the clock is relatively low but also if it is relatively high.

9 is a block diagram illustrating a semiconductor memory device including a latency control circuit according to a second embodiment of the present invention.

9, a semiconductor memory device including a latency control circuit according to the second embodiment of the present invention includes a delay locked loop 900, an internal command generator 910, a clock delay unit 920, A command synchronization unit 940, a command variable delay unit 950, a latency shifter 960, a buffer unit 970, an output control unit 980, and a duty correction unit 990. The delay locked loop 900 includes a delayed copy model unit 902, a phase comparison unit 904, a delay amount control unit 906 and a DLL variable delay unit 908. The buffer unit 970 includes a clock buffer unit 972 and a command buffer unit 974. The internal command generation unit 910 includes a command decoding unit 914 and an additional latency shifting unit 916. The duty correction unit 990 includes a duty ratio adjusting unit 992 and a clock driving unit 994.

The buffer unit 970 buffers an externally applied clock CLK and a command CMD to generate an external clock ICLK and an external command ICMD. More specifically, the buffer unit 970 buffers an external clock (ICLK) buffered by an externally applied clock (CLK) to the clock delay unit 920, the additional latency shifter 916, and the latency shifter 960 And a command buffer unit 974 for transferring the external command (ICMD) generated by buffering the command (CMD) applied from the outside to the internal command generation unit 910 . At this time, the externally applied clock CLK and the external clock ICLK have a phase difference by the buffering delay amount tD1. Likewise, the external command CMD and the external command ICMD have a phase difference by the buffering delay amount tD1. That is, the clock buffer unit 972 and the command buffer unit 974 each have an operation delay amount equal to the buffering delay amount tD1.

The delay locked loop 100 includes an external clock LCLK for delay fixing between the feedback clock FBCLK generated by reflecting the delay amount tD1 + tD6 of the clock delay path to the delay locked clock DLLCLK and the external clock ICLK, (ICLK) as a delay locked clock DLLCLK. That is, the external clock ICLK and the delay locked clock DLLCLK have a phase difference of the variable delay amount tD3. For reference, the detailed configuration and operation of the delay locked loop 900 are well known and will not be described in detail here.

The internal command generation unit 910 generates the internal command ICMD_A in response to the external command ICMD. The command decoding unit 914 among the constituent elements of the internal command generating unit 910 decodes the external command ICMD to generate a decoding command ICMD_C. The additional latency shifting unit 916 of the internal command generating unit 910 shifts the internal command ICMD_C by an additive latency (AL) based on the external clock ICLK, ICMD_A. At this time, the external command ICMD and the internal command ICMD_A have a phase difference of the operation delay amount tD2 of the internal command generation unit 910. [ For reference, the additional latency (AL) generally refers to the time until the column address is input after the row address is input in the semiconductor memory device.

The command variable delay unit 950 delays the internal command ICMD_A by the variable delay amount tD3 of the delay locked loop 900 and outputs the delayed command as the variable delay command ICMD_R. That is, the internal command ICMD_A is supplied to the variable delay amount tD3 to correspond to the delay locked clock DLLCLK generated by delaying the external clock ICLK by the variable delay amount tD3 while passing through the delay locked loop 900, And outputs it as the variable delay command ICMD_R.

Duty correction section 990 corrects the duty ratio of delay locked clock DLLCLK and outputs it as duty correction clock DCCCLK. At this time, the delay locked clock DLLCLK and the duty correction clock DCCCLK have a phase difference of the operation delay amount tD5 of the duty cycle correction unit 990.

When the external command ICMD output through the command buffer unit 974 included in the buffer unit 970 is the clock enable command CKE, the operation of the duty cycle correcting unit 990 is turned on / Off control.

That is, in a general semiconductor memory device, after determining that the clock enable command is the clock enable command (CKE) through the command decoding unit 914 included in the internal command generation unit 310, the operation of the duty cycle correction unit 990 is turned on / OFF control. However, in the semiconductor memory device including the latency control circuit according to the second embodiment of the present invention, in response to the external command ICMD output through the command buffer unit 974 included in the buffer unit 970, Off operation of the duty correction unit 990 faster than a general semiconductor memory device by controlling the on / off operation of the duty correction unit 990.

The purpose of turning on / off the operation of the duty correction unit 990 faster than the general semiconductor memory device in this manner is that the clock delay, which is a key component of the semiconductor memory device including the latency control circuit according to the second embodiment of the present invention, The command synchronizing unit 940 and the latency shifting unit 960 operate in response to the duty correction clock DCCCLK and the command variable delay unit 950 operates in synchronization with the internal command generation unit 910 And the command synchronization unit 940. That is, since the command variable delay unit 950 is disposed between the internal command generation unit 910 and the command synchronization unit 940, when the operation of the duty cycle correction unit 990 is controlled as in a general semiconductor memory device, The operation of compensating the operation delay amount tD2 of the clock delay unit 920 and the internal command generation unit 910 in the command synchronization unit 940 can be overlapped with the operation interval of the duty cycle correction unit 990. [ Therefore, it is necessary to perform an operation to control the operation of the duty correction unit 990 in the operation section of the internal command generation unit 910.

The clock delay unit 920, the command synchronization unit 940, and the latency shifter 960, which are core components of the semiconductor memory device including the latency control circuit according to the second embodiment of the present invention, The clock delay unit 920 can operate in response to the clock DCCCLK and the command variable delay unit 950 is disposed between the internal command generation unit 910 and the command synchronization unit 940, And the delay amount to be compensated in the command synchronizing unit 940 is the delay amount tD2 ?? tD5 obtained by subtracting the operation delay amount tD5 of the duty cycle correcting unit 990 from the operation delay amount tD2 of the internal command generating unit 910 ). That is, the delay amount delayed until the external clock ICLK becomes the duty correction clock DCCCLK becomes equal to the variable delay amount tD3 of the delay locked loop 900 and the operation delay amount tD5 of the duty cycle correction unit 990 The delay amount tD3 + tD5 which is the combined delay amount tD3 and the delay amount until the external command ICMD becomes the variable delay command ICMD_R becomes equal to the operation delay amount tD2 of the internal command generation unit 910, The delay amount difference between the duty correction clock DCCCLK and the variable delay command ICMD_R becomes equal to the delay amount tD2 + tD3 of the internal command generator 910, (tD2 ?? tD5) obtained by subtracting the operation delay amount tD5 of the duty cycle correction unit 990 from the delay time tD2. The delay amount to be compensated by the clock delay unit 920 and the command synchronizing unit 940 is equal to the operation delay amount tD5 of the duty correction unit 990 at the operation delay amount tD2 of the internal command generation unit 910, (TD2 ?? tD5).

The clock delay unit 920 outputs the duty correction clock DCCCLK to the operation delay amount tD5 of the duty cycle correction unit 990 at the operation delay amount tD2 of the internal command generation unit 910, The internal clock DCLK [1: N] is generated by delaying it by a delay amount tD2 ?? tD5. Here, it is found that there is only one duty correction clock DCCCLK applied to the clock delay unit 920, but the internal clock DCLK [1: N] output from the clock delay unit 920 is N. [ This is because the clock delay unit 920 delays the duty correction clock DCCCLK step by step to generate N internal clocks DCLK [1: N]. For example, if the duty correction clock DCCCLK is the same clock as the first internal clock DCLK [1], the first internal clock DCLK [1] is delayed by the set first delay amount and the second internal clock DCLK The second internal clock DCLK [2] is generated in such a manner that the third internal clock DCLK [2] is generated by delaying the second internal clock DCLK [2] ]). The phase difference between the duty correction clock DCCCLK and the Nth internal clock DCLK [N] is set to the internal command generator 910 regardless of the value of N, (TD2 ?? tD5) obtained by subtracting the operation delay amount tD5 of the duty cycle correction unit 990 from the operation delay amount tD2 of the duty correction unit 990. [ The delay amount of the clock delay unit 920 is smaller than the delay amount tD2 ?? tD5 obtained by subtracting the operation delay amount tD5 of the duty cycle correction unit 990 from the operation delay amount tD2 of the internal command generation unit 910, Should be in the same state as.

The command synchronizing unit 940 compares the delay amount tD2 ?? tD5 obtained by subtracting the operation delay amount tD5 of the duty cycle correcting unit 990 from the operation delay amount tD2 of the internal command generating unit 910 The synchronous command ICMD_S is generated by sequentially synchronizing the variable delay command ICMD_R to the internal clock DCLK [1: N] and the duty correction clock DCCCLK. At this time, the command synchronization unit 940 synchronizes the variable delay command ICMD_R with the Nth internal clock DCLK [N] of the N internal clocks DCLK [1: N], and then the Nth internal clock DCLK The first internal clock DCLK (N-1) having the same phase as the duty correction clock DCCCLK in such a manner that the internal command ICMD_A synchronized to the N-1th internal clock DCLK [N] [1: N]) to the synchronization command (ICMD_S).

The latency shifter 960 generates the latency control signal LT_CON by shifting the synchronization command ICMD_S by the set number of latency LASHIFT based on the delay locked clock DLLCLK. At this time, the set latency number (LASHIFT) becomes the number of times (CLSHIFT-N or CWLSHIFT-N) obtained by subtracting N from the target latency number (CLSHIFT or CWLSHIFT). Here, the target number of times of latency (CLSHIFT or CWLSHIFT) means a target latency value to be latency shifted by the latency control circuit. (CL) value (CLSHIFT) or a cache write latency (CWL) value (CWLSHIFT) used in a semiconductor memory device. The latency shifter 960 performs latency shifting only by the number of latency times (LASHIFT) of the variable delay command ICMD_R, that is, the number of times CLSHIFT-N or CWLSHIFT-N obtained by subtracting N from the target latency number CLSHIFT or CWLSHIFT The reason why the delay amount tD2 is smaller than the delay amount tD5 obtained by subtracting the operation delay amount tD5 of the duty cycle correction unit 990 from the operation delay amount tD2 of the internal command generation unit 910 in the command synchronization unit 940 ) Is compensated for, N latency shifting operations are performed. In other words, the variable delay command ICMD_R and the synchronization command ICMD_S have a phase difference of N periods based on the duty correction clock DCCCLK, and the latency shifter 960 compensates for the phase difference only , The finally generated latency control signal LT_CON becomes latency shifted by the target number of times of latency (CLSHIFT or CWLSHIFT) as compared with the external command ICMD.

The output control unit 980 controls the data output IN_DATA - > TX_DATA in response to the latency control signal LT_CON and the duty correction clock DCCCLK. That is, the internal data IN_DATA output from the semiconductor memory device starts to be output as external data TX_DATA in response to the latency control signal LT_CON, and is output as burst data in response to the duty correction clock DCCCLK. BL are sequentially output as external data TX_DATA.

FIG. 10 is a detailed circuit diagram of a clock delay unit and a command synchronization unit in the semiconductor memory device including the latency control circuit according to the second embodiment of the present invention shown in FIG.

Referring to FIG. 10, a clock delay unit 920 among the constituent elements of the semiconductor memory device including the latency control circuit according to the second embodiment of the present invention shown in FIG. 9 steps the duty correction clock DCCCLK step by step It can be seen that N internal clocks (DCLK [1: N]) are generated by delaying.

Specifically, since it is assumed that the first internal clock DCLK [1] among the N internal clocks DCLK [1: N] is the same clock as the duty correction clock DCCCLK, the delay included in the clock delay unit 920 The number of elements 922 < 1: N-1 > is N-1.

At this time, the N-1 delay elements 922 < 1: N-1 > included in the clock delay unit 920 may have the same delay amount by the designer's choice, have. but. The amount of delay of the N-1 delay elements 922 &lt; 1: N-1 &gt; included in the clock delay unit 920 is calculated from the operation delay amount tD2 of the command generation unit 910, (TD2? TD5) obtained by subtracting the operation delay amount (tD5) of the operation delay amount (990).

The command synchronization unit 940 includes N flip-flops 942 < 1: N &gt;. The first flip-flop 942 <1> receives the variable delay command ICMD_R applied to the signal input terminal D in response to the N-th internal clock DCLK [N] applied to the clock input terminal C To the signal output terminal (Q). Then, the second flip-flop 942 < 2 > receives the first flip-flop 942 < 2 > applied to the signal input D in response to the (N-1) -th internal clock DCLK [N- (FCM [1]) placed on the signal output terminal Q of the flip flop 942 <1> to the signal output terminal Q. The Nth flip-flop 942 is connected to the Nth flip-flop 942 in the same manner as the connection method of the first flip-flop 942 and the second flip-flop 942 <2> The synchronizing command ICMD_S is outputted to the signal output terminal Q of the synchronizing signal generating circuit.

11 is a timing diagram illustrating the operation of the semiconductor memory device including the latency control circuit according to the second embodiment of the present invention shown in Fig.

11, the semiconductor memory device including the latency control circuit according to the second exemplary embodiment of the present invention includes a delay control circuit 960 and a delay control circuit 960. The semiconductor memory device includes a delay control circuit 960, a delay correction circuit ICMD_R, a duty correction clock DCCCLK, It can be seen that the half clock cycle (1/2 tck) is always always based on this duty correction clock DCCCLK. Note that the timing diagram shown in Fig. 11 shows that the operation of the latency control circuit is performed in a state where N is 3.

It can be seen that the duty correction clock DCCCLK is delayed stepwise to generate a total of three internal clocks DCLK [1: 3] at intervals of the operation delay amount tD2 of the command generator 910. [ That is, the first internal clock DCLK [1] having the same phase as the duty correction clock DCCCLK, the second internal clock DCLK [2] delaying the duty correction clock DCCCLK, and the second internal clock DCLK [ A third internal clock DCLK [3] delaying DCLK [2] is generated. At this time, the phase difference between the first internal clock DCLK [1] and the third internal clock DCLK [3] having the same phase as the duty correction clock DCCCLK is the operation delay amount tD2 of the command generator 910 (TD2 ?? tD5) obtained by subtracting the operation delay amount tD5 of the duty cycle correction unit 990 from the delay amount tD2.

The variable delay command ICMD_R output from the command variable delay unit 950 is output as the first synchronization command FCM [1] in response to the third internal clock DCLK [3]. That is, it is outputted as the first synchronization command FCM [1] for one period (1 tck) at a time point corresponding to the rising edge of the third internal clock DCLK [3] in the interval in which the variable delay command ICMD_R is input .

Then, the first synchronization command FCM [1] is output as the second synchronization command FCM [2] in response to the second internal clock DCLK [2]. That is, the second synchronization command FCM [2] for one period (1 tck) at the time corresponding to the rising edge of the second internal clock (DCLK [2]) in the interval in which the first synchronization command (FCM [ .

Finally, the second synchronization command FCM [2] is output as the third synchronization command ICMD_S in response to the first internal clock DCLK [1]. That is, as a third synchronization command (ICMD_S) for one period (1 tck) at a time corresponding to the rising edge of the first internal clock (DCLK [1]) in the interval in which the second synchronization command (FCM [ do.

At this time, it can be seen that the third synchronization command ICMD_S is synchronized with the duty correction clock DCCCLK since the first internal clock DCLK [1] is a clock having the same phase as the duty correction clock DCCCLK.

Therefore, it can be seen that the interval between the variable delay command ICMD_R and the duty correction clock DCCCLK applied to the latency shifter 960 is always a half clock cycle (1 / 2tck) on the basis of the duty correction clock DCCCLK This is a characteristic that the frequency of the duty correction clock DCCCLK is kept constant even when the frequency is faster or slower.

In summary, the above-described latency control circuit according to the embodiment of the present invention is characterized in that the operation for compensating the operation delay amount of the command generator 910, which is regarded as an element asynchronous to the clock in the command delivery path, By controlling the shifting operation to be performed before the shifting operation, it is possible to maintain a constant interval between the latency shifting clock and the command based on the period of the clock at the time when the layout shifting operation is performed. Therefore, the latency shifting operation can be performed stably regardless of whether the frequency of the clock fluctuates, that is, not only when the frequency of the clock is relatively low but also if it is relatively high.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. Will be apparent to those of ordinary skill in the art.

100, 600, 900: delay locked loop
110, 310, 610, 910: internal command generation unit
320, 620, 920: clock delay unit
340, 640, 940:
150, 650, 950: a command variable delay unit
160, 360, 660, 960: Latency shifting unit
170, 370, 670, 970:
180, 680, 980:
990:

Claims (23)

An internal command generation unit for generating an internal command in response to an external command;
A clock delay unit for generating an internal clock by delaying an external clock by an operation delay amount of the internal command generation unit;
A command synchronizer for sequentially synchronizing the internal command with the internal clock and the external clock to generate a synchronization command to compensate for an operation delay amount of the internal command generator; And
Shifting the synchronization command by a predetermined number of latency times based on the external clock,
And a latch circuit.
The method according to claim 1,
The clock delay unit includes:
By delaying the external clock step by step, Wherein the phase difference between the external clock and the Nth internal clock corresponds to an operation delay amount of the internal command generator.
3. The method of claim 2,
The command synchronization unit,
The first internal clock is synchronized with the Nth internal clock of the N internal clocks, and the Nth synchronized internal clock is synchronized with the (N-1) And having the same phase as the clock - to sequentially generate a synchronization command to generate a synchronization command.
The method of claim 3,
The command synchronization unit,
1) -th internal clock applied to the clock input terminal of the second flip-flop to the signal output terminal in response to the N-th internal clock applied to the clock input terminal of the first flip-flop, Flop and the N flip-flops are provided to the signal output terminal of the first flip-flop.
The method of claim 3,
The set number of times of latency,
And the number of times the target latency time is subtracted from the target latency time.
The method according to claim 1,
The internal-
A command decoding unit decoding the external command to generate the internal command; And
And an additional latency shifter for shifting the internal command decoded based on the external clock by an additional number of times of latency.
The method according to claim 6,
A command buffer unit for buffering a command applied from the outside and transferring the command as the external command to the internal command generation unit; And
Further comprising a clock buffer unit for buffering a clock applied from the outside and providing the external latency to the additional latency shifter, the clock delay unit, and the latency shifter.
A delay locked loop for variably delaying the external clock and outputting the delay locked clock as the delay locked clock in order to establish a delay lock between the feedback clock and the external clock generated by reflecting the delay amount of the clock delay path to the delay locked clock;
An internal command generation unit for generating an internal command in response to an external command;
A clock delay unit for generating an internal clock by delaying the external clock by an operation delay amount of the internal command generator;
A command synchronizer for sequentially synchronizing the internal command with the internal clock and the external clock to generate a synchronization command to compensate for an operation delay amount of the internal command generator;
A command variable delay unit for delaying the synchronization command by a variable delay amount of the delay locked loop;
A latency shifter for generating a latency control signal by shifting an output command of the variable delay unit by a predetermined latency based on the delay locked clock; And
An output control unit for controlling data output in response to the latency control signal and the delay locked clock,
And the semiconductor memory device.
9. The method of claim 8,
The clock delay unit includes:
By delaying the external clock step by step, Wherein the phase difference between the external clock and the Nth internal clock corresponds to an operation delay amount of the internal command generator.
10. The method of claim 9,
The command synchronization unit,
The first internal clock is synchronized with the Nth internal clock of the N internal clocks, and the Nth synchronized internal clock is synchronized with the (N-1) Wherein the synchronizing command is generated by sequentially synchronizing up to a clock having the same phase as the clock.
11. The method of claim 10,
The command synchronization unit,
1) -th internal clock applied to the clock input terminal of the second flip-flop to the signal output terminal in response to the N-th internal clock applied to the clock input terminal of the first flip-flop, Wherein the N flip-flops are provided in a manner that a command placed on a signal output terminal of the first flip-flop applied to a signal input terminal is transmitted to a signal output terminal in response to the first flip-flop.
11. The method of claim 10,
The set number of times of latency,
The number of times the target latency time is subtracted from the target latency time.
9. The method of claim 8,
The internal-
A command decoding unit decoding the external command to generate the internal command; And
And an additional latency shifter for shifting the internal command decoded based on the external clock by an additional number of times of latency.
14. The method of claim 13,
A command buffer unit for buffering a command applied from the outside and transferring the command as the external command to the internal command generation unit; And
Further comprising a clock buffer unit for buffering an externally applied clock to provide said external clock as said delay locked loop, said additional latency shifter, and said clock delay unit.
A delay locked loop for variably delaying the external clock and outputting the delay locked clock as the delay locked clock in order to establish a delay lock between the feedback clock and the external clock generated by reflecting the delay amount of the clock delay path to the delay locked clock;
A duty correction unit for correcting the duty ratio of the delay locked clock and outputting the duty correction clock as a duty correction clock;
An internal command generation unit for generating an internal command in response to an external command;
A command variable delay unit for delaying the internal command by a variable delay amount of the delay locked loop to generate a variable delay command;
A clock delay unit for generating the internal clock by delaying the duty correction clock by a delay amount by subtracting the operation delay amount of the duty correction unit from the operation delay amount of the internal command generation unit;
A command synchronization unit for sequentially generating a synchronization command by sequentially synchronizing the variable delay command with the internal clock and the duty correction clock to compensate for an operation delay amount of the internal command generator;
A latency shifter for generating a latency control signal by shifting the synchronization command by a predetermined latency based on the duty correction clock; And
An output control unit for controlling data output in response to the latency control signal and the duty correction clock,
And the semiconductor memory device.
16. The method of claim 15,
The clock delay unit includes:
The duty correction clock is delayed step by step, Wherein the phase difference between the duty correction clock and the Nth internal clock is a delay obtained by subtracting the operation delay amount of the duty correction unit from the operation delay amount of the internal command generation unit, Of the semiconductor memory device.
17. The method of claim 16,
The command synchronization unit,
Wherein the first internal clock synchronizes the variable delay command with the Nth internal clock of the N internal clocks, and synchronizes the Nth synchronized internal clock with the N-1th internal clock, And having the same phase as the duty correction clock in order to generate the synchronization command.
18. The method of claim 17,
The command synchronization unit,
1) -th internal clock applied to the clock input terminal of the first flip-flop, to the signal output terminal in response to the N-th internal clock applied to the clock input terminal of the second flip-flop, And N flip-flops are provided in a manner that a command placed at a signal output terminal of the first flip-flop, which is applied to a signal input terminal in response to a clock, is transmitted to a signal output terminal.
18. The method of claim 17,
The set number of times of latency,
The number of times the target latency time is subtracted from the target latency time.
16. The method of claim 15,
The internal-
A command decoding unit decoding the external command to generate the internal command; And
And an additional latency shifter for shifting the internal command decoded based on the external clock by an additional number of times of latency.
21. The method of claim 20,
A command buffer unit for buffering a command applied from the outside and transferring the command as the external command to the internal command generation unit; And
And a clock buffer unit for buffering an externally applied clock and providing the external clock as the delay locked loop and the additional latency shifter.
22. The method of claim 21,
And when the external command buffered through the command buffer unit is a clock enable command, the operation of the duty ratio correction unit is on / off controlled in response thereto.
23. The method of claim 22,
The duty-
A duty ratio controller for receiving the delay locked clock and adjusting a duty ratio of the delay locked clock, the operation being controlled on / off in response to the clock enable command; And
And a clock driving unit for driving the output clock of the duty ratio adjusting unit to the clock delay unit, the command synchronizing unit, the latency shifting unit, and the output control unit by using the duty adjusting clock.

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