KR20130025730A - Organic electro-luminesence display panel and manufactucring method of the same - Google Patents

Abstract

The present invention relates to an organic light emitting display panel and a method of manufacturing the organic light emitting display panel which can secure the aperture ratio while increasing the capacity of the storage capacitor, the organic electroluminescent display panel according to the present invention includes a buffer film and an active layer formed on a substrate; A gate insulating film including a first gate insulating film having a first thickness, a second gate insulating film having a second thickness, and a gate electrode overlapping the active layer with the first and second gate insulating films interposed therebetween on the active layer; An interlayer insulating film formed on the gate electrode, source and drain contact holes formed through the first and second gate insulating films to expose the source and drain regions of the active layer, and the interlayer insulating film; A source and a drain formed in each of the source and drain contact holes to be connected to the source and drain regions of the active layer, respectively. An organic electroluminescent element comprising a rain electrode, a first electrode connected to the drain electrode, an organic common layer formed on the first electrode, a second electrode formed to face the first electrode, and the second And a storage capacitor formed by overlapping the upper storage electrode and the lower storage electrode with the gate insulating layer interposed therebetween.

Description

Organic electroluminescent display panel and manufacturing method thereof {ORGANIC ELECTRO-LUMINESENCE DISPLAY PANEL AND MANUFACTUCRING METHOD OF THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic electroluminescent display panel and a method of manufacturing the same, and more particularly, to an organic electroluminescent display panel and a method of manufacturing the same, which can secure an aperture ratio while increasing the capacity of a storage capacitor.

The image display device that realizes various information on the screen is a core technology of the information communication age and it is becoming thinner, lighter, more portable and higher performance. Accordingly, as a flat panel display device that can reduce the weight and volume, which is a disadvantage of the cathode ray tube (CRT), an organic light emitting display device for displaying an image by controlling the amount of light emitted from the organic light emitting layer has been in the spotlight. An organic light emitting display (OLED) is a self-luminous element using a thin light emitting layer between electrodes and has an advantage that it can be thinned like a paper. Such an organic light emitting display (OLED) is divided into an active matrix OLED (PMOLED) and a passive matrix OLED (AMOLED).

At this time, the active matrix OLED (AMOLED) displays images by arranging pixels composed of three color (R, G, B) sub-pixels in a matrix form. Each sub-pixel includes an organic electroluminescent element and a cell driver for driving the organic electroluminescent element. The cell driver includes at least two thin film transistors and a storage capacitor connected between a gate line for supplying a scan signal, a data line for supplying a video data signal, and a common power supply line for supplying a common power supply signal, As shown in Fig.

Meanwhile, in order to realize a high resolution of the display device, the number of pixel areas per unit area must be increased, which means that one pixel area is reduced in size. When the size of one pixel area is small, the area of the storage capacitor is reduced by decreasing the size of the components constituting the pixel area, which means a decrease in storage capacity. Accordingly, the storage capacity is increased by increasing the area of the storage electrode. However, as the area of the storage electrode is increased, the actual pixel area is reduced and the aperture ratio is reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides an organic electroluminescent display panel capable of securing an aperture ratio while increasing the capacity of a storage capacitor, and a method of manufacturing the same.

To this end, the organic light emitting display panel according to the present invention includes a buffer layer and an active layer formed on a substrate, a first gate insulating layer having a first thickness, and a second gate insulating layer having a second thickness, on the active layer. The gate electrode overlapping the active layer with the gate insulating layer, the first and second gate insulating layers interposed therebetween, an interlayer insulating layer formed on the gate electrode, and a source region and a drain region of the active layer exposed; Source and drain contact holes formed to penetrate the first and second gate insulating layers, an interlayer insulating film, source and drain electrodes formed to be connected to the source and drain regions of the active layer, respectively, in the source and drain contact holes; And a first electrode connected to the drain electrode, an organic common layer formed on the first electrode, and facing the first electrode. An organic electroluminescent device including a formed second electrode and a storage capacitor formed by overlapping a storage upper electrode and a lower storage electrode with the second gate insulating layer interposed therebetween.

Here, the second gate insulating film is thicker than the first gate insulating film.

The first gate insulating layer is formed only in a region where the gate electrode is formed, and the second gate insulating layer is formed on the entire surface of the substrate.

In addition, the buffer layer, the active layer, and the first and second gate insulating layers may be formed in the same process.

A method of manufacturing an organic light emitting display panel according to the present invention includes a gate insulating film including a buffer film and an active layer on a substrate, a first gate insulating film having a first thickness, a second gate insulating film having a second thickness, and a storage lower electrode. Forming a gate electrode to overlap the active layer with the first and second gate insulating layers interposed therebetween, and forming a storage upper electrode to overlap the lower storage with the second gate insulating layer interposed therebetween. Forming an interlayer insulating film on a substrate on which the gate electrode and the storage upper electrode are formed, and forming source and drain contact holes penetrating the first and second gate insulating films and the interlayer insulating film; Forming a source and a drain electrode in each of the drain contact holes, and forming a first electrode connected to the drain electrode. Step and further characterized in that it comprises a step of forming with the first organic layer on the common first electrode, a second electrode.

Here, forming a buffer film and an active layer, a gate insulating film including a first gate insulating film having a first thickness, a second gate insulating film having a second thickness, and a storage lower electrode on the substrate may include forming a buffer film on the substrate. Forming an active layer, a first gate insulating film having the first thickness, forming a first photoresist pattern on the first gate insulating film, and a second photoresist thinner than the first photoresist pattern; Forming a lower storage electrode by patterning the active layer and the first gate insulating layer by an etching process using the first and second photoresist patterns, and forming the first and second photoresist patterns by an ashing process. 1) thinning the photoresist pattern, removing the second photoresist pattern, and exposing the etching process using the first photoresist pattern; Removing the first gate insulating layer, and then doping the lower storage insulating layer to have conductivity, and removing the remaining first photoresist, and then applying the second gate insulating layer of the second thickness to the entire surface. Characterized in that it comprises a.

The first and second gate insulating layers are formed on the active layer, and the second gate insulating layers are formed on the storage lower electrode.

The second gate insulating layer may be thicker than the first gate insulating layer.

The buffer layer, the active layer, and the first and second gate insulating layers are formed in the same process.

In the organic light emitting display panel of the present invention, first and second gate insulating layers are formed between the active layer and the gate electrode, and only the second gate insulating layer is formed between the storage lower electrode and the storage upper electrode.

Accordingly, the distance between the gate electrode and the active layer is farther away, thereby improving device characteristics of the thin film transistor, and increasing the storage capacitor capacity by making the distance between the storage lower electrode and the storage upper electrode close.

As such, by increasing the storage capacitor capacity, the area of the upper and lower electrodes of the storage can be reduced, thereby securing an aperture ratio.

1 is an equivalent circuit diagram of one pixel of an organic light emitting display panel according to the present invention.
FIG. 2 is a vertical cross-sectional view of one pixel of the organic light emitting display panel illustrated in FIG. 1.
3A to 3G are cross-sectional views illustrating a method of manufacturing an organic light emitting display panel according to an exemplary embodiment of the present invention shown in FIG. 2.
4A through 4F are cross-sectional views illustrating the gate insulating film illustrated in FIG. 3A.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The configuration of the present invention and the operation and effect thereof will be clearly understood through the following detailed description. Before describing the present invention in detail, the same components are denoted by the same reference symbols as possible even if they are displayed on different drawings. In the case where it is judged that the gist of the present invention may be blurred to a known configuration, do.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to FIGS. 1 to 4F.

1 is an equivalent circuit diagram of one pixel of an organic light emitting display panel according to the present invention, and FIG. 2 is a vertical cross-sectional view of one pixel of the organic electroluminescent display panel shown in FIG. 1.

As illustrated in FIG. 1, one pixel of an organic light emitting display panel according to an exemplary embodiment of the present invention includes a cell driver 200 connected to a gate line GL, a data line DL, and a power line PL; The organic light emitting diode OLED is connected between the cell driver 200 and the ground GND.

The cell driver 200 includes a switch thin film transistor TS connected to a gate line GL and a data line DL, a switch thin film transistor TS, a power supply line PL, and a first electrode of an organic light emitting diode. A driving thin film transistor TD connected between 122 and a storage capacitor C connected between the power supply line PL and the drain electrode 110 of the switch thin film transistor TS.

The gate electrode of the switch thin film transistor TS is connected to the gate line GL, the source electrode is connected to the data line DL, and the drain electrode is connected to the gate electrode and the storage capacitor C of the driving thin film transistor TD. . The source electrode of the driving thin film transistor TD is connected to the power supply line PL, and the drain electrode is connected to the pixel electrode serving as the anode of the OEL cell. The storage capacitor C is connected between the power line PL and the gate electrode of the driving thin film transistor TD.

The switch thin film transistor TS is turned on when a scan pulse is supplied to the gate line GL, and supplies the data signal supplied to the data line DL to the gate electrode of the storage capacitor C and the driving thin film transistor TD. do. The driving thin film transistor TD controls the amount of light emitted from the organic EL device by controlling the current I supplied from the power supply line PL to the organic EL device in response to a data signal supplied to the gate electrode. Also, even when the switch thin film transistor TS is turned off, the driving thin film transistor TD is supplied with a constant current I until the data signal of the next frame is supplied by the voltage charged in the storage capacitor C. The electroluminescent element keeps luminescence.

As shown in FIG. 3, in the driving thin film transistor, a buffer layer 116 and an active layer 114 are formed on the substrate 101, and the gate electrode 106 is formed with the channel region 114C of the active layer 114. The first and second gate insulating layers 112a and 112b are interposed therebetween. The source electrode 108 and the drain electrode 110 are formed so as to be insulated with the gate electrode 106 and the interlayer insulating film 126 interposed therebetween. The source electrode 108 and the drain electrode 110 are n + through the source contact hole 124S and the drain contact hole 124D respectively penetrating the interlayer insulating layer 126 and the first and second gate insulating layers 112a and 112b. It is connected to each of the source region 114S and the drain region 114D of the active layer 114 implanted with impurities. The active layer 114 includes a lightly doped drain (LDD) region (not shown) doped with an n-impurity between the channel region 114C and the source and drain regions 114S and 114D to reduce the off current ). In addition, an organic passivation layer 118 formed of an organic insulating material is formed on the driving thin film transistor TD formed on the substrate 101. Alternatively, the passivation layer on the driving thin film transistor TD may be formed of two layers, an inorganic passivation layer formed of an inorganic insulating material and an organic passivation layer formed of an organic insulating material.

The organic light emitting diode OLED includes a bank insulating layer having a first electrode 122 connected to the drain electrode 110 of the driving thin film transistor TD, and a bank hole 135 exposing the first electrode 122. 130, an organic common layer 132 formed on the first electrode 122, and a second electrode 134 formed to face the first electrode. In the organic light emitting diode OLED, when a voltage is applied between the first electrode 122 and the second electrode 134, holes are formed from the first electrode 122 and electrons from the second electrode 134. The electrons are injected and recombined in the third common layer 150c (the light emitting layer), whereby excitons are generated. As the excitons fall to the ground state, light is emitted to the bottom.

The first electrode 122 is a transparent conductive electrode such as a transparent conductive oxide (TCO) as an anode and is an indium tin oxide (ITO), an indium zinc oxide (IZO), or an IZO. Is formed. Since the first electrode 122 is formed of a transparent conductive electrode, light generated from the light emitting layer may emit back light through the first electrode 122. The second electrode 134 is a cathode and is formed of a reflective metal material such as aluminum (Al). As shown in FIG. 2, the present invention may emit the bottom surface, but may emit the bottom, the front side, or the both sides depending on the material of the first and second electrodes 122 and 134.

The organic common layer 132 may include a hole injection layer (HIL), a hole transport layer (HTL), an emitting layer (EML), and an electron transport layer on the first electrode 122. (ETL) and an electron injection layer (EIL) are sequentially stacked.

The storage capacitor 125 is formed by overlapping the storage lower electrode 125a doped with p + or n + impurities and the storage upper electrode 125b with the second gate insulating layer 112b interposed therebetween. The storage capacitor 125 keeps the data signal charged in the first electrode 122 stable until the next data signal is charged.

The gate insulating layer 112 includes a first gate insulating layer 112a having a first thickness and a second gate insulating layer 112b having a second thickness thinner than the first thickness. In this case, the first and second gate insulating layers 112a and 112b are formed between the gate electrode 106 and the active layer 114, and the second gate insulating layer 112b includes the storage upper electrode 125b and the storage lower electrode ( 125a). The first gate insulating layer 112a is formed only in a region where the gate electrode 106 is formed, and the second gate insulating layer 112b is formed by applying the entire surface of the substrate 101. As such, the gate insulating layer 112 formed between the active layer 114 and the gate electrode 106 is formed in two layers to form a thick layer, and the gate insulating layer formed between the storage upper electrode 125b and the storage lower electrode 125a. 112 is thinly formed in one layer. As such, by forming a thin gate insulating layer 112 formed in the storage capacitor region, the area of the storage upper / lower electrodes 125a and 125b can be reduced, thereby ensuring an aperture ratio.

Specifically, the capacitor C has the following Equation 1, is proportional to the dielectric constant ε _r and the area A of the electrode, and has a relation inversely proportional to the thickness t of the gate insulating film. That is, as the thickness t of the gate insulating film is thinner, the value of the capacitor C is increased, and as the thickness t of the gate insulating film is thicker, the gate insulating film t and the capacitor C are decreased. ) Has an inverse relationship.

Meanwhile, in [Equation 1], ε _r means a relative dielectric constant, ε ₀ means a dielectric constant of vacuum, A means an area (cm ² ), and t means a thickness of a gate insulating film. do.

Accordingly, the thickness of the gate insulating layer 112 is formed in the storage capacitor region to increase the capacitor capacity while reducing the area A of the storage upper / lower electrodes 125a and 125b. As such, the area A of the storage upper / lower electrodes 125a and 125b may be reduced, thereby securing an aperture ratio.

In this case, the gate insulating layer 112 and the active layer 114 including the first and second gate insulating layers 112a and 112b are formed as one mask in the same process. Therefore, the area of the storage upper / lower electrodes 125a and 125b can be reduced without adding a process.

3A to 3G are cross-sectional views illustrating a method of manufacturing an organic light emitting display panel according to an exemplary embodiment of the present invention shown in FIG. 2.

Referring to FIG. 3A, a buffer film 116 is formed on a substrate 101, an active layer 114, a first gate insulating layer 112a having a first thickness, and a second having a second thickness. The gate insulating layer 112 including the gate insulating layer 112b and the storage lower electrode 125a are formed. This will be described with reference to FIGS. 4A to 4F.

In detail, as illustrated in FIG. 4A, the buffer layer 116 has an inorganic insulating material such as silicon oxide (SiO ₂ ) formed on the substrate 100 by a deposition method such as CVD or plasma enhanced chemical vapor deposition (PECVD). Is deposited and formed. The active layer 224 deposits amorphous silicon on the buffer layer 116 and then performs a dehydrogenaiton process to remove hydrogen atoms present in the amorphous silicon thin film. The amorphous silicon is then crystallized with a laser to become poly-silicon to form an active layer 114.

The first gate insulating layer 212 is formed by depositing an inorganic insulating material having a first thickness on the active layer 114 by a deposition method such as CVD or plasma enhanced chemical vapor deposition (PECVD).

As shown in FIG. 4B, the photoresist is applied on the first gate insulating layer 212, and then the photoresist is exposed and developed by a photolithography process using a slit mask or a halftone mask. Is formed.

Specifically, the halftone mask 170 includes a blocking region S1 having a blocking layer 172 formed on a substrate, and a semi-transmitting region S2 having a semi-transparent layer 174 formed on a substrate, as shown in FIG. 4B. ) And a transmission region S3 in which only a substrate exists.

The blocking region S1 is positioned in a region where the gate electrode 106 is to be formed to block ultraviolet rays, thereby leaving the first photoresist pattern 220a after development, as shown in FIG. 4B. The semi-transmissive region S2 is a second photo thinner than the first photoresist pattern 220a as shown in FIG. 4B after the semi-transmissive layer 174 is stacked on the region where the storage capacitor 125 is to be formed to control light transmittance. The resist pattern 220b is left. The transmissive region S3 transmits all the ultraviolet rays so that the photoresist is removed as shown in FIG. 4B after development.

As shown in FIG. 4C, the first gate insulating layer 212 and the active layer 224 are patterned by an etching process using the first and second photoresist patterns 220a and 220b having different thicknesses, thereby lowering the storage lower electrode 125a. ) Is formed.

Subsequently, the first photoresist pattern 220a is thinned by ashing the first and second photoresist patterns 220a and 220b by an ashing process using an oxygen (O ₂ ) plasma as shown in FIG. 4D. Pattern 220b is allowed to be removed.

Thereafter, as illustrated in FIG. 4E, the first gate insulating layer 112a exposed by the etching process using the ashed first photoresist pattern 220a is removed. Accordingly, only the active layer 114 remains in the region where the storage capacitor is to be formed, and the active layer 114 and the first gate insulating layer 112a remain in the region where the gate electrode 106 is to be formed. In this case, the exposed storage lower electrode 125a is doped with n + or p + impurities to become conductive, and the first photoresist pattern 220a remaining on the first gate insulating layer 112a is removed by a strip process.

Next, as shown in FIG. 4F, only the first gate insulating layer 112a is formed in the storage capacitor 125 region by applying the entire surface of the second gate insulating layer 112b having a thickness smaller than that of the first insulating layer 112a. First and second gate insulating layers 112a and 112b are formed in the region where the gate electrode 106 is to be formed.

Referring to FIG. 3B, a gate insulating layer 112 is formed on the buffer layer 116 on which the active layer 114 is formed, and a gate electrode 106 and a storage upper electrode 125b are formed thereon, and an active layer ( The source region 114S and the drain region 114D facing each other with the channel region 114C of the 114 therebetween are formed.

Specifically, the gate metal layer is formed on the second gate insulating layer 112b through a deposition method such as a sputtering method. As the gate metal layer, molybdenum (Mo), aluminum (Al), chromium (Cr) and the like and alloys thereof are laminated and used in a single layer or a multilayer structure. Then, the gate metal layer is patterned by a photolithography process and an etching process using a second mask to form the gate electrode 106 and the storage upper electrode 125b.

In this case, the gate electrode 106 overlaps the active layer 114 with the first and second gate insulating layers 112a and 112b interposed therebetween, and the storage upper electrode 125b has the second gate insulating layer 112b interposed therebetween. And overlap the lower storage electrode 125a.

The source region 114S and the drain region 114D of the active layer doped with the n + impurity are formed by doping the n + impurity into the active layer 114 which is not overlapped with the gate electrode 106 using the gate electrode 106 as a mask. Is formed.

Referring to FIG. 3C, an interlayer insulating layer 126 is formed on the gate insulating layer 112 on which the gate electrode 106 is formed, and passes through the first and second gate insulating layers 112a and 112b and the interlayer insulating layer 126. Source and drain contact holes 124S and 124D are formed.

Specifically, the interlayer insulating film 126 is formed by depositing an inorganic insulating material such as silicon oxide, silicon nitride, or the like on the gate insulating film 112 on which the gate electrode 106 is formed by a deposition method such as PECVD or CVD. Subsequently, source and drain contact holes 124S and 124D penetrating through the first and second gate insulating layers 112a and 112b and the interlayer insulating layer 126 are formed by a photolithography process and an etching process using a third mask. Source and drain contact holes 124S and 124D expose source and drain regions 114S, 114D, 214S and 214D.

Referring to FIG. 3D, source and drain electrodes 108 and 110 are formed on the substrate 101 on which the interlayer insulating layer 126 is formed.

Specifically, the source and drain metal layers are formed on the interlayer insulating layer 126 by a deposition method such as sputtering, and then the source and drain metal layers are patterned by a photolithography process and an etching process using a fourth mask. The drain electrode 110 is formed. The source electrode 108 and the drain electrode 110 are connected to the source region and the drain region 114S and 114D of the active layer 114 through the source and drain contact holes 124S and 124D, respectively.

Referring to FIG. 3E, the passivation layer 118 including the pixel contact hole 120 is formed on the substrate 101 on which the source and drain electrodes 108 and 110 are formed.

Specifically, the protective film 119 is formed by PECVD or CVD on the substrate 101 on which the source and drain electrodes 108 and 110 are formed. The passivation layer 118 may be formed of an inorganic insulating material or an organic insulating material, and may be formed of two layers to be made of an inorganic insulating material and an organic insulating material. The passivation layer 118 is patterned by a photolithography process and an etching process using a fifth mask to form the pixel contact hole 120 penetrating the passivation layer 118. The pixel contact hole 120 exposes the drain electrode 110.

Referring to FIG. 3F, the first electrode 122 of the organic light emitting diode that is in direct contact with the drain electrode 110 of the driving thin film transistor TD is formed.

Specifically, TCO (Transparent Conductive Oxide; TCO), ITO (Indium Tin Oxide (ITO), ITO), IZO (Indum Zinc Oxide; After forming the transparent conductive electrode layer, the first electrode 122 is formed by patterning the transparent conductive electrode layer by a photolithography process and an etching process using a sixth mask.

Referring to FIG. 3G, a bank insulating layer 130 having a bank hole 135 is formed on the substrate 101 on which the first electrode 122 is formed.

In detail, an organic insulating material such as an acrylic resin is entirely formed on the substrate 101 on which the first electrode 122 is formed through a coating method such as spinless or spin coating. Thereafter, the organic insulating material is patterned in the photolithography process and the etching process using the seventh mask to expose the first electrode 122 penetrating the bank insulating layer 130 including the bank hole 135.

Referring to FIG. 3H, an organic common layer 132 and a second electrode 134 are formed on the first electrode 122.

Specifically, a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (Electron Transport Layer) using a shadow mask in the bank hole 135; ETL) and electron injection layer (EIL) are sequentially stacked to form an organic common layer 132. Thereafter, a second highly reflective second electrode 134 such as aluminum (Al) is deposited on the substrate 101 on which the organic common layer 132 is formed.

The foregoing description is merely illustrative of the present invention, and various modifications may be made by those skilled in the art without departing from the spirit of the present invention. Accordingly, the embodiments disclosed in the specification of the present invention are not intended to limit the present invention. The scope of the present invention should be construed according to the following claims, and all the techniques within the scope of equivalents should be construed as being included in the scope of the present invention.

101: substrate 108: source electrode
110: drain electrode 112a; First gate insulating film
112b: second gate insulating film 114: active layer
116: buffer film 120: pixel contact hole
122: first electrode 124S: source contact hole
124D: Drain contact hole 126: Interlayer insulating film
130: bank insulating film 132: organic common layer
134: second electrode

Claims (9)

A buffer film and an active layer formed on the substrate;
A gate insulating film including a first gate insulating film of a first thickness and a second gate insulating film of a second thickness on the active layer;
A gate electrode overlapping the active layer with the first and second gate insulating layers interposed therebetween;
An interlayer insulating film formed on the gate electrode;
A source contact hole and a drain contact hole formed to penetrate the first and second gate insulating layers and the interlayer insulating layer to expose the source and drain regions of the active layer;
Source and drain electrodes formed on the source and drain contact holes to be connected to the source and drain regions of the active layer, respectively;
An organic electroluminescent device comprising a first electrode connected to the drain electrode, an organic common layer formed on the first electrode, and a second electrode formed to face the first electrode;
And a storage capacitor formed by overlapping a storage upper electrode and a storage lower electrode with the second gate insulating layer interposed therebetween. The method of claim 1,
The second gate insulating layer is thicker than the first gate insulating layer. The method of claim 1,
And the first gate insulating layer is formed only in a region where the gate electrode is formed, and the second gate insulating layer is formed on the entire surface of the substrate. The method of claim 1,
The buffer layer, the active layer, and the first and second gate insulating layers are formed in the same process. Forming a gate insulating film including a buffer film and an active layer, a first gate insulating film having a first thickness, a second gate insulating film having a second thickness, and a storage lower electrode on the substrate;
Forming a gate electrode to overlap the active layer with the first and second gate insulating layers interposed therebetween, and forming a storage upper electrode to overlap the lower storage with the second gate insulating layer interposed therebetween;
Forming an interlayer insulating layer on the substrate on which the gate electrode and the storage upper electrode are formed, and forming source and drain contact holes penetrating the first and second gate insulating layers and the interlayer insulating layer;
Forming a source and a drain electrode in each of the source and drain contact holes;
Forming a first electrode connected to the drain electrode;
Forming an organic common layer and a second electrode on the first electrode. The method of claim 5,
Forming a gate insulating layer including a buffer layer and an active layer, a first gate insulating layer having a first thickness, a second gate insulating layer having a second thickness, and a storage lower electrode on the substrate
Forming a buffer film, an active layer, and a first gate insulating film of the first thickness on the substrate;
Forming a first photoresist pattern and a second photoresist thinner than the first photoresist pattern on the first gate insulating layer;
Forming a lower storage electrode by patterning the active layer and the first gate insulating layer by an etching process using the first and second photoresist patterns;
Thinning the first photoresist pattern and removing the second photoresist pattern by ashing the first and second photoresist patterns;
Removing the first gate insulating layer exposed by the etching process using the first photoresist pattern, and then doping impurities into the lower storage electrode to make the conductive layer conductive;
And removing the remaining first photoresist and then applying the entire surface of the second gate insulating layer having the second thickness. The method according to claim 6,
And forming the first and second gate insulating layers on the active layer, and forming the second gate insulating layer on the storage lower electrode. The method according to claim 6,
And the second gate insulating layer is thicker than the first gate insulating layer. The method of claim 5,
The buffer layer, the active layer, and the first and second gate insulating layers are formed in the same process.

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