KR20120116842A - System and method to overcome wander accumulation to achieve precision clock distribution over large networks - Google Patents

Abstract

Systems and methods for synchronizing clocks across a packet switching network eliminate the need for accumulation and enable precise clock distribution across large networks. In addition to the standard precision time protocol (PTP) synchronization message or similar time synchronization message, each clock regenerator stage receives a generic clock error message from a previous stage, updates this error message with its own stage clock error, and updates it. The aggregated clock error to be transmitted to the next stage. This enables a synchronization algorithm to compensate for the error of the previous stage, effectively allowing each clock regenerator to lock directly to the overall master clock.

Description

SYSTEM AND METHOD TO COVER WONDER COLLECTION TO ACHIEVE PRECISION CLOCK DISTRIBUTION ON LARGE NETWORKS TECHNICAL AND METHOD TO OVERCOME WANDER ACCUMULATION TO ACHIEVE

[preference]

This application claims priority to US Provisional Patent Application No. 61 / 475,080, filed April 13, 2011, entitled 35 U.S.C. Claimed under § 119 (e), the subject matter of which is incorporated herein by reference in its entirety.

The present invention generally relates to the field of clock distribution on packet-switched networks. More specifically, the present invention relates to systems and methods for overcoming wonder accumulation such that clock signals can be distributed over large networks with high precision.

Synchronizing the elements that make up a network is fundamentally important to achieve good network performance. This is especially true for telecommunication systems and control systems where all nodes and users need to maintain good synchronization with each other. As more systems become Internet Protocol (IP) based, the need for high precision time distribution only increases.

In general, synchronizing clocks over a network requires distributing timing information from the master clock to multiple slave clocks throughout the network. However, variable latency and traffic dependent delay make this distribution scheme challenging in the context of packet-based networks. Accordingly, the Precision Time Protocol IEEE-1588 standard has emerged as one way to address many of the problems associated with packet-based time synchronization of network elements. PTP copes with time transfer latency that occurs as time packet and data packet traffic travels through hubs, switches, cables, and other hardware that forms a network.

PTP operates using the master-slave concept. The master is equipped with a high precision clock such as an atomic clock. The master and slave devices exchange data packets that allow the slave device to lock to a master clock reference. For example, Figure 1 describes a basic PTP packet exchange process for transmitting timing information. The master unit 102 sends a synchronization message 106 at regular intervals. The slave device 104 receives the synchronization message 106 with a time stamp and immediately sends a delay request packet 108 back to the master 102. In response, the master responds with a delay response packet 110. Receiving a synchronization message allows the slave to align its local timebase with the frequency of the master clock, and additional delay request and delay response packets add the slave's local clock phase to the master clock to complete the synchronization. Enable sorting. Other synchronization methods, such as the Network Time Protocol (NTP) 4th Edition, are also used in the art. Implementation details differ from PTP, but NTP also relies on timing message exchanges from master to slave and from slave to master to achieve synchronization.

As described above, the slave clock fixed to the master clock is known as an ordinary clock. The PTP protocol also defines a boundary clock. The boundary clock normally functions as a clock, but in addition it also serves as a master clock for other downstream normal or boundary clocks. Thus, such a chain of boundary clocks provides a method for distributing grand master clock references across very large networks. For example, FIG. 2 shows the collective master clock 202 networked with four boundary clocks 204, 206, 208 and 210. The overall master clock 202 and the first boundary clock 204 exchange PTP packets 212 to phase lock the first boundary clock 204 to the master clock 202. The boundary clock 206 is fixed to the boundary clock 204 via the PTP packet exchange 214 in the same manner. The third and fourth boundary clocks 208 and 210 are fixed to the preceding boundary clock by the exchange of PTP packets 216 and 218 in the same manner. The last boundary clock 210 is thus fixed to the overall master clock 202 through all intermediate boundary clocks.

This method works well for some applications where the number of boundary clocks in the chain is very small, but does not achieve sufficient precision for many other applications. The problem with this architecture is that each boundary clock introduces a certain amount of clock error. The error introduced by each boundary clock is propagated along the next boundary clock in the chain so that the overall error continues to increase. For the back clocks in the distribution chain, the error can increase to an unacceptable size. This problem is particularly acute in the case of very large networks that may involve many boundary clock stages. Thus, it would be advantageous to provide a system and method for eliminating the accumulation of boundary clock errors to enable precise clock distribution over large networks.

The present invention relates to a system and method for synchronizing clock regenerators to overcome wonder accumulation. An example of a clock regenerator is a boundary clock in a packet switched internet protocol network. However, the present systems and methods may equally be applied to telecommunication networks and any other type of network that requires precise time distribution.

Embodiments of a clock synchronization system for use in a network according to the present invention include a general master clock with a precision timing source and at least first and second clock regenerators. The first clock regenerator is coupled to the overall master clock and includes a first synchronization processing unit for synchronizing the first local clock and the first local clock to the overall master clock. The first synchronization processing unit is configured to receive a master to slave message from the collective master clock and send the slave to master message back to the master clock. The synchronization processing unit uses these messages to calculate the first master to slave path delay and the first slave to master path delay. The first synchronization processing unit is further configured to calculate a first stage clock error that is one half of the difference between the first slave to master path delay and the first master to slave path delay. The first synchronization processing unit is further configured to calculate a first global clock error that is the sum of the first stage clock error and the global clock baseline error. The global clock baseline error is defined as zero. In some embodiments, the overall master clock is configured to send an overall clock baseline error to the first clock regenerator. However, in other embodiments, the global clock baseline error is generated by the first clock regenerator itself. The first synchronization processing unit is further configured to synchronize the first local clock to the overall master clock using the first stage clock error and the overall clock baseline error.

While synchronization messages and delayed response messages are discussed with reference to the PTP protocol, it should be understood that the present invention is not limited to systems implementing such standards. Synchronization and delay response messages discussed herein are intended to encompass other message formats and protocols for achieving synchronization in a similar manner. For example, the systems and methods described herein apply equally to similar protocols and mechanisms for time synchronization, such as the "Network Time Protocol" (NTP) 4th Edition and other similar methods.

The embodiment further includes a second clock regenerator operatively coupled to the first clock regenerator and including a second local clock and a second synchronization processing unit. The second synchronization processing unit is configured to receive the synchronization message and the delay response message from the first clock regenerator. It is further configured to receive a first global clock error from the first clock regenerator. The second synchronization processing unit is further configured to calculate a second stage clock error based on the information from the synchronization and delay response message. It is configured to synchronize the second local clock to the overall master clock based at least in part on the second stage clock error and the first overall clock error.

In some embodiments, the overall clock error needs to be quantized for storage in the clock regenerator and transfer between different clock regenerators. The aggregate clock error can be quantized to 64 bits, 32 bits, or less to save system resources while maintaining their precision at a predetermined level. In another embodiment, each global clock error may be packaged together with one of the existing PTP messages, such as a delay response message within the scope of the TLV extension defined in the PTP standard, which are together as part of a single message. Can be sent to the next clock regenerator stage to be sent.

In some embodiments, the processing element in the clock regenerator stage includes a speed control unit. The speed control unit selectively controls the frequency at which the overall clock error calculated at the clock regenerator stage is transmitted to the next clock regenerator. The rate at which the aggregate clock error is transmitted may be a fixed rate or a variable rate.

In another embodiment, the processing element in the clock regenerator stage further includes a time-out unit. The timeout unit is configured to include a memory and a timeout counter for storing the aggregate clock error received from the previous stage. The timeout counter is reset to its initial value whenever a global clock error is received from the previous stage. The timeout counter then counts down from the initial value at a fixed rate. The total clock error stored in memory will be used to synchronize the clock regenerator stage unless the timeout counter reaches zero. In other words, the timeout unit ensures that the clock regenerator is using the aggregate clock error signal no later than a certain configurable time.

An embodiment of the method for synchronizing N master clocks with N (N is an integer greater than 1) clock in a network according to the invention comprises the steps described below. The method includes sending a synchronization message from the master master clock to the first clock regenerator and sending a delay response message from the master master clock to the first clock regenerator. In a first clock regenerator, the method includes calculating a first master to slave path delay based at least in part on a synchronization message; Calculating a first slave to master path delay based at least in part on the delay response message; Calculating a first stage clock error that is one half of the difference between the first slave to master path delay and the first master to slave path delay; Generating a first global clock error that is the sum of the first stage clock error and the global clock baseline error (the global clock baseline error is set to zero); And synchronizing the first clock regenerator to the overall master clock based at least in part on the first stage clock error and the overall clock baseline error.

Similar processes follow at each clock regenerator stage. For example, in a k-th (k is an integer between 1 and N) clock regenerator, the method includes receiving a synchronization message from a k-1 th clock regenerator; receiving a delay response message from a k-1 th clock regenerator; receiving a k-1 th overall clock error from a k-1 th clock regenerator; calculating a k-th master to slave path delay based at least in part on the synchronization message from the k-th clock regenerator; calculating a kth slave to master path delay based at least in part on a delay response message from the k−1 th clock regenerator; calculating a k th stage clock error that is one half of the difference between the k th slave to master path delay and the k th master to slave path delay; calculating a k th overall clock error, which is the sum of the k th stage clock error and the k-1 th overall clock error; And synchronizing the k-th clock regenerator to the overall master clock based at least in part on the k-th stage clock error and the k-1 th overall clock error.

And finally, at the N-th (last) clock regenerator, the method includes receiving a synchronization message from the N-th clock regenerator; Receiving a delay response message from the N-1 < th > clock regenerator; Receiving an N-1 th overall clock error from an N-1 th clock regenerator; Calculating an N-th master to slave path delay based at least in part on the synchronization message from the N-th clock regenerator; Calculating an Nth slave to master path delay based at least in part on a delay response message from the N-1th clock regenerator; Calculating an Nth stage clock error that is one half of the difference between the Nth slave to master path delay and the Nth master to slave path delay; And synchronizing the N th clock regenerator to the overall master clock based at least in part on the N th stage clock error and the N-1 th overall clock error. This method allows each of the N clock regenerators to be synchronized directly to the overall master clock.

Another embodiment of a method for synchronizing N master clock regenerators with a master master clock may include configuring the master master clock to generate an overall clock baseline error and send it to the first clock regenerator. . Different embodiments may include generating an aggregate clock baseline error in the first clock regenerator. And some embodiments may include quantizing the global clock error to 32 bits or less in each clock regenerator to save system resources.

Other embodiments and applications according to the present invention will also become apparent by considering the following detailed description of the preferred embodiment and the accompanying drawings, which will first be described briefly.

1 illustrates an exemplary synchronization packet exchange between a master and a slave node in an implementation of the PTP protocol.
2 is a block diagram illustrating synchronizing several clock regenerators to a master clock in accordance with an exemplary implementation of the PTP protocol.
3 is a block diagram of an embodiment of a clock synchronization system in accordance with the present invention.

The present invention provides an apparatus and method for removing wonder accumulation in a network to enable precise clock distribution across a large network. Unlike standard PTP networks, where each boundary clock is synchronized directly to the preceding boundary clock and thus indirectly to the overall master clock, embodiments of the network according to the present invention provide each clock by distributing additional error signals through the network. The regenerator is effectively synchronized to the overall master criteria itself.

3 is a block diagram of a clock synchronization system according to an embodiment of the present invention. Although this embodiment is described with reference to a PTP network that includes a boundary clock, this is generally applicable to other types of networks that include a clock regenerator to be synchronized to the overall master clock reference. The master master clock 302 contains the main precision timing source to which the network is to be synchronized. The first boundary clock 304 is fixed to the overall master 302 using conventional PTP slave synchronization algorithm 320 and standard PTP packet exchange 322. The first boundary clock 304 calculates its clock error relative to the immediately previous clock (in this case, the overall master) and generates its "stage clock error" 314. In a standard PTP implementation, this stage clock error will be used directly to drive the phase locked loop of the boundary clock stage. However, in this case, the boundary clock 304 also receives an additional "collective clock error" signal 312. This overall clock error signal is summed with the stage clock error 314 to produce a combined clock error for driving the satellite fixed loop at 316, the sum also being the updated overall clock error signal 318 as the next boundary clock 306. Is delivered). The overall clock error 318 supplied to the next boundary clock 306 thus includes a measure of the error for the overall master of the boundary clock 304.

By definition, global clock baseline error signal 312 is assigned a fixed value of zero since it originates from global master 302. Each subsequent boundary clock receives both a standard PTP packet and an overall clock error signal that effectively represents any error introduced by the preceding stage. For example, the boundary clock i 309 exchanges the PTP packet 348 with the boundary clock i-1 308 and receives the aggregate clock error signal 346 from the boundary clock i-1. Mathematically, the process can be described as follows.

Here, GrandClockError (i-1) is the overall clock error received by the i th boundary clock, and GrandClockError (i) is the updated overall clock error signal sent by the i th boundary clock. StageClockError (i) is the stage clock error of the i th boundary clock. As with any standard PTP slave algorithm, s2mDelay (i) is a slave to master path delay obtained from a typical “delay response” message, and m2sDelay (i) is a typical “sync” message for the i th boundary clock. The master to slave path delay obtained.

While synchronization messages and delayed response messages are discussed with reference to the PTP protocol, it should be understood that the present invention is not limited to systems implementing such standards. Synchronization and delay response messages discussed herein are intended to encompass other message formats and protocols for achieving synchronization in a similar manner. For example, the systems and methods described herein apply equally to similar protocols and mechanisms for time synchronization, such as the "Network Time Protocol" (NTP) 4th Edition and other similar methods.

The n th boundary clock 310 receives a global clock error 356 from the i th boundary clock 309 and also receives a standard PTP message 364 from the i th boundary clock. The aggregate clock error 356 is added to the n th stage clock error 360 and used as the feedback signal 362 for the n th PTP synchronization loop 358. Since the global clock error signal 356 has been updated at each intervening stage, not only the last n th boundary clock 310, but all other leading boundary clocks are essentially fixed directly to the global master 302 itself.

In the embodiments described above, the overall master 302 outputs an initial overall clock error signal 312 as shown in equation (1). However, in other embodiments, the overall master may not be configured to support or output the overall clock error signal, such as products of different manufacturers. In such a case, the first boundary clock must detect the aggregate clock error signal by examining the message format or through any other mechanism known in the art. The first boundary clock will then simply use its stage clock error as the updated overall clock error 318 and pass it to the second boundary clock 306. Such embodiments will also fall within the scope and spirit of the art.

The calculation of StageClockError (i) shown in Equation 2 is merely an example. Those skilled in the art will also recognize other changes or algorithms to mitigate the effects of packet delay variations, which will also fall within the scope and spirit of the present invention.

Under normal operation of the network according to an embodiment of the present invention, all boundary clocks receive, update, and transmit the aggregate clock error in accordance with Equations 2 and 3 below. This makes each boundary clock "invisible" to each other, and any error introduced by each boundary clock is reflected in the overall clock error signal, which can then be removed by a simple algorithm by subsequent normal or boundary clocks. In the sense that it is. In some embodiments, an individual boundary clock may assume that its own stage clock error is unreliable for some reason. In such a case, it may choose to simply convey the received global clock error instead of updating the received global clock error with its own stage clock error. In doing so, the error associated with this particular boundary clock will be "visible" for subsequent boundary clock stages, even though subsequent stages will still be invisible to each other. In other words, subsequent boundary clocks will only receive errors for the visible boundary clock stage and its boundary clock stage. Once the visible boundary clock returns to normal operation and begins delivering an updated overall clock error that includes its own stage clock error, it will be invisible once again. The downstream clocks will then all be locked to the master master 302 once again. Thus, the disclosed fixed configurations and methods are effective and stable. While the embodiments described above assume that all boundary clocks are “invisible” in the sense described above, other embodiments in which some boundary clocks are “visible” are also possible, and these embodiments are also contemplated by the scope and spirit of the present invention. Will belong.

In particular, in one embodiment, the processing element in the boundary clock stage includes a timeout unit. The timeout unit is configured to include a memory and a timeout counter for storing the aggregate clock error received from the previous stage. The timeout counter is reset to its initial value whenever a global clock error is received from the previous stage. The timeout counter then counts down from the initial value at a fixed rate. The global clock error stored in memory will be used to synchronize its boundary clock stages unless the timeout counter reaches zero. In other words, the timeout unit ensures that the boundary clock is using the aggregate clock error signal no later than a certain configurable time.

The calculation of GrandClockError (i) shown in Equation 3 is merely an example. Those skilled in the art will also recognize other variations or algorithms to achieve a good estimate of the clock error for the overall master 302 of the boundary clock i 309, which will also fall within the scope and spirit of the present invention. .

In addition, calculating and transmitting any other type of clock error information between the boundary clocks to eliminate or reduce the boundary clock error accumulation will also fall within the scope and spirit of the present invention.

In the preferred embodiment, the overall clock error should be transmitted at a speed fast enough for the slave lock algorithm to work effectively. In other words, the time it takes for the first global clock error sent by the first stage boundary clock to reach the final stage boundary clock is such that the final boundary clock is fixed to the global master accurately and based on its slave tracking algorithm. It should be small enough to be able to. For example, if the aggregate clock error is sent by each boundary clock at a rate of 30 times per second, the longest time for the aggregate clock error of the first boundary clock to reach the thirtieth stage is approximately one second. This time delay is short enough for many phase locked loop based PTP slave algorithms. Thus, in principle, the desired transmission rate of the aggregate clock error signal will depend on the maximum number of boundary clocks involved in the serial concatenation. Although implementations regarding 30 stages and a total clock error rate of 30 Hz have been discussed above, other embodiments are possible and will likewise fall within the scope and spirit of the present invention. In particular, embodiments with a first stage to nth stage delay other than 1 second are also possible.

In another preferred embodiment, the overall clock error is maintained with sufficient precision while limiting the total number of bits needed to store and transmit the overall clock error to save system resources. In one embodiment, the overall clock error is measured in nanoseconds and multiplied by 256. This provides a total bone clock error precision of 1/256 nanoseconds. The total number of bits used to represent the aggregate clock error is set to 64 bits. In other embodiments, the number of bits may be reduced to 32 or more. Embodiments with other precision values will also fall within the scope and spirit of the present invention.

In one embodiment, the aggregate clock error is distributed between the boundary clocks as a special additional packet or message. In other embodiments, this may be added to existing network messages. For example, within the PTP standard, TLV extensions can be added to existing "delay response" messages and used to convey a generic clock error message. In addition, the TLV extension may be sent every "delay response" message or every few "delay response" messages to reduce bandwidth consumption. Other methods of distributing aggregate clock error information at fixed or variable rates are also possible and would fall within the scope and spirit of the present invention.

Some embodiments of apparatus and methods for removing wonder accumulation in a network have been described above. Those skilled in the art will also recognize other variations, embodiments, and applications of the system for improving the precision of distributed timing criteria, which will also fall within the scope and spirit of the present invention.

Claims (19)

A clock synchronization system for use in a network,
A grand master clock, a first clock regenerator and a second clock regenerator,
The master master clock includes the main precision timing source,
The first clock regenerator is operably connected to the collective master clock and the second clock regenerator,
The first clock regenerator includes a first synchronization processing unit for synchronizing a first local clock and the first local clock with the overall master clock;
The first synchronization processing unit,
Receive a first master to slave message from the overall master clock,
Send a first slave to master message to the overall master clock,
Calculate a first master to slave path delay and a first slave to master path delay based at least in part on the first master to slave message and the first slave to master message,
Calculate a first stage clock error that is one half of the difference between the first slave to master path delay and the first master to slave path delay,
Generate a first global clock error that is the sum of the first stage clock error and a global clock baseline error, wherein the global clock baseline error is set to zero;
Synchronize the first local clock to the global master clock based at least in part on the first stage clock error and the global clock baseline error,
Send the first global clock error to the second clock regenerator,
The second clock regenerator is operably connected to the first clock regenerator,
The second clock regenerator includes a second synchronization processing unit for synchronizing a second local clock and the second local clock with the overall master clock;
The second synchronization processing unit,
Receive a second synchronization message from the first clock regenerator,
Receive a second delay response message from the first clock regenerator,
Receive and store the first global clock error from the first clock regenerator,
Calculate a second master to slave path delay based at least in part on the second synchronization message,
Calculate a second slave to master path delay based at least in part on the second delay response message,
Calculate a second stage clock error that is one half of the difference between the second slave to master path delay and the second master to slave path delay,
Calculate a second total clock error that is the sum of the first general clock error and the second stage clock error,
And synchronize the second local clock to the overall master clock based at least in part on the second stage clock error and the first overall clock error. The method of claim 1,
The global master clock is further configured to generate the global clock baseline error and to send the global clock baseline error to the first clock regenerator. The method of claim 1,
And the first clock regenerator is further configured to generate the global clock baseline error. The method of claim 1,
And the first synchronization processing unit includes a memory element for storing the first global clock error. The method of claim 1,
And the first synchronization processing unit is further configured to quantize the first global clock error to 32 bits or less. The method of claim 1,
And the first global clock error is packaged with the second delay response message to be received by the second clock regenerator. Clock synchronization system for use in a network having an overall master clock and N clock regenerators, where N is an integer greater than 1,
A first clock regenerator operably connected to the master master clock;
kth clock regenerator, where k is an integer between 1 and N; And
Nth clock regenerator operatively connected to the N-1th clock regenerator
Including,
The k-th clock regenerator,
an operational connection to the k-1 th clock regenerator;
an operational connection to the k + 1 th clock regenerator; And
Synchronization processing unit
/ RTI >
The synchronization processing unit,
Receive a master to slave message from the k-1 th clock regenerator,
Send a slave-to-master message to the k-1 th clock regenerator,
Calculate a kth master to slave path delay and a kth slave to master path delay based at least in part on the master to slave message and the slave to master message,
Calculate a kth stage clock error that is one half of the difference between the kth slave to master path delay and the kth master to slave path delay,
Receive a k-1 th overall clock error from the k-1 th clock regenerator,
Calculating a k-th overall clock error, which is the sum of the k-1 th overall clock error and the k-th stage clock error,
Synchronize the k th clock regenerator to the overall master clock based at least in part on the k th stage clock error and the k-1 th overall clock error;
And a k th processing element configured to send the k th overall clock error to the k + 1 th clock regenerator. The method of claim 7, wherein
And the k th processing element comprises a memory element for storing the k-1 th overall clock error. The method of claim 7, wherein
And the synchronization processing unit is further configured to quantize the k-th overall clock error to 32 bits or less. The method of claim 7, wherein
The kth processing element is further configured to combine them into packets such that the kth overall clock error and a delay response message for the k + 1 th clock regenerator are sent together with the k + 1 th clock regenerator system. The method of claim 7, wherein
And the k th processing element further comprises a speed control unit configured to selectively control the frequency at which the k th overall clock error is transmitted to the k + 1 th clock regenerator. The method of claim 7, wherein
The kth processing element further comprises a timeout unit having a memory for storing the k−1th overall clock error and a timeout counter that is decremented from an initial value,
The timeout unit updates the memory such that the timeout unit stores the received k−1th overall clock error whenever the k−1th overall clock error is received, and sets the timeout counter to the initial value. And use the k-1 th overall clock error to synchronize the k th clock regenerator to the overall master clock unless the timeout counter reaches zero. A method of synchronizing each of said N clock regenerators to said overall master clock in a network comprising a global master clock and N clock regenerators, where N is an integer greater than 1,
Sending a master to slave message from the master master clock to a first clock regenerator;
Sending a slave to master message from the first clock regenerator to the overall master clock;
In the first clock regenerator,
Calculating a first master to slave path delay and a first slave to master path delay based at least in part on the master to slave message and the slave to master message;
Calculating a first stage clock error that is one half of the difference between the first slave to master path delay and the first master to slave path delay;
Generating a first global clock error that is the sum of the first stage clock error and the global clock baseline error, wherein the global clock baseline error is set to zero; And
Synchronizing the first clock regenerator to the global master clock based at least in part on the first stage clock error and the global clock baseline error
Performing;
in k th clock regenerator-k is an integer greater than 1 and less than N-,
receiving a master to slave message from a k-1 th clock regenerator;
Sending a slave to master message to the k-1 th clock regenerator;
Receiving and storing a k-1 th overall clock error from the k-1 th clock regenerator;
Calculating a k-th master-to-slave path delay and a k-th slave-to-master path delay based at least in part on the master to slave message and the slave to master message;
Calculating a kth stage clock error that is one half of the difference between the kth slave to master path delay and the kth master to slave path delay;
Calculating a k-th overall clock error, which is the sum of the k-th stage clock error and the k-1 th overall clock error; And
Synchronizing the k th clock regenerator to the overall master clock based at least in part on the k th stage clock error and the k-1 th overall clock error
Performing a synchronization process comprising; And
In the Nth clock regenerator,
Receiving a master to slave message from an N-1 th clock regenerator;
Sending a slave-to-master message to the N-1 th clock regenerator;
Receiving and storing an N-1 th overall clock error from the N-1 th clock regenerator;
Calculating an Nth master to slave path delay and an Nth slave to master path delay based at least in part on the master to slave message and the slave to master message;
Calculating an Nth stage clock error that is one half of the difference between the Nth slave to master path delay and the Nth master to slave path delay; And
Synchronizing the N th clock regenerator to the overall master clock based at least in part on the N th stage clock error and the N-1 th overall clock error;
Steps to perform
≪ / RTI > The method of claim 13,
At the k th clock regenerator, packing the k th overall clock error into a message and sending the message to the k + 1 th clock regenerator. 15. The method of claim 14,
Sending the message to the k + 1 th clock regenerator is performed at a fixed rate. 15. The method of claim 14,
Sending the message to the k + 1 th clock regenerator is performed at a variable rate. The method of claim 13,
Configuring the global master clock to generate the global clock baseline error and to send the global clock baseline error to the first clock regenerator. The method of claim 13,
Generating the global clock baseline error in the first clock regenerator. The method of claim 13,
Quantizing the global clock error to 32 bits or less in each clock regenerator.

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