KR20120020311A - Circuit and method for delaying internal write signal of memory device - Google Patents

Abstract

An internal write signal delay circuit is disclosed. The internal write signal delay circuit may include a latency controller configured to delay a write signal activated by a column address strobe signal by a write latency to generate a latency signal, and to activate an internal clock from an activation point of the write signal to an activation point of the latency signal. An internal clock generator and a delay output unit configured to delay and output an internal light signal activated by the write signal in synchronization with the internal clock.

Description

Internal write signal delay circuit and delay method of memory device {CIRCUIT AND METHOD FOR DELAYING INTERNAL WRITE SIGNAL OF MEMORY DEVICE}

The present invention relates to an internal write signal delay circuit and a delay method for reducing power consumption of a semiconductor memory device.

Generally, a semiconductor memory device includes a command decoder for activating internal signals of a memory device according to a command from a system, a core region including memory cell arrays for storing data, and input / output of actual data. This includes the DQ region.

The column address strobe signal CAS applied to the command decoder may generate a read or write command for inputting / outputting data from the memory device. Specifically, when the column address strobe signal CAS is activated 'high' and the write enable signal WE is deactivated 'low', data is read from the core area and out of memory. When the read signal CASRD for output is activated 'high' and the column address strobe (CAS) signal and the write enable signal WE are simultaneously activated 'high', data is received from the outside of the memory and stored in the core area. The write signal CASWT is activated to 'high'. In addition, when the write signal CASWT is activated, the internal write signal WTDQ applied to the DQ region is activated 'high' to receive the actual data from the DQ region.

Here, the actual data input to the DQ region occurs after a predetermined time has passed since the write signal CASWT is activated, and this time is referred to as write latency (WL).

1 is a block diagram of a conventional internal write signal delay circuit.

Referring to FIG. 1, a conventional internal write signal delay circuit may include an internal clock generator 101 generating an internal clock ICLK from an activation time of a column address strobe signal CAS to an activation time of an idle signal IDLE. And a delay output unit 103 that operates in synchronization with the generated internal clock ICLK. In this embodiment, WL = 4 clocks.

First, the internal write signal WTDQ is input to the delay output unit 103 at a time point 3.5 clock ahead of the start point of the write operation (data input time point) in the actual DQ region, and the second output signal is provided via the delay output unit 103. The delayed signal is output as the delayed internal write signal WTDQ_15. To this end, the delay output unit 103 may include two D flip-flops (not shown) that operate in synchronization with the internal clock ICLK. The delayed internal write signal WTDQ_15 is transferred to the DQ region 1.5 times ahead of the actual write start time, in order to provide a time allowance to prepare for receiving data input from the DQ region.

2 is a diagram illustrating an internal configuration of the internal clock generator 101 of FIG. 1.

Referring to FIG. 2, the internal clock generator 101 includes an SR latch for activating the clock control signal CLKCTRL using the column address strobe signal CAS, the reset signal RST, and the idle signal IDLE. do. Referring to the operation of the SR latch, the clock control signal CLKCTRL is activated by activating the column address strobe signal CAS while the reset signal RST is activated and the idle signal IDLE is deactivated. Even if the address strobe signal CAS is deactivated, the clock control signal CLKCTRL remains active. After that, when the idle signal IDLE is activated, the clock control signal CLKCTRL is deactivated. The internal clock generator 101 transfers the external clock CLK to the internal clock ICLK while the clock control signal CLKCTRL is activated, and activates the internal clock ICLK to the delay output unit 103. It is input and used.

3 is a timing diagram of signals used in the internal write signal delay circuit of FIG. 1.

Referring to the operation of the internal write signal delay circuit through FIG. 3, the reset signal RST is activated in the internal clock generator 101 to initialize the circuit, and the idle signal IDLE is inactivated. Thereafter, when the column address strobe signal CAS is activated, the clock control signal CLKCTRL is activated to generate an internal clock ICLK. The delay output unit 103 delays and outputs the internal write signal WTDQ in synchronization with the internal clock ICLK. When the idle signal IDLE is activated again, the clock control signal CLKCTRL is deactivated to stop the generation of the internal clock ICLK.

Here, the clock control signal CLKCTRL generates the internal clock ICLK when the column address strobe signal CAS is activated regardless of the write signal CASWT and the read signal CASRD. However, in the internal write signal delay circuit of FIG. 1, the internal clock ICLK does not need to be generated in a section in which the read signal CASRD is activated instead of the write signal CASWT. In addition, even when the operation of the delay output unit 103 is terminated before the idle signal IDLE is applied, the internal clock ICLK is continuously generated until the activation time of the idle signal IDLE. As a result, an unnecessary power consumption occurs in the memory device due to the toggle of the unnecessary internal clock ICLK.

The present invention has been proposed to solve the above problems, and an object thereof is to provide an internal write signal delay circuit and a delay method for reducing unnecessary power consumption of a semiconductor memory device.

An internal write signal delay circuit according to the present invention for achieving the above object includes a latency controller for generating a latency signal by delaying a write signal activated by a column address strobe signal by a write latency, and the latency from the time at which the write signal is activated. An internal clock generator for activating the internal clock until the signal activation time and a delay output unit for delaying and outputting the internal light signal activated by the write signal in synchronization with the internal clock.

The internal clock generator may transmit the external clock received to the internal clock when the write signal is activated, and fix the internal clock to a predetermined level when the latency signal is activated.

The internal write signal delay method according to the present invention includes generating a latency signal by delaying a write signal activated by a column address strobe signal by a write latency, and an internal clock from an activation point of the write signal to an activation point of the latency signal. Activating and delaying the internal write signal activated by the write signal in synchronization with the internal clock.

According to the present invention, by activating the internal clock only for a time as long as the write latency from the time when the write signal is activated by the column address strobe signal, it is possible to prevent unnecessary toggling of the internal clock and reduce unnecessary power consumption of the memory device. It works.

1 is a block diagram of a conventional internal write signal delay circuit.
2 is a block diagram of the internal clock generating unit 101 of FIG.
3 is a timing diagram of signals used in the internal write signal delay circuit of FIG.
Figure 4 is a block diagram of an embodiment of an internal write signal delay circuit according to the present invention.
5 is a block diagram of the internal clock generator 403 of FIG.
6 is a configuration diagram of the latency controller 401 of FIG. 4.
7 is a configuration diagram of the delay output unit 405 of FIG. 4.
8 is a timing diagram of signals used in the internal write signal delay circuit of FIG.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

4 is a configuration diagram of an internal write signal delay circuit according to the present invention.

Referring to FIG. 4, an internal write signal delay circuit according to an exemplary embodiment of the present invention may include a latency controller configured to delay a write signal CASWT activated by a column address strobe signal CAS by a write latency to generate a latency signal CASWT_WL. 401, the write signal CASWT in synchronization with the internal clock generator 403 and the internal clock ICLK that activate the internal clock ICLK from the activation time of the write signal CASWT to the activation time of the latency signal CASWT_WL. And a delay output unit 405 for delaying and outputting the internal write signal WTDQ activated by.

The write signal CASWT is a signal that receives data from the outside of the memory and stores the data in the core area. When the column address strobe signal CAS and the write enable signal WE are simultaneously activated as high, Is activated. In addition, when the write signal CASWT is activated, the internal write signal WTDQ for receiving real data in the DQ region is activated as 'high'.

The internal clock generator 403 activates the internal clock ICLK from the time when the write signal CASWT is 'high', not the column address strobe signal CAS. In the related art, the internal clock ICLK is activated by the column address strobe signal CAS, which consumes unnecessary power. Therefore, when the write signal CASWT is activated, the internal clock ICLK may be deactivated. The internal clock generator 403 is controlled to start the toggling.

The latency signal CASWT_WL is a signal obtained by delaying the write signal CASWT by the write latency. Since the actual data is input to the DQ region of the semiconductor memory after the write latency after the write signal CASWT is activated as 'high', the internal write signal WTDQ notifies the start of the internal write operation to the DQ region. ) Must be delivered. Therefore, the delay output unit 405 delaying the internal write signal WTDQ may operate only during the write latency period from the time when the write signal CASWT is activated. That is, the internal clock ICLK is activated only for the time as long as the write latency, so that the internal clock ICLK is transmitted to the delay output unit 405. To this end, an internal clock is generated by generating a latency signal CASWT_WL, which delays the write signal CASWT by the write latency, and fixes the internal clock ICLK at a constant level from the time when the latency signal CASWT_WL is activated as 'high'. The current consumed for toggling (ICLK) can be minimized.

5 is a block diagram of the internal clock generator 403 of FIG. 4.

Referring to FIG. 5, the internal clock generator 403 responds to the clock control signal generator 501 and the clock control signal CLKCTRL, which generate the clock control signal CLKCTRL for activating the internal clock ICLK. The clock output unit 503 activates the internal clock ICLK.

The clock control signal generator 501 activates the clock control signal CLKCTRL to 'high' from the time when the write signal CASWT is activated to 'high', and when the latency signal CASWT_WL is activated to 'high'. SR latch for controlling to deactivate the clock control signal CLKCTRL to 'low'. As a result, even after the clock control signal CLKCTRL is activated even before the idle signal IDLE is activated, toggling of the internal clock ICLK is stopped by the latency signal CASWT_WL. When the idle signal IDLE is activated, it is no longer necessary to supply the internal clock ICLK, so the toggling of the internal clock ICLK is similarly stopped.

The clock output unit 503 transfers the external clock CLK input during the activation period of the clock control signal CLKCTRL to the internal clock ICLK.

FIG. 6 is a configuration diagram of the latency controller 401 of FIG. 4.

Referring to FIG. 6, the latency controller 401 displays one of N D flip-flops connected in series and a signal output from each of the N D flip-flops in response to the light latency in order to delay the write signal CASWT. And a selection unit 601 for selecting with the signal CASWT_WL.

Each of the N D flip-flops delays the input signal by one clock, and the output signals are all input to the selector 601. The selector 601 may select an output signal corresponding to the write latency among the N output signals as the latency signal CASWT_WL. For example, when WL = 4 clocks, selecting the signal output from the fourth D flip-flop allows the write signal CASWT to be delayed by 4 clocks to obtain the latency signal CASWT_WL.

7 is a configuration diagram of the delay output unit 405 of FIG. 4.

As shown in FIG. 7, the delay output unit 405 may include two D flip-flops 701 and 703 that operate in synchronization with the internal clock ICLK. When the write signal CASWT is activated as 'high' in the memory device, the internal write signal WTDQ for receiving data from the DQ region is activated as 'high', and the delay output unit 405 is configured to output such an internal write signal ( In order to deliver WTDQ) to DQ area, it delays output for a certain time.

To this end, the delay output unit 405 delays the internal write signal WTDQ so that the clock is 1.5 clock ahead of the start point of the actual write operation (data input time point) and outputs the delayed internal write signal WTDQ_15. The reason for the 1.5 clock ahead of the actual write start time is to provide a time allowance to prepare to receive the data input from the DQ region. Here, an inverter driver (not shown) may be further included for inverting and outputting the delayed internal write signal WTDQ_15.

8 is a timing diagram of signals used in the internal write signal delay circuit of FIG. 4.

The effect of the present invention can be confirmed by comparing the timing diagram of FIG. 8 with FIG. 3.

Unlike the delay circuit of FIG. 3, the clock control signal CLKCTRL is activated 'high' not by the column address strobe signal CAS but by the write signal CASWT. Thereafter, when the write latency signal CASWT_WL is activated, the clock control signal CLKCTRL is deactivated to 'low'. The internal clock ICLK is activated only for a period of time corresponding to the write latency from the activation period of the clock control signal CLKCTRL, that is, the activation time of the write signal CASWT. In this embodiment, WL = 4 clocks.

In addition, after the activation time of the latency signal CASWT_WL, the internal clock ICLK does not toggle even before the idle signal IDLE is activated.

As such, by preventing current consumption due to toggling of the unnecessary internal clock ICLK, power consumption of the memory device may be reduced.

As described above, in the present invention, the internal clock is activated only for a time as long as the write latency from the time when the write signal is activated by the column address strobe signal, thereby preventing unnecessary toggling of the internal clock and unnecessary power consumption of the memory device. An internal write signal delay circuit and a delay method that can be reduced are proposed.

The present invention described above is capable of various substitutions, modifications, and changes without departing from the technical spirit of the present invention for those skilled in the art to which the present invention pertains. It is not limited by the drawings.

Claims (8)

A latency controller generating a latency signal by delaying a write signal activated by the column address strobe signal by a write latency;
An internal clock generator configured to activate an internal clock from an activation time of the write signal to an activation time of the latency signal; And
A delay output unit configured to delay and output an internal light signal activated by the write signal in synchronization with the internal clock;
An internal write signal delay circuit comprising a.
The method of claim 1,
The internal clock generator
When the write signal is activated, the received external clock is transmitted to the internal clock, and when the latency signal is activated, the internal clock is fixed to a predetermined level.
Internal write signal delay circuit.
The method of claim 1,
The internal clock generator
A clock control signal generator configured to generate a clock control signal for activating the internal clock; And
And a clock output unit activating the internal clock in response to the clock control signal.
Internal write signal delay circuit.
The method of claim 3,
The clock control signal generator
And an SR latch for activating the clock control signal when the write signal is activated and deactivating the clock control signal when the latency signal or idle signal is activated.
The method of claim 1,
The latency controller
A plurality of D flip-flops connected in series for delaying the write signal; And
And a selector configured to select one of the outputs of the plurality of D flip-flops as the latency signal in response to the light latency.
Internal write signal delay circuit.
The method of claim 1,
The delay output unit
One or more D flip-flops connected in series for delaying the internal write signal.
Internal write signal delay circuit.
Generating a latency signal by delaying the write signal activated by the column address strobe signal by the write latency;
Activating an internal clock from an activation time of the write signal to an activation time of the latency signal; And
Delaying and outputting an internal write signal activated by the write signal in synchronization with the internal clock;
Internal light signal delay method comprising a.
The method of claim 7, wherein
Activating the internal clock
When the write signal is activated, the received external clock is transmitted to the internal clock, and when the latency signal is activated, the internal clock is fixed to a predetermined level.
Internal light signal delay method.

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