KR20120004223A - Semiconductor device manufacturing method - Google Patents

Abstract

The present invention is to provide a method for manufacturing a semiconductor device that can prevent the bridge between the storage node contact and the bit line according to the step and reduce the resistance of the semiconductor device, the step of forming an isolation layer on the substrate to define the active region ; Forming a buried bit line of a line type having a protrusion overlapping the active region while being embedded in the device isolation film of the substrate; Forming a first insulating film pattern on the entire structure including the buried bit line; Forming a contact type recess pattern in active regions on both sides of the protrusion of the buried bit line; And forming a line-type gate pattern protruding over the substrate while filling the recess pattern, thereby securing a process margin when forming a storage node contact, and reducing self-aligned contact fail between the storage node contact and the gate pattern. And reducing the storage node contact resistance, increasing process margins, and increasing mass productivity.

Description

Semiconductor device manufacturing method {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing techniques, and more particularly to a method of manufacturing a semiconductor device comprising a semi-barrier bit line.

In a typical DRAM process, an isolation layer is formed on a substrate to define an active region, and then a gate pattern, a landing plug contact, a bit line contact, a bit line, a storage node contact, and a storage node are sequentially processed on the substrate. have.

However, the conventional technology causes various problems such as a bridge between the storage node contact and the bit line while the step is generated by the bit line when forming the storage node contact.

In addition, a landing plug contact is formed on the gate pattern after the gate pattern is formed for the connection of the bit line and the storage node, and the resistance of the bit line contact and the storage node contact increases, and the integration of the semiconductor device proceeds to the landing plug contact process. There is a problem in that a self-aligned contact fail occurs.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and provides a method of manufacturing a semiconductor device capable of preventing bridges between storage node contacts and bit lines due to a step and reducing resistance of the semiconductor device. There is this.

A semiconductor device manufacturing method according to an embodiment of the present invention for achieving the above object comprises the steps of defining an active region by forming an isolation layer on the substrate; Forming a buried bit line of a line type having a protrusion overlapping the active region while being embedded in the device isolation film of the substrate; Forming a first insulating film pattern on the entire structure including the buried bit line; Forming a contact type recess pattern in active regions on both sides of the protrusion of the buried bit line; And forming a line-type gate pattern protruding from the substrate while filling the recess pattern.

In particular, the recess pattern may include a pin pattern or a saddle pin pattern.

In addition, the gate pattern may be formed to be biased toward a central portion of the active region.

The forming of the buried bit line may include forming a photoresist pattern on the substrate including the device isolation layer to simultaneously open a portion of the active region and a bit line region; Forming a trench by etching the substrate using the photoresist pattern as an etch barrier; Forming a spacer on sidewalls of the trench; And embedding a conductive material in the trench to form a bit line.

The method may further include forming an insulating layer filling the gate pattern after the gate pattern; Etching the insulating layer to form a contact hole exposing the substrate between the gate patterns; And forming a storage node contact by filling a conductive material in the contact hole. The forming of the contact hole may include etching the insulating layer using self-aligned contact etching.

The semiconductor device manufacturing method of the present invention described above has the effect of securing the process margin when forming the storage node contact by forming the buried bit line in advance and forming the gate pattern in the center portion of the active region.

Therefore, there is an effect of reducing the self-aligned contact fail and storage node contact resistance between the storage node contact and the gate pattern.

In addition, the buried bit line is applied to omit the landing plug contact and directly connect the storage node contact to the substrate, thereby reducing the resistance of the storage node contact.

In addition, process margins are secured and mass productivity is increased by eliminating the landing plug contact and the bit line contact.

1 to 8 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the technical idea of the present invention.

1 to 8 are process plan views and cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention. (a) is a top view, and (b) or (c) is sectional drawing cut | disconnected according to each direction. For the convenience of description, a plan view and a cross-sectional view will be described with reference to the case.

As shown in FIG. 1, an isolation layer 11A is formed on a substrate 10 through a shallow trench isolation (STI) process. In this case, the device isolation layer 11A may include an oxide film such as a high density plasma oxide (HDP oxide) and a spin on dielectric (SOD). The active area 11B is defined by the device isolation film 11A.

Subsequently, a first mask pattern 12 for opening a bit line is formed on the substrate 10 including the device isolation layer 11A. The first mask pattern 12 is formed by coating a photoresist on the substrate 10 and patterning the exposure and development to open the bit line region. In addition, when the second mask pattern 12 is formed of a photoresist layer, a hard mask such as an amorphous carbon layer may be further formed below the photoresist layer to secure an etching margin.

The bit line region opened by the first mask pattern 12 may be formed to have a protruding region overlapping the active region 11B. That is, the bit line region opened by the first mask pattern 12 is formed in a line type as a whole and overlaps with the center portion of the active region 11B. This is to connect the bit line and the substrate 10 while the bit line contact is omitted.

As illustrated in FIG. 2, the bit line trench 13 is formed by etching the substrate 10 using the first mask pattern 12 (see FIG. 1) as an etch barrier. The bit line trench 13 may be etched in an area opened by the first mask pattern 12, that is, a line type bit line area and a protruding area overlapping the active area 11B.

The bit line trench 13 is formed by etching both the device isolation film 11A and the active region 11B, wherein the device isolation film 11A formed of the oxide film using the selectivity ratio of silicon and the oxide film is the active region 11B. It is desirable to allow more etching. This is to lower the shift resistance by increasing the thickness of the bit line.

Next, the first mask pattern 12 (see FIG. 1) is removed. When the first mask pattern 12 (see FIG. 1) is a photosensitive film, the first mask pattern 12 (see FIG. 1) is removed by dry etching, and the dry etching includes an oxygen strip process.

As shown in FIG. 3, spacers 14 are formed on sidewalls of the bit line trench 13. The spacer 14 is formed by forming an insulating material for the spacer along the step of the entire structure including the bit line trench 13, and then etching the spacer insulating material to remain only on the sidewall of the bit line trench 13. do. In this case, the insulating material is preferably formed of a nitride film.

Subsequently, a conductive material is embedded in the bit line trench 13 to form the bit line 15. The conductive material may be formed in a stacked structure of a barrier metal film and a metal material, wherein the metal material is formed of tungsten, for example. In detail, a barrier metal film is formed in the bit line trench 13, and a metal material is buried in a thickness sufficient to sufficiently fill the bit line trench 13 on the barrier metal film, and then the surface of the substrate 10 is exposed. The buried bit line 15 is formed by etching the metal material and the barrier metal film with the target.

Thus, a line type buried bit line 14 having a protrusion overlapping the middle portion of the active region 11B is formed. In other words, the protrusion overlapping the active region 11B serves as a contact to form the contact-integrated buried bit line 14.

As described above, by forming a buried bit line 14 connected to the active region 11B and buried in the substrate 10, an advantage of securing a process margin by eliminating a bit line contact process for subsequent connection with the active region is provided. have.

As shown in FIG. 4, the first insulating layer 16 is formed on the substrate 10 including the buried bit line 15. The first insulating layer 16 is for insulating between the buried bit line 15 and the upper layer, and is preferably formed of an insulating material. For example, the insulating material includes a nitride film.

Subsequently, a second mask pattern 17 is formed on the first insulating layer 16. The second mask pattern 17 may be formed by coating a photoresist on the first insulating layer 16 and patterning the gate region to be opened by exposure and development. In this case, the gate area opened by the second mask pattern 17 is defined as a contact type.

As shown in FIG. 5, the recess pattern 18 is formed by etching the first insulating layer 16 (see FIG. 4) and the substrate 10 using the second mask pattern 17 (see FIG. 4) as an etch barrier. . The etched first insulating layer 16 (refer to FIG. 4) is hereinafter referred to as 'first insulating layer pattern 16A'.

In the recess pattern 18 etched by the second mask pattern 17 (see FIG. 4), the active region 11B and the device isolation layer 11A outside the active region 11B are etched together, and the device isolation layer 11A is formed. More than this active region 11B is etched to form a fin type (hereinafter referred to as a fin type), hereinafter referred to as a fin type recess pattern "pin pattern 18".

Next, the second mask pattern 17 (see FIG. 4) is removed. When the second mask pattern 17 (see FIG. 4) is a photoresist film, the second mask pattern 17 (see FIG. 4) is removed by dry etching, and the dry etching includes an oxygen strip process.

Referring to the plan view of (a), contact pin patterns 18 are formed on both sides of the protrusions of the buried bit line 15.

In addition, referring to the cross-sectional view of (b) viewed from the top view of (a) B-B ', it can be seen that the buried bit line 15 is formed on both sides around the pin pattern (18).

As illustrated in FIG. 6, the gate insulating layer 19 is formed on the sidewalls and the bottom of the fin pattern 18. The gate insulating film 19 is preferably formed of an oxide film, for which an oxidation process may be performed.

Subsequently, the polysilicon layer 20 is formed on the substrate 10 and the first insulating film pattern 16A with a thickness sufficiently filling the fin pattern 18. After the polysilicon layer 20 is formed, a planarization process is performed for a subsequent process. The planarization process may be performed by a chemical mechanical polishing process.

Subsequently, a metal layer 21 is formed on the planarized polysilicon layer 20, and a hard mask nitride film 22 is formed on the metal layer 21. The metal layer 21 may be formed in a stacked structure, wherein the metal layer 21 has a stacked structure of a barrier metal film and a metal material layer for electrodes. In addition, the electrode metal material layer includes tungsten.

As shown in FIG. 7, the gate pattern G is formed by etching the hard mask nitride film 22, the metal layer 21, and the polysilicon layer 20. In detail, after forming a photoresist pattern defining a gate pattern region on the hard mask nitride film 22 and patterning the hard mask nitride film 22, the hard mask nitride film 22 is formed as an etch barrier as a metal layer ( 21) and the polysilicon layer 20 are etched. In particular, the polysilicon layer 20 may be sufficiently etched so as not to remain on the first insulating layer pattern 16A and to remain only in the fin pattern 18.

Hereinafter, the etched polysilicon layer 20 is a 'polysilicon electrode 20', the etched metal layer 21 is a 'metal electrode 21', and the etched hard mask nitride layer 22 is a 'gate hard mask ( 22).

In particular, since the gate pattern G is formed in a line type and the bit line contact is omitted by the buried bit line 15, the gate pattern G is directed toward the protrusion of the buried bit line 15, that is, the center portion of the active region. Etch to shift. In this case, the biased distance of the gate pattern G may be sufficiently insulated between neighboring gate patterns G, and it is preferable to proceed to an optimal distance at which the line width CD of a subsequent storage node contact is widened.

Therefore, as shown in the plan view of (a), it can be seen that the gate pattern G, which is partially overlapped with the contact type fin pattern 18 and is biased toward the center portion of the active region 11B, is formed. In the cross-sectional view of (b) in which the plan view of FIG.

In addition, referring to the cross-sectional view of (c) in which the plan view of (a) is viewed from the direction C-C ', both the buried bit line 15 and the buried bit line 15 formed in the center portion of the active region 11B are centered. The gate pattern G may be etched by filling the contact type fin pattern 18 and the fin pattern 18 formed next to the center portion of the active region 11B, that is, the upper portion of the buried bit line 15.

As described above, the gate pattern G is formed in the center of the active region 11B to secure an etch region for forming subsequent storage node contacts.

Subsequently, the capping film 23 is formed along the step of the entire structure including the gate pattern G. The capping layer 23 is to prevent the polysilicon electrode 20 exposed by the insulating and biased etching between the gate patterns G from coming into contact with the outside. The capping layer 23 is preferably formed of an insulating material, for example, a nitride layer. do.

As shown in FIG. 8, the second insulating layer 24 is formed on the capping layer 23 to a thickness sufficiently filling the gate patterns G. Referring to FIG. The second insulating layer 24 is for insulating between the gate pattern G and the upper layer, and is preferably formed of an insulating material, for example, an oxide layer.

Subsequently, after forming the contact hole exposing the substrate 10 by etching the second insulating layer 24, the conductive material is filled to form a storage node contact 25. The conductive material includes polysilicon. The contact hole may be etched using a self aligned etching process, that is, an etching selectivity between the nitride film and the oxide film.

As shown in FIG. 3, the buried bit line is formed in advance, and the gate pattern G is patterned so as to be inclined to the center portion of the active region. Can be secured sufficiently.

In addition, as the gate pattern G is biased, the etching area is widened, and thus, the self-aligned contact failing between the storage node contact 25 and the gate pattern G is reduced, and the storage node contact 25 is widened, so that the etching pattern is increased. The contact area can be increased, thus reducing the resistance of the storage node contacts 25.

Moreover, there is no need to form additional storage node contacts as the area of contact between storage node contacts 25 and storage nodes increases, landing plug contacts are omitted and a direct connection between substrate 10 and storage node contacts 25 is eliminated. Possible resistance of the storage node contacts 25 is reduced.

In addition, eliminating the landing plug contact, the bit line contact, etc., has the advantage of increasing the process margin and mass productivity, and has the advantage of improving the product characteristics and product yield by reducing the resistance of the semiconductor device.

Although the technical spirit of the present invention has been described in detail according to the above embodiments, it should be noted that the above embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

10: substrate 11A: device isolation film
11B: active area 12: first mask pattern
13: trench 14: spacer
15: buried bit line 16: first insulating film
17: second mask pattern 18: pin pattern
19 gate insulating film 20 polysilicon electrode
21: metal electrode 22: gate hard mask
23 capping film 24 second insulating film
25: Storage Node Contact

Claims (6)

Forming an isolation region on the substrate to define an active region;
Forming a buried bit line of a line type having a protrusion overlapping the active region while being embedded in the device isolation film of the substrate;
Forming a first insulating film pattern on the entire structure including the buried bit line;
Forming a contact type recess pattern in active regions on both sides of the protrusion of the buried bit line; And
Forming a gate pattern of a line type protruding from the substrate while filling the recess pattern;
A semiconductor device manufacturing method comprising a.
The method of claim 1,
The recess pattern includes a fin pattern or a saddle fin pattern.
The method of claim 1,
And the gate pattern is formed to be biased toward a center portion of the active region.
The method of claim 1,
Forming the buried bit line,
Forming a photoresist pattern on the substrate including the device isolation layer to simultaneously open a portion of the active region and a bit line region;
Forming a trench by etching the substrate using the photoresist pattern as an etch barrier;
Forming a spacer on sidewalls of the trench; And
Embedding a conductive material in the trench to form a bit line.
The method of claim 1,
After forming the gate pattern,
Forming an insulating film filling the gate pattern;
Etching the insulating layer to form a contact hole exposing the substrate between the gate patterns; And
Filling a conductive material in the contact hole to form a storage node contact
A semiconductor device manufacturing method further comprising.
The method of claim 5,
Forming the contact hole,
And fabricating the insulating film by using self-aligned contact etching.

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