KR20110001102A - Program Operation Method of Nonvolatile Memory Device - Google Patents

Abstract

According to the present invention, in a program operation of a nonvolatile memory device in which a plurality of memory cells, a source select transistor, a drain select transistor, and a dummy cell adjacent to the source and drain select transistors are connected, a program operation is performed on an n-1 memory cell. Performing a program operation on the n-th memory cell adjacent to the dummy cell after performing a program operation on the n-th memory cell, performing a program operation on the n-th memory cell, and then performing a program operation on the dummy cell A method of operating a nonvolatile memory device includes performing an operation to increase a threshold voltage of an nth memory cell to a target threshold voltage.

Description

Program operation method of non-volatile memory device

The present invention relates to a program operation method of a nonvolatile memory device, and more particularly, to a program operation method of a nonvolatile memory device using a dummy cell in order to improve the reliability of the program operation.

The nonvolatile memory device includes a memory cell array in which data is stored. The memory cell array includes a plurality of strings, each string including a plurality of memory cells. Memory cells included in different strings are each connected to a wordline.

Recently, a program operation is performed in a multilevel cell (MLC) method using a plurality of bits for miniaturization and large capacity of a nonvolatile memory device.

1 is a diagram illustrating a conventional method of programming a nonvolatile memory device, and FIG. 2 is a graph illustrating a problem of the conventional program method.

1 and 2, in a program operation of a nonvolatile memory device, an interference caused by program operation of neighboring memory cells increases as the degree of integration of the device increases. For example, an operation of first programming memory cells connected to an even bit line (BLe) and then programming memory cells connected to an odd bit line (BLo) will be described. The numbers shown at the locations of the respective memory cells in FIG. 1 indicate a program operation sequence. That is, the program operation 1 is performed on the memory cells connected to the even bit line BLe and the zeroth word line WL0. Subsequently, the program operation 2 is performed on the memory cells connected to the odd bit line BLo and the zeroth word line WL0. Next, the program operation 3 is performed on the memory cell connected to the even bit line BLe and the first word line WL1.

When the program operation is sequentially performed as described above, in the case of a memory cell programmed first, neighboring memory cells are interrupted while being programmed. Accordingly, the program operation is performed by setting a voltage lower than the target threshold voltage by an amount of change in voltage due to interference. For example, in the case of the memory cell in which the program operation 1 is performed first, since interference is received from the X, Y, and Z directions, the threshold voltage is reduced in consideration of these to perform the program operation. Accordingly, the threshold voltage of the first programmed memory cell 1 becomes the target threshold voltage when the program operation of the memory cell in which the program operation 4 is performed is completed or becomes adjacent to the target threshold voltage.

However, this is only from the 0th word line (WO) to the n-th word line (WLn-1). Memory cells connected to the nth word line WLn, which is the last word line, are less interferenceed than memory cells connected to the other word lines WL0 to WLn-1. Accordingly, the threshold voltages (B of FIG. 2) of the memory cells connected to the last word line WLn are lower than the threshold voltages (A of FIG. 2) of the memory cells connected with the remaining word lines WL0 to WLn-1. It will have a distribution.

SUMMARY OF THE INVENTION An object of the present invention is to form a dummy word line between a drain select line and a word line adjacent thereto and to perform a dummy program operation on memory cells connected to the dummy word line to cause interference in neighboring memory cells. The threshold voltages of the cells are adjacent to the target threshold voltages.

A method of operating a nonvolatile memory device according to an exemplary embodiment of the present invention may include a program of a nonvolatile memory device in which a plurality of memory cells, a source select transistor, a drain select transistor, and a dummy cell adjacent to the source and drain select transistors are connected. In operation, a program operation is performed on the n−1 th memory cell. After the program operation of the n-th memory cell is performed, the program operation is performed on the n-th memory cell adjacent to the dummy cell. After performing the program operation of the n-th memory cell, performing a program operation to the dummy cell to increase the threshold voltage of the n-th memory cell to the target threshold voltage.

In the performing of the program operation on the n-th memory cell, the threshold voltage of the n--1 memory cell is equal to the target threshold by an amount of change in the threshold voltage due to interference generated in the program operation on the n-th memory cell. Perform lower than the voltage.

The performing of the program operation on the n-th memory cell may include performing the program operation such that the threshold voltage of the n-th memory cell is lower than the target threshold voltage by an amount of change in the threshold voltage due to interference generated in performing the program operation on the dummy cell. do.

A method of operating a nonvolatile memory device according to a second embodiment of the present invention may include a program of a nonvolatile memory device in which a plurality of memory cells, a source select transistor, a drain select transistor, and a dummy cell adjacent to the source and drain select transistors are connected. In operation, a program operation is performed on the n−1 th memory cell. After the program operation of the n-th memory cell is performed, the program operation is performed on the dummy cell. After performing the program operation of the dummy cell, and performing a program operation on the n-th memory cell adjacent to the dummy cell to increase the threshold voltage of the n-th memory cell to the target threshold voltage. .

The program operation performed on the dummy cell is performed in the same manner as the program operation performed on the n-th or n-th memory cell.

The threshold voltage of the nth memory cell in the erased state is increased by performing a program operation on the dummy cell.

A method of operating a nonvolatile memory device according to a third embodiment of the present invention may include a plurality of word lines, a source select line, a drain select line, and a dummy word line adjacent to the source and drain select lines. In the program operation of, the memory cells connected from the 0th word line to the n-2nd word line among the word lines are sequentially programmed. The first program operation is performed on the first memory cell connected to the n-1 word line and the first bit line, and the second program operation is performed on the second memory cell adjacent to the first memory cell and connected to the second bit line. do. After the second program operation is performed, a third program operation is performed on the third memory cell connected to the n-th word line and the first bit line adjacent to the dummy word line, and is adjacent to the third memory cell and is connected to the second bit line. A fourth program operation is performed on the connected fourth memory cell. After the fourth program operation, a fifth program operation is performed on the first dummy cell connected to the dummy word line and the first bit line, and the second dummy cell is adjacent to the first dummy cell and connected to the second bit line. A method of operating a nonvolatile memory device comprising performing a sixth program operation.

The first program operation is performed such that the threshold voltage of the first memory cell is lower than the target threshold voltage by an amount of change in the threshold voltage due to interference generated during the second to fourth program operations.

By using interference generated when the fifth and sixth program operations are performed, the threshold voltages of the third and fourth memory cells are increased to be the target threshold voltages.

A method of operating a nonvolatile memory device according to a fourth embodiment of the present invention is a nonvolatile memory device in which a plurality of word lines, a source select line, a drain select line, and a dummy word line adjacent to the source and drain select lines are connected. In the program operation of, the memory cells connected from the 0th word line to the n-2nd word line among the word lines are sequentially programmed. The first program operation is performed on the first memory cell connected to the n-1 word line and the first bit line, and the second program operation is performed on the second memory cell adjacent to the first memory cell and connected to the second bit line. do. After performing a second program operation, a second program operation is performed on a first dummy cell connected to the dummy word line and the first bit line, and a second dummy adjacent to a first dummy cell and connected to a second bit line. Perform a fourth program operation on the cell. After performing the fourth program operation, a fifth program operation is performed on the third memory cell connected to the n-th word line and the first bit line adjacent to the dummy word line, and is adjacent to the third memory cell and is connected to the second bit line. A method of operating a nonvolatile memory device comprising performing a sixth program operation on a connected fourth memory cell.

The third and fourth program operations are performed on the first and second dummy cells to increase the threshold voltages of the third and fourth memory cells in the erased state.

In the third and fourth program operations, the threshold voltages of the third and fourth memory cells are increased by an amount of change in the threshold voltage due to interference occurring during the third and fourth program operations.

According to an embodiment of the present invention, a dummy word line is formed between a drain select line and a word line adjacent thereto, and a dummy program operation is performed on memory cells connected to the dummy word line to generate interference to neighboring memory cells, thereby excluding the dummy word line. The threshold voltages of the memory cells connected to the remaining word lines are adjacent to the target threshold voltage of the program operation. As a result, the reliability of the nonvolatile memory device can be improved.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided for complete information.

3 is a circuit diagram illustrating a nonvolatile memory device according to the present invention.

The nonvolatile memory device includes a memory cell array in which data is stored, and the memory cell array includes a plurality of strings separated by bit lines. Each string includes a drain select transistor DST, memory cells 110, and a source select transistor SST connected in series with each other. A drain of the drain select transistor DST is electrically connected to a bit line BLe or BLo, and a source of the source select transistor SST is connected to a common source line. Electrically connected.

Drain select transistors DST of different strings are connected to form a drain select line DSL, memory cells 110 of different strings are connected to form word lines WL0 to WLn, and sources of different strings The select transistors SST are connected to form a source select line SSL.

In particular, during a program operation of the memory cells Fc and Fd connected to the n-th word line WLn, the drain select transistor DST and the n-th memory cells Fc and Fd may be increased to increase the threshold voltage to the target threshold voltage. Dummy cells Da and Db are formed in between. Specifically, the dummy bit Da is formed between the drain select transistor DST and the nth memory cell Fc in the even bit line BLe, and the drain select transistor DST is formed in the odd bit line BLo. The dummy cell Db is formed between the nth memory cell Fd. In addition, dummy cells Da and Db of different strings are connected to form a dummy word line Dummy WL.

The program operation of the nonvolatile memory device will be described below.

4 is a view for explaining a program method according to an embodiment of the present invention, Figure 5 is a graph for explaining a change in the threshold voltage according to an embodiment of the present invention.

Referring to FIG. 4, a program operation is performed on memory cells Fa and Fb connected to an n−1 th word line WLn−1 and memory cells Fc and Fd connected to an n th word line WLn. Perform the program operation. Subsequently, a program operation is performed on the dummy cells Da and Db connected to the dummy word line Dummy WL.

Specifically, a program operation is sequentially performed from memory cells connected to the zeroth word line WL0 to memory cells connected to the n−1 th word line WLn-1. Preferably, the selected word line first performs a program operation on the memory cells connected to the even bit line BLe, and then performs a program operation on the memory cells connected to the odd bit line BLO to perform a neighboring bit line. Minimize interference between lines. Alternatively, the program order of the even and odd bit lines BLe and BLo may be changed.

The program operation of the memory cells connected to the n-th word line WLn-1, the n-th word line WLn, and the dummy word line WLn will be described below.

4 and 5, program operations are sequentially performed on memory cells connected to the 0th to nth-2th word lines WL0 to WLn-2. Subsequently, a program operation is performed on the memory cell Fa connected to the n-th word line WLn-1 and the even bit line BLe.

For convenience of description, a memory cell connected to the n-th word line WLn-1 and the even bit line BLe is referred to as a first memory cell Fa, and an operation of programming the first memory cell Fa into the first memory cell Fa is described. 1 Program operation (①). A memory cell connected to the n-1 word line WLn-1 and the odd bit line BLo is called a second memory cell Fb, and an operation of programming the second memory cell Fb into a second memory cell Fb ②). A memory cell connected to the nth word line WLn and the even bit line BLe is called a third memory cell Fc, and an operation of programming the third memory cell Fc is called a third program operation ③. . A memory cell connected to the nth word line WLn and the odd bit line BLo is called a fourth memory cell Fd, and an operation of programming the fourth memory cell Fd is called a fourth program operation ④. . A dummy cell connected to the dummy word line Dummy WL and the even bit line BLe is called a first dummy cell Da, and an operation of programming the first dummy cell Da is called a fifth program operation ⑤. . A dummy cell connected to the dummy word line Dummy WL and the odd bit line BLo is called a second dummy cell Db, and an operation of programming the second dummy cell Db is called a sixth program operation ⑥. .

The program operation method is as follows.

After the first program operation ① is performed on the first memory cell Fa, the second program operation is performed on the second memory cell Fb (②). In particular, the first and second program operations ① and ② may be performed by the amount of change caused by the interference rather than the target threshold voltage in consideration of the interference to be received during the program operation of the third and fourth memory cells Fc and Fd. It is desirable to perform the program operation so as to have a low threshold voltage.

During the first and second program operations ① and ②, the third and fourth memory cells Fc and Fd interfere with each other and the threshold voltage in the erased state is slightly increased (1, 2 in FIG. 5). Subsequently, a third program operation ③ is performed on the third memory cell Fc (3 in FIG. 5). The third program operation ③ is performed to be at a level lower than the target threshold voltage Vf in consideration of the interference of the fourth to sixth program operations ④ to ⑥ to be subsequently performed. Preferably, the third program operation ③ is performed to be at a level lower than the target threshold voltage Vf by the amount of change in the threshold voltage caused by the interference of the fourth to sixth program operations ④ to ⑥. After performing the third program operation ③, the fourth program operation ④ is performed on the fourth memory cell Fd.

Subsequently, in order to reach the threshold voltages of the third and fourth memory cells Fc and Fd to the target threshold voltage Vf, fifth and sixth program operations may be performed on the first and second dummy cells Da and Db. ⑤ and ⑥) respectively. For example, the fifth and sixth program operations ⑤ and ⑥ may be performed by any one of the first to fourth program operations ① to ④. The threshold voltage of the third memory cell Fc may be increased to reach the target threshold voltage Vf due to the interference generated during the fifth and sixth program operations ⑤ and ⑥ (5 in FIG. 5,). ⑥).

According to the exemplary embodiment described above, after a program operation is performed on the memory cells Fc and Fd connected to the n th word line WLn of the last order, the dummy cells Da and Db connected to the dummy word line Dummy WL. ), The program operation is further performed to generate interference. Thus, the threshold voltages of the memory cells Fc and Fd connected to the n th word line WLn of the last order may be reached by the target threshold voltage Vf.

6 is a view for explaining a program method according to another embodiment of the present invention, Figure 7 is a graph for explaining a change in the threshold voltage according to another embodiment of the present invention.

6 and 7, for convenience of description, a memory cell connected to an n−1 th word line WLn−1 and an even bit line BLe is called a first memory cell Fa, and a first memory cell The operation to program Fa is called a first program operation ①. A memory cell connected to the n-1 word line WLn-1 and the odd bit line BLo is called a second memory cell Fb, and an operation of programming the second memory cell Fb into a second memory cell Fb ②). A dummy cell connected to the dummy word line Dummy WL and the even bit line BLe is called a first dummy cell Da, and an operation of programming the first dummy cell Da is called a third program operation ③. . A dummy cell connected to the dummy word line Dummy WL and the odd bit line BLo is called a second dummy cell Db, and an operation of programming the second dummy cell Db is called a fourth program operation ④. . A memory cell connected to the nth word line WLn and the even bit line BLe is called a third memory cell Fc, and an operation of programming the third memory cell Fc into a fifth program operation ⑤ is performed. This is called. A memory cell connected to the nth word line WLn and the odd bit line BLo is called a fourth memory cell Fd, and an operation of programming the fourth memory cell Fd is called a sixth program operation ⑥. .

The program operation method is as follows.

The program operation is sequentially performed on the memory cells connected to the zeroth to n-th word lines WL0 to WLn-2. Subsequently, after the first program operation ① is performed on the first memory cell Fa, the second program operation is performed on the second memory cell Fb (②). In particular, the first and second program operations ① and ② may be performed by the amount of change caused by the interference rather than the target threshold voltage in consideration of the interference to be received during the program operation of the third and fourth memory cells Fc and Fd. It is desirable to perform the program operation so as to have a low threshold voltage.

During the first and second program operations ① and ②, the third and fourth memory cells Fc and Fd are interrupted to increase the threshold voltage in the erased state (1, 2 in FIG. 7). Subsequently, after the third program operation ③ is performed on the first dummy cell Da, the fourth program operation ④ is performed on the second dummy cell Da. During the third and fourth program operations ③ and ④, since the third and fourth memory cells Fc and Fd are subjected to interference, the threshold voltage of the erased state is increased (3 and 4 in FIG. 7). . In this case, the third and fourth program operations ③ and ④ are performed in the same manner as the first or second program operations ① or ②, or the same as the fifth or sixth program operations ⑤ or ⑥ to be performed subsequently. Can be done.

As such, the threshold voltages of the third and fourth memory cells Fc and Fd connected to the n-th word line WLn and in an erased state are the n-th word line WLn-1 and the dummy word line Dummy WL. This is increased due to the program operation of the memory cells Fa, Fb, Da, and Db connected to each other (1 to 4 in FIG. 7). Since the program operation is performed while the threshold voltage level of the erase state is increased, the target threshold voltage Vf can be easily reached (5 in FIG. 7).

As described above, the program operation of the memory cell of the last order of the string can be easily performed by using the interference generated by the dummy cells and performing the program operation on the dummy cells. In particular, the threshold voltages of the memory cells connected in the same string and performing the same program operation can be made uniform. Accordingly, the reliability of the nonvolatile memory device can be improved.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a view for explaining a conventional method of programming a nonvolatile memory device.

2 is a graph illustrating a problem caused by a conventional program method.

3 is a circuit diagram illustrating a nonvolatile memory device according to the present invention.

4 is a diagram for describing a program method according to an exemplary embodiment.

5 is a graph illustrating a change in threshold voltage according to an embodiment of the present invention.

6 is a diagram for describing a program method according to another exemplary embodiment.

7 is a graph illustrating a change in threshold voltage according to another embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

WL0 ~ WLn: Word line BLe, BLo: Bit line

100: Dummy Page Dummy WL: Dummy Word Line

Da, Db: dummy cells Fa to Fd: memory cells

DST: Drain Select Transistor SST: Source Select Transistor

DSL: Drain Select Line SSL: Source Select Line

CSL: Common Source Line

Claims (12)

In a program operation of a nonvolatile memory device in which a plurality of memory cells, a source select transistor, a drain select transistor, and a dummy cell adjacent to the source and drain select transistors are connected, Performing a program operation on an n-1th memory cell; Performing a program operation on an n-th memory cell adjacent to the dummy cell after performing a program operation on the n-th memory cell; And And after performing a program operation on the nth memory cell, performing a program operation on the dummy cell to increase the threshold voltage of the nth memory cell to a target threshold voltage. The method of claim 1, The performing of the program operation on the n-th memory cell may include: A method of operating a nonvolatile memory device in which the threshold voltage of the n-th memory cell is lower than the target threshold voltage by an amount of change in the threshold voltage due to interference generated in the program operation on the n-th memory cell. . The method of claim 1, The performing of a program operation on the nth memory cell may include: And a threshold voltage of the nth memory cell to be lower than a target threshold voltage by an amount of change of the threshold voltage due to interference generated in the program operation on the dummy cell. In a program operation of a nonvolatile memory device in which a plurality of memory cells, a source select transistor, a drain select transistor, and a dummy cell adjacent to the source and drain select transistors are connected, Performing a program operation on an n-1th memory cell; Performing a program operation on the dummy cell after performing a program operation on the n−1 th memory cell; And After the program operation of the dummy cell is performed, performing a program operation on an nth memory cell adjacent to the dummy cell to increase a threshold voltage of the nth memory cell to a target threshold voltage. Way. The method according to claim 1 or 4, The program operation performed on the dummy cell is performed in the same manner as the program operation performed on the n-th or n-th memory cell. The method of claim 4, wherein And performing a program operation on the dummy cell to increase the threshold voltage of the nth memory cell in the erased state. In a program operation of a nonvolatile memory device in which a plurality of word lines, a source select line, a drain select line, and a dummy word line adjacent to the source and drain select lines are connected, Sequentially programming memory cells connected from a 0th word line to an n-2th word line among the word lines; A first program operation is performed on a first memory cell connected to an n-1 word line and a first bit line, and a second program operation is performed on a second memory cell adjacent to the first memory cell and connected to a second bit line. Performing; After performing the second program operation, a third program operation is performed on an n-th word line adjacent to the dummy word line and a third memory cell connected to the first bit line, and is adjacent to the third memory cell. Performing a fourth program operation on a fourth memory cell connected to the second bit line; And After performing the fourth program operation, a fifth program operation is performed on the first dummy cell connected to the dummy word line and the first bit line, and is adjacent to the first dummy cell and connected to the second bit line. A method of operating a nonvolatile memory device comprising performing a sixth program operation on a second dummy cell. The method of claim 7, wherein The first program operation, And a threshold voltage of the first memory cell lower than a target threshold voltage by an amount of change of a threshold voltage due to interference generated during the second to fourth program operations. The method of claim 7, wherein And increasing threshold voltages of the third and fourth memory cells to be the target threshold voltage by using interference generated when the fifth and sixth program operations are performed. In a program operation of a nonvolatile memory device in which a plurality of word lines, a source select line, a drain select line, and a dummy word line adjacent to the source and drain select lines are connected, Sequentially programming memory cells connected from a 0th word line to an n-2th word line among the word lines; A first program operation is performed on a first memory cell connected to an n-1 word line and a first bit line, and a second program operation is performed on a second memory cell adjacent to the first memory cell and connected to a second bit line. Performing; After performing the second program operation, a third program operation is performed on the first dummy cell connected to the dummy word line and the first bit line, and is adjacent to the first dummy cell and connected to the second bit line. Performing a fourth program operation on the second dummy cell; After performing the fourth program operation, a fifth program operation is performed on an n-th word line adjacent to the dummy word line and a third memory cell connected to the first bit line, and is adjacent to the third memory cell. And performing a sixth program operation on a fourth memory cell connected to the second bit line. The method of claim 10, And operating the third and fourth program operations on the first and second dummy cells to increase the threshold voltages of the third and fourth memory cells in an erased state. The method of claim 11, In the third and fourth program operation, The threshold voltages of the third and fourth memory cells are increased by an amount of change in the threshold voltage due to interference generated during the third and fourth program operations.

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