KR20100085341A - Method for fabricating solar cell using diffusion blocking layer - Google Patents

Abstract

In the present invention, a method of manufacturing a solar cell using the diffusion barrier layer is disclosed. The solar cell manufacturing method using the diffusion barrier layer according to the present invention, (a) forming a lower electrode 200 on the substrate 100; (b) forming a lower first amorphous semiconductor layer 310 on the lower electrode 200; (c) forming a second amorphous semiconductor layer 320 on the lower first amorphous semiconductor layer 310; (d) forming a third amorphous semiconductor layer 330 on the second amorphous semiconductor layer 320; (e) forming a fourth amorphous semiconductor layer 340 on the third amorphous semiconductor layer 330; (f) forming a fifth amorphous semiconductor layer 350 on the fourth amorphous semiconductor layer 340; (g) The first to fifth amorphous semiconductor layers 310, 320, 330, 340, and 350 are heat-treated to form the first, third, and fifth amorphous semiconductor layers 310, 330, and 350 for the first and second. And crystallization into the third polycrystalline semiconductor layers 311, 331, and 351, respectively, and a part or the entire area of the second and fourth amorphous semiconductor layers 320 and 340 is formed in the first and third polycrystalline semiconductor layers 311. 351) and crystallizing; And (h) forming an upper electrode 400 on the third polycrystalline semiconductor layer 351.

Description

Manufacturing method of solar cell using diffusion barrier layer {METHOD FOR FABRICATING SOLAR CELL USING DIFFUSION BLOCKING LAYER}

The present invention relates to a method of manufacturing a solar cell using a diffusion barrier layer, and more particularly to manufacturing a solar cell that can improve the photoelectric conversion efficiency by preventing the diffusion of impurities in the intrinsic (i-type) semiconductor layer during the crystallization process. It is about a method.

In general, a thin film type solar cell using amorphous silicon (a-Si) is manufactured with a pn junction structure because the diffusion length of a carrier is much lower than that of single crystal or polycrystalline silicon due to the characteristics of the amorphous silicon material itself. If so, the collection efficiency of electron-hole pairs generated by light is very low.

In order to overcome this problem, a pin structure is formed between p-type and n-type having high impurity doping concentration using an intrinsic semiconductor layer containing no impurity as a light absorbing layer, and heat-treated to form polycrystalline silicon (p -si) has been proposed to crystallize. In such a polycrystalline p-i-n structure, a depletion region is formed at the junction between the i-layer, which is the light absorbing layer, and the p-layer and the n-layer having high doping concentration, thereby generating an electric field therein.

Therefore, the electron-hole pair generated by the incident light (receiving) in the i-layer is a drift in which electrons (-) move to n-type semiconductors and holes (+) move to p-type semiconductors according to the internal electric field, not diffusion. ) Current can flow. However, in such a p-i-n structure, impurities of n-type and p-type semiconductors are unnecessarily diffused into adjacent light absorbing layers (i-type semiconductors) during crystallization, thereby lowering photoelectric conversion efficiency.

1 is a graph showing the doping concentration according to crystallization of a p-i-n type solar cell according to the prior art.

Referring to FIG. 1, as an example, an ideal doping concentration of a p-type semiconductor layer formed by doping boron and an n-type semiconductor layer formed by doping phosphorous is shown in graphs 10 and 20. Likewise, the doping concentration of the impurity should be zero in the i-type semiconductor layer. However, the actual doping concentrations of p-type and n-type crystallized into a polycrystalline silicon layer by performing a heat treatment process are diffused into the i-type semiconductor layer as shown in graphs 11 and 21 to form low-doped states (p-, n-). It can be seen that. Accordingly, the i-type semiconductor layer, which is a light absorbing layer, may reduce the internal electric field, which is an original function, to reduce the generation of drift currents, and thus may cause a decrease in photoelectric conversion efficiency.

The present invention is to solve the above problems of the prior art, and an object of the present invention is to prevent impurities from diffusing into the light absorbing layer (intrinsic semiconductor layer) during the crystallization process.

In addition, the present invention has another object to improve the photoelectric conversion efficiency of the solar cell.

The object of the present invention comprises the steps of (a) forming a lower electrode on the substrate; (b) forming a lower first amorphous semiconductor layer on the lower electrode; (c) forming a second amorphous semiconductor layer on the lower first amorphous semiconductor layer; (d) forming a third amorphous semiconductor layer on the second amorphous semiconductor layer; (e) forming a fourth amorphous semiconductor layer on the third amorphous semiconductor layer; (f) forming a fifth amorphous semiconductor layer on the fourth amorphous semiconductor layer; (g) heat treating the first to fifth amorphous semiconductor layers to crystallize the first, third, and fifth amorphous semiconductor layers into first, second, and third polycrystalline semiconductor layers, respectively; And crystallizing a part or entire region of a fourth amorphous semiconductor layer in the first and third polycrystalline semiconductor layers; And (h) forming an upper electrode on the third polycrystalline semiconductor layer.

First, the second and fourth amorphous semiconductor layers are formed in a solar cell, wherein each of the second and fourth amorphous semiconductor layers is formed in a different conductivity type from the adjacent first and fifth amorphous semiconductor layers.

The second and fourth amorphous semiconductor layers each have a lower doping degree of impurities than the first and fifth amorphous semiconductor layers adjacent to each other.

The first to fifth amorphous semiconductor layer is formed of p +, n-, i, p-, n + type, the first to third polycrystalline semiconductor layer is characterized in that the crystallization of p, i, n type It is a manufacturing method of a battery.

The first to fifth amorphous semiconductor layer is formed of n +, p-, i, n-, p + type, the first to third polycrystalline semiconductor layer is characterized in that the crystallization of n, i, p type It is a manufacturing method of a battery.

The first to fifth amorphous semiconductor layer is a method of manufacturing a solar cell, characterized in that formed of amorphous silicon.

Finally, the first to third polycrystalline semiconductor layer is a method of manufacturing a solar cell, characterized in that the crystallized from polycrystalline silicon.

According to the present invention, it is possible to prevent the diffusion of impurities in the light absorbing layer of the solar cell.

In addition, according to the present invention, it is possible to increase the drift current generated in the light absorbing layer of the solar cell.

Moreover, according to this invention, the photoelectric conversion efficiency of a solar cell can be improved.

DETAILED DESCRIPTION The following detailed description of the invention refers to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that the various embodiments of the present invention are different but need not be mutually exclusive. For example, certain features, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the invention in connection with an embodiment. It is also to be understood that the position or arrangement of the individual components within each disclosed embodiment may be varied without departing from the spirit and scope of the invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention, if properly described, is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled. In the drawings, like reference numerals refer to the same or similar functions throughout the several aspects, and length, area, thickness, and the like may be exaggerated for convenience.

DETAILED DESCRIPTION Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention.

[Preferred Embodiments of the Invention]

In the following detailed description according to an embodiment of the present invention, silicon most commonly used as a material for forming a semiconductor layer is described as an example, but the present invention is not limited thereto, and it is limited to known materials having semiconductor characteristics. Can be used without

In addition, in the following detailed description according to an embodiment of the present invention, i-type means intrinsic that is not doped with impurities, and impurity when doping boron (B: boron) as n-type dopant when p-type doping is used. Phosphorus (P) was used as the present invention, but the present invention is not limited thereto, and a known technique may be used without limitation.

In addition, in the following detailed description according to an embodiment of the present invention, the meaning of + and-indicates a relative difference in doping concentration, and means that + has a higher concentration of doping than-. For example, n + is higher doped than n-.

2A to 2D are cross-sectional views illustrating a manufacturing process of a solar cell using a diffusion barrier layer according to an embodiment of the present invention.

2A, in accordance with an embodiment of the present invention, a substrate 100 is provided. The material of the substrate 100 may be either a transparent material or an opaque material according to the direction in which the solar cell receives light. For example, the substrate 100 may include glass, plastic, silicon, metal, stainless steel (SUS), and the like.

It may be desirable for the surface of the substrate 100 to be texturized. Texturing is to prevent a phenomenon that optical loss is generated by reflection of light incident on the substrate surface of the solar cell, and the characteristics of the substrate are reduced, thereby roughening the surface of the substrate. That is, when the surface of the substrate is roughened by forming an uneven pattern on the surface of the substrate, the light reflected once may be reflected back and incident, thereby reducing the reflectance of the light and increasing the amount of light trapping. It is possible to improve the photoelectric conversion efficiency.

In addition, an anti-reflective layer (not shown) may be formed on the substrate 100. The anti-reflective layer is not directly absorbed into the silicon layer by the sunlight incident through the substrate 100 and is immediately reflected to the outside, thereby degrading the efficiency of the solar cell. It can serve to prevent the phenomenon.

The material of the anti-reflection layer may be silicon oxide (SiO _x ) or silicon nitride (SiN _x ), but is not limited thereto. The antireflection layer may be formed by a low pressure chemical vapor deposition (LPCVD), a plasma enhanced chemical vapor deposition (PECVD), or the like.

Subsequently, according to an embodiment of the present invention, a lower electrode 200 of a conductive material may be formed on the substrate 100. The material of the lower electrode 200 may be any one of molybdenum (Mo), tungsten (W), and molybdenum tungsten (MoW), or alloys thereof, in which electrical properties are not degraded even when a high temperature process is performed while the contact resistance is low. The present invention is not necessarily limited thereto, and may include copper, aluminum, titanium, and the like, which are conventional conductive materials.

The lower electrode 200 may be formed by physical vapor deposition (PVD), such as thermal evaporation, e-beam evaporation, or sputtering, and LPCVD, PECVD, and metal organic chemistry. Chemical Vapor Deposition (CVD), such as Metal Organic Chemical Vapor Deposition (MOCVD). In this case, if the substrate 100 is formed of a conductive material, the lower electrode 200 may be omitted and the substrate may be used as the lower electrode.

Like the surface of the substrate 100 described above, a surface of the lower electrode 200 may perform a texturing process of forming an uneven pattern to improve photoelectric conversion efficiency of the solar cell.

Meanwhile, a reflective layer (not shown) which is a transparent conductive layer may be further formed on the lower electrode 200. That is, the reflective layer may be located between the lower electrode 200 and the first polycrystalline silicon layer 310 to be formed later. The reflective layer is incident on the substrate 100 while being electrically connected to the lower electrode 200. The light can be reflected to improve the photoelectric conversion efficiency. The reflective layer is preferably AZO (ZnO: Al) in which a small amount of Al is added to ZnO, but is not necessarily limited thereto. Indium tin oxide (ITO), zinc oxide (ZnO), and indium zinc oxide (IZO), which are conventional transparent conductive materials, are not necessarily limited thereto. ), FSO (SnO: F) doped with a small amount of F in SnO, and the like.

The method of forming the reflective layer may include physical vapor deposition such as sputtering and chemical vapor deposition such as LPCVD, PECVD, and MOCVD.

Next, referring to FIG. 2B, according to an embodiment of the present invention, five amorphous silicon layers 310, 320, 330, 340, and 350 may be sequentially stacked on the lower electrode 200. have.

In more detail, the first amorphous silicon layer 310 is formed on the lower electrode 200, and then the second amorphous silicon layer 320 is formed on the first amorphous silicon layer 310, and then the second amorphous silicon layer 310 is formed. The third amorphous silicon layer 330 is formed on the silicon layer 320, and then the fourth amorphous silicon layer 340 is formed on the third amorphous silicon layer 330, and then the fourth amorphous silicon layer 340 is formed. The fifth amorphous silicon layer 350 may be formed on the second amorphous silicon layer 350.

The first to fifth amorphous silicon layers 310, 320, 330, 340, and 350 may be formed using a chemical vapor deposition method such as PECVD or LPCVD.

In this case, the first, third, and fifth amorphous silicon layers 310, 330, and 350 may be formed of a p-type, i-type, and n-type conductive type to form a structure of p, i, n diodes. The second and fourth amorphous silicon layers 320 and 340 formed between the first, third and fifth amorphous silicon layers 310, 330 and 350, respectively, are adjacent to the first and fifth amorphous silicon layers 310 and 350. ) And a conductive type different from each other. That is, n-type may be located between p-type and i-type, and p-type may be located between n-type and i-type.

Preferably, the second and fourth amorphous silicon layers 320 and 340 may be of a conductive type having a lower doping concentration than the neighboring first and fifth amorphous silicon layers 310 and 350. For example, a conductive type of p +, n-, i, p-, n + type, and vice versa may be of a conductive type of n +, p-, i, n-, p + type. The four amorphous silicon layers 320 and 340 may prevent impurities from the heavily doped first and fifth amorphous silicon layers 310 and 350 from diffusing into the third amorphous silicon layer 330. A more detailed description will be understood by the following detailed description with reference to FIGS. 3 and 4.

Next, referring to FIG. 2C, in accordance with an embodiment of the present invention, heat treatment is performed on the first to fifth amorphous silicon layers 310, 320, 330, 340, and 350 to convert the amorphous silicon layer into a polycrystalline silicon layer. Crystallize. That is, the first, third, and fifth amorphous silicon layers 310, 330, and 350 are crystallized into the first, second, and third polycrystalline silicon layers 311, 331, and 351, respectively, by heat treatment. A part or entire region of the second and fourth amorphous silicon layers 320 and 340 may be included in the first and third polycrystalline silicon layers 311 and 351 by heat treatment and may be crystallized.

The crystallization method of the amorphous silicon layer may be any one of solid phase crystallization (SPC), excimer laser annealing (ELA), sequential lateral solidification (SLS), metal induced crystallization (MIC), and metal induced lateral crystallization (MILC). Although the crystallization method of the amorphous silicon is a known technique, a detailed description thereof will be omitted herein.

As a result, the crystallized first, second, and third polycrystalline silicon layers 311, 331, and 351 are p-type, i-type, and n-type polycrystalline silicon layers capable of producing electric power with photovoltaic power generated by receiving light. The stacked p, i, and n diodes 300 may be stacked, or vice versa, and may be a structure of a solar cell.

Next, referring to FIG. 2D, an upper electrode 400 of a transparent conductive material may be formed on the third polycrystalline silicon layer 351. The material of the upper electrode 400 is preferably any one of ITO, ZnO, IZO, AZO (ZnO: Al), and FSO (SnO: F), but is not necessarily limited thereto.

The method of forming the upper electrode 400 may include a physical vapor deposition method such as sputtering and a chemical vapor deposition method such as LPCVD, PECVD, and MOCVD.

On the other hand, the upper electrode 400 may be formed of an opaque metal, which is a known technique that can be applied to the case of the bottom light receiving type will be omitted herein.

Doping Concentration According to Crystallization

3 is a graph showing the doping concentration before crystallization of the p-i-n type solar cell according to an embodiment of the present invention.

4 is a graph showing the doping concentration after crystallization of the p-i-n type solar cell according to an embodiment of the present invention.

First, referring to FIG. 3, the doping concentration of the ideal i-type amorphous silicon layer 330 should be zero as shown in the graphs 30 and 40. That is, in an ideal case, the doping concentration of the i-type amorphous silicon layer 330 may be a high concentration of the p + type amorphous silicon layer 310 and phosphorous formed by doping boron in high concentration during the crystallization heat treatment process. The doping concentration of the n + type amorphous silicon layer 350 formed by doping should not be affected.

However, when the crystallization process starts, the doping concentrations of the p-type (boron) and n-type (phosphorus) actually measured are diffused in the i-type amorphous silicon layer 330 as shown in the graphs 31 and 41 so that the low-doped state (n- , p-). Therefore, unnecessary impurities (boron and phosphorus) are diffused into the i-type amorphous silicon layer 330, thereby reducing the intrinsic region.

Next, referring to FIG. 4, a heat treatment is performed in the state of the doping concentration of FIG. 3, whereby an amorphous silicon layer is crystallized. At this time, the n- and p-type amorphous silicon layers 320 and 340 of the low concentration doping are coupled to the impurities diffused from the neighboring high doping p + and n + type amorphous silicon layers 310 and 350. The polycrystalline silicon layers 311 and 351 may be changed.

In more detail, for example, the n-type amorphous silicon layer 320 positioned between the p + and i-type amorphous silicon layers 310 and 330 may have impurities (boron) of the p + amorphous silicon layer 310 diffused by heat treatment. By the p-type polycrystalline semiconductor layer 311 can be crystallized. Therefore, impurities (boron) of the p + type amorphous silicon layer 310 may be prevented from diffusing into the i type amorphous silicon layer 330 which is a light absorbing layer and crystallized, thereby reducing the decrease in photoelectric conversion efficiency.

Similarly, the p-type amorphous silicon layer 340 positioned between the n + and i-type amorphous silicon layers 350 and 330 is n due to impurities (phosphorus) of the n + amorphous silicon layer 350 diffused by heat treatment. The crystal may be crystallized while being changed into the type polycrystalline semiconductor layer 351. Therefore, it is possible to prevent impurities (phosphorus) of the n + type amorphous silicon layer 350 from diffusing into the i type amorphous silicon layer 330 which is a light absorbing layer and crystallizing, thereby further reducing the decrease in photoelectric conversion efficiency.

In the foregoing detailed description, the present invention has been described by specific embodiments such as specific components and the like, but the embodiments and drawings are provided only to help a more general understanding of the present invention, and the present invention is limited to the above embodiments. However, one of ordinary skill in the art can make various modifications and variations from this description.

Therefore, the spirit of the present invention should not be construed as being limited to the above-described embodiments, and all of the equivalents or equivalents of the claims, as well as the following claims, I will say.

1 is a graph showing the doping concentration according to crystallization of a p-i-n type solar cell according to the prior art.

2A to 2D are cross-sectional views illustrating a manufacturing process of a solar cell using a diffusion barrier layer according to an embodiment of the present invention.

Figure 3 is a graph showing the doping concentration of the initial crystallization state of the p-i-n type solar cell according to an embodiment of the present invention.

4 is a graph showing the doping concentration after crystallization of the p-i-n type solar cell according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: substrate

200: lower electrode

310: first amorphous silicon layer

320: second amorphous silicon layer

330: third amorphous silicon layer

340: fourth amorphous silicon layer

350: fifth amorphous silicon layer

311: first polycrystalline silicon layer

331: second polycrystalline silicon layer

351: third polycrystalline silicon layer

400: upper electrode

Claims (7)

(a) forming a lower electrode on the substrate; (b) forming a lower first amorphous semiconductor layer on the lower electrode; (c) forming a second amorphous semiconductor layer on the lower first amorphous semiconductor layer; (d) forming a third amorphous semiconductor layer on the second amorphous semiconductor layer; (e) forming a fourth amorphous semiconductor layer on the third amorphous semiconductor layer; (f) forming a fifth amorphous semiconductor layer on the fourth amorphous semiconductor layer; (g) heat treating the first to fifth amorphous semiconductor layers to crystallize the first, third, and fifth amorphous semiconductor layers into first, second, and third polycrystalline semiconductor layers, respectively; And crystallizing a part or entire region of a fourth amorphous semiconductor layer in the first and third polycrystalline semiconductor layers; And (h) forming an upper electrode on the third polycrystalline semiconductor layer Method for manufacturing a solar cell comprising a. The method of claim 1, And the second and fourth amorphous semiconductor layers are formed in a different conductivity type than the first and fifth amorphous semiconductor layers adjacent to each other. The method of claim 2, And the second and fourth amorphous semiconductor layers are less doped with impurities than the first and fifth amorphous semiconductor layers adjacent to each other. The method of claim 1, The first to fifth amorphous semiconductor layer is formed of p +, n-, i, p-, n + type, the first to third polycrystalline semiconductor layer is characterized in that the crystallization of p, i, n type Method for producing a battery. The method of claim 1, And the first to fifth amorphous semiconductor layers are formed in n +, p-, i, n-, and p + types, and the first to third polycrystalline semiconductor layers are crystallized in n, i and p types. Method for producing a battery. The method of claim 1, The first to fifth amorphous semiconductor layer is a method of manufacturing a solar cell, characterized in that formed of amorphous silicon. The method of claim 1, The first to third polycrystalline semiconductor layer is a method of manufacturing a solar cell, characterized in that the crystallization of polycrystalline silicon.

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