KR20100076610A - Semiconductor memory device - Google Patents

Abstract

The present invention relates to a technology for transmitting a repair block selection signal to a column fuse circuit, and an object of the present invention is to provide a semiconductor memory device which reduces the number of transmission lines by combining and repairing a repair block selection signal of neighboring memory banks. It is done. According to an aspect of the present invention, a semiconductor memory device having a memory bank including a plurality of cell blocks, the second address corresponding to the block address of the first memory bank and the cell block position of the first memory bank A block selection signal generator for generating a plurality of common repair block selection signals in response to block addresses of the memory banks, a plurality of transmission lines for transmitting the plurality of common repair block selection signals, and a plurality of transmission lines for accessing the memory banks; A semiconductor memory device including a column fuse unit for outputting a column repair address corresponding to the plurality of common repair block selection signals transmitted through the plurality of transmission lines in response to a location information signal is provided.

Description

Technical Field [0001] The present invention relates to a semiconductor memory device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design technology, and more particularly, to a technology for delivering a repair block selection signal to a column fuse circuit.

As the integration technology of the semiconductor memory device (SEMICONDUCTOR MEMORY DEVICE) is advanced, the number of memory cells (CELL) and signal lines in a semiconductor memory device is rapidly increasing, and the line width of the internal circuit is narrow because it is integrated in a limited space. The size of memory cells is also getting smaller. For this reason, the possibility of failure of the memory cell CELL of the semiconductor memory device increases. Even though the cell is defective, the memory having the expected capacity can be shipped with a high yield. This is because there is a redundancy circuit (REDUNDANCY CIRCUIT) to save. The redundancy circuit includes a fuse (FUSE) for programming a repair address (REPAIR ADDRESS) corresponding to the redundancy memory cell and the defective memory cell. In general, when the wafer process (WAFER PROCESS) is completed, various tests are performed. When repair is possible among the memory cells read as defective, the defect is repaired by replacing the memory with a redundant memory cell. That is, the internal circuit performs programming to change the address corresponding to the bad memory cell to the address of the redundancy memory cell. Accordingly, when an address corresponding to the bad memory cell is input, the redundancy memory cell is replaced to perform a normal operation. In order to program address information corresponding to a bad memory cell, a fuse programming method is mainly used. When the fuse is subjected to a laser beam or electrical stress, the electrical resistance of the fuse changes as the electrical characteristics of the fuse change. The electrical connection of these fuses is used to program the address.

For reference, a semiconductor memory device divides an internal memory area into a plurality of banks, and a bank is divided into a plurality of cell blocks. The cell block may also be referred to as a unit cell matrix, a sub cell array, or a mat.

1 is a block diagram of a semiconductor memory device of the prior art.

Referring to FIG. 1, a semiconductor memory device having a memory bank including a plurality of cell blocks may include a first signal for generating a plurality of first bank repair block selection signals corresponding to a block address of a first memory bank Bank0. A bank block selection signal generation unit, a plurality of transmission lines for transmitting a plurality of first bank repair block selection signals, and a plurality of second repair block selection signals corresponding to the block addresses of the second memory bank Bank1; A second bank block selection signal generation unit for generating, a plurality of transmission lines for transmitting the plurality of second repair block selection signals, and a column corresponding to the plurality of first bank repair block selection signals transmitted through the transmission lines A first bank column fuse set for outputting a repair address and a column corresponding to a plurality of second bank repair block selection signals transmitted through a transmission line A second bank column fuse unit for outputting a repair address is provided.

The first bank block selection signal generation unit may include a plurality of first bank repair block selection signals generated in the row decoder X-Dec allocated to the first memory bank Bank0 through a transmission line. RPT), and a plurality of first bank repair block selection signals are transmitted from the repeater (RPT) to the first bank column fuse set.

In addition, the second bank block selection signal generation unit may include a plurality of second bank repair block selection signals generated in the row decoder X-Dec allocated to the second memory bank Bank1 through a transmission line. And a plurality of second bank repair block selection signals from the repeater (RPT) to the second bank column fuse unit (Fuse Set).

The column fuse unit assigned to each memory bank outputs a column repair address corresponding to a plurality of first bank repair block selection signals or a plurality of second bank repair block selection signals when its memory bank is accessed. do.

The detailed configuration and main operations of the semiconductor memory device configured as described above are as follows.

2 is a circuit diagram of a block select signal generator.

Referring to FIG. 2, the block selection signal generator 200 may include a plurality of repair block selection signals XMATYF <0:15> corresponding to the block addresses XMATB <0:15> of a corresponding memory bank in an active operation mode. It consists of a plurality of logical combinations (200_1, 200_2, ..., 200_16) for generating a.

Since the plurality of logic combination units 200_1, 200_2,..., 200_16 are configured with the same circuit, the first logical combination unit 200_1 will be described in detail.

The first logic combiner 200_1 receives a first negative logic means NOR1 for inputting an active signal R2ACB and a refresh signal REFDD, and an output signal for the first negative logic means NOR1 for input. Second negative logic means NOR2 for inputting the first inverter INV1, the output signal of the first inverter INV1, and the first block address bit signal XMATB <0>, and the second negative logic means NOR2. A second inverter (INV2) for inputting a signal output from the () and a third inverter (INV3) for inputting the signal output from the second inverter (INV2).

The first logic combination unit 200_1 may be configured to have a first block address of a memory bank accessed when the active signal R2ACB is activated at a low level and the refresh signal REFDD is deactivated at a low level, that is, in an active operation mode. When the bit signal XMATB <0> is activated, the first repair block selection signal XMATYF <0> is activated and output. Accordingly, the block select signal generator 200 generates a plurality of repair block select signals XMATYF <0:15> when the semiconductor memory device operates in the active operation mode.

In this case, since the plurality of repair block selection signals XMATYF <0:15> are generated for each memory bank and transmitted through each transmission line, the repair block selection signals XMATYF <0:15> for each memory bank are transmitted. Each transmission line should be arranged.

3 is a circuit diagram of the column fuse of FIG. 1.

Referring to FIG. 3, the column fuse unit 300 includes a plurality of fuse sets 300_1, 300_2,..., 300_6, and the plurality of fuse sets 300_1, 300_2,..., 300_6 are each configured with the same circuit. For example, the first fuse set 300_1 will be described in detail. For reference, the number of fuses SET is the same as the number of bits of the repair address. In the present embodiment, since the number of fuse sets SET is six, the number of bits of the column repair address YRA <0: 5> may be six bits in total. Also, the number of fuses in the fuse set is equal to the number of cell blocks allocated to the memory bank in this example. Therefore, when the first repair block selection signal XMATYF <0> of the repair block selection signals XMATYF <0:15> is activated, each of the first to sixth fuse sets 300_1, 300_2,..., 300_6 The column repair address (YRA <0: 5>) corresponding to the electrical state of the first fuse will be output.

The first fuse set 300_1 includes a precharge unit 310 for precharging the common node N0 in response to the precharge signal WLCBYFB, and a plurality of fuses connected to the common node N0 and connected in parallel to each other. And a pull-down driver 330 connected to the plurality of fuses 320 to selectively pull down the connection nodes of the plurality of fuses 320 in response to the plurality of repair block selection signals XMATYF <0:15>. ) And an output unit 340 connected to the common node N0 for outputting the first column repair address bit signal YRA <0>.

In the present exemplary embodiment, the precharge unit 310 is composed of an NMOS transistor MN0 connected between the power supply voltage terminal VDD and the common node N0 and controlled by the precharge signal WLCBYFB. The precharge signal WLCBYFB is deactivated in the active mode and, when activated, precharges the common node N0 to the power supply voltage VDD. In addition, the pull-down driving unit 330 is connected to each of the connection nodes of the plurality of fuses 320 and the other end is connected to the ground voltage terminal VSS to control the plurality of repair block selection signals XMATYF <0:15>. It consists of a number of NMOS transistors. In addition, the output unit 340 includes a latch unit 341 for latching a signal output from the common node NO and an inverter INV3 for inputting a signal output from the latch unit 341.

First, when the precharge signal WLCBYFB is activated, the first fuse set 300_1 precharges the common node N0 using the power supply voltage VDD, so that the output unit 340 outputs the common node N0. The signal is latched and finally the first column repair address bit signal YRA <0> is output at a high level which is an initial value.

Next, when entering the active operation mode, the precharge signal WLCBYFB is deactivated to stop the precharge operation on the common node N0 and is activated among the plurality of repair block selection signals XMATYF <0:15>. The voltage level of the common node N0 is changed by the repair block selection signal XMATYF <i> and the electrical state of the fuse, and the logic level of the first column repair address bit signal YRA <0> is changed according to the voltage level. This is determined. For example, assuming that the first repair block selection signal XMATYF <0> is activated and the first fuse is connected, the potential level of the common node N0 is lowered to the ground voltage level due to a pull-down operation. The first column repair address bit signal YRA <0> is output at a low level. This operation is simultaneously performed on the first to sixth fuse sets 300_1 to 300_6, and the column repair address bit signals YRA <0: 5> are output.

That is, the conventional semiconductor memory device as described above includes a transmission line for each memory bank for transmitting a repair block selection signal corresponding to the block address of the memory bank. As a result, a large number of transmission lines may limit the size of the semiconductor memory device.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-described problems, and an object thereof is to provide a semiconductor memory device which reduces the number of transmission lines by combining and transmitting repair block selection signals of neighboring memory banks. .

According to an aspect of the present invention for achieving the above technical problem, in a semiconductor memory device having a memory bank including a plurality of cell blocks, the block address of the first memory bank and the cell block of the first memory bank A block selection signal generator for generating a plurality of common repair block selection signals in response to block addresses of a second memory bank corresponding to a position; A plurality of transmission lines for transmitting the plurality of common repair block selection signals; And a column fuse unit configured to output column repair addresses corresponding to the plurality of common repair block selection signals transmitted through the plurality of transmission lines in response to the position information signals of the memory banks to be accessed. .

The semiconductor memory device to which the present invention is applied can reduce the number of transmission lines for transmitting the repair block selection signal, thereby reducing the overall size of the semiconductor memory device. Therefore, it is more advantageous in terms of cost by increasing the number of semiconductor memory devices that can be manufactured with one wafer, that is, 'NET DIE'.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. . For reference, in the drawings and detailed description, terms, symbols, symbols, etc. used to refer to elements, blocks, etc. may be represented by detailed units as necessary, and therefore, the same terms, symbols, symbols, etc. are the same in the entire circuit. Note that it may not refer to.

In general, the logic signal of the circuit is divided into a high level (HIGH LEVEL, H) or a low level (LOW LEVEL, L) corresponding to the voltage level, and may be expressed as '1' and '0', respectively. In addition, it is defined and described that it may additionally have a high impedance (Hi-Z) state and the like. In addition, PMOS (P-channel Metal Oxide Semiconductor) and N-channel Metal Oxide Semiconductor (NMOS), which are terms used in the present embodiment, are known to be a type of MOSFET (Metal Oxide Semiconductor Field-Effect Transistor).

4 is a configuration diagram of a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 4, a semiconductor memory device having a memory bank including a plurality of cell blocks may include a second memory corresponding to a block address of a first memory bank Bank0 and a cell block position of a first memory bank Bank0. A block selection signal generator for generating a plurality of common repair block selection signals in response to the block addresses of the bank Bank1, a plurality of transmission lines for transmitting the plurality of common repair block selection signals, and a memory bank to be accessed And a column fuse unit for outputting a column repair address corresponding to the plurality of common repair block selection signals transmitted through the plurality of transmission lines in response to the position information signal of the plurality of transmission lines.

The block select signal generator transmits a plurality of common repair block select signals generated by being located inside the row decoder X-Dec to a repeater (RPT) through a transmission line, and then again in each of the repeaters (RPT). A plurality of common repair block selection signals are transmitted to a column fuse set allocated to the bank.

A column fuse set assigned to each bank outputs a column repair address corresponding to a plurality of common repair block selection signals transmitted through a plurality of transmission lines when the allocated memory bank is accessed. That is, the common repair block selection signal is generated by combining the block address of the first memory bank Bank0 with the block address of the second memory bank Bank1 corresponding to the block position of the first memory bank Bank0. The number of transmission lines required for transmitting the selection signal to the column fuse set through the transmission line is reduced by half compared to that without combining.

The detailed configuration and main operations of the semiconductor memory device configured as described above are as follows.

5 is a circuit diagram according to an embodiment of a block selection signal generator.

Referring to FIG. 5, the block select signal generator 500 may include a block address XMATB0 <0:15> of a first memory bank Bank0 and a cell block position of a first memory bank in an active operation mode. A plurality of logic combination units for generating a plurality of common repair block selection signals XMATYF <0:15> corresponding to a result of logically combining the block addresses XMATB1 <0:15> of the two memory banks Bank1 ( 500_1,500_2, ..., 500_16).

Since the plurality of logic combination units 500_1, 500_2,..., 500_16 are each configured with the same circuit, the first logic combination unit 500_1 will be described in detail.

The first logic combiner 500_1 includes a first negative logic unit NOR1 for inputting an active signal R2ACB and a refresh signal REFDD, and a first block address bit signal XMATB0 of the first memory bank Bank0. Output from the second negative logical means (NOR2) and the first negative logical means (NOR1) for inputting <0> and the first block address bit signal XMATB1 <0> of the second memory bank Bank1. Output from the first inverter INV1 that takes a signal as input, the second inverter INV2 that takes the signal output from the second negative logic means NOR2, and the first and second inverters INV1 and INV2. The third negative logic unit NOR3 that takes a signal as an input, the third inverter INV3 that receives a signal output from the third negative logic unit NOR3, and the signal output from the third inverter INV3. It consists of the 4th inverter INV4 which inputs as an input.

The first logic combination unit 500_1 is configured to activate the first memory bank Bank0 in the active operation mode when the active signal R2ACB is activated at a low level and the refresh signal REFDD is deactivated at a low level. The first common repair block selection signal XMATYF when any one or more of the first block address bit signal XMATB0 <0> and the first block address bit signal XMATB1 <0> of the second memory bank Bank1 are activated. <0>) is activated and output. Accordingly, the block selection signal generator 500 generates a plurality of common repair block selection signals XMATYF <0:15> when the semiconductor memory device operates in the active operation mode.

The common repair block selection signal XMATYF <0:15> may be configured to convert the block addresses XMATB0 <0:15> and XMATB1 <0:15> of the first memory bank Bank0 and the second memory bank Bank1. Since the signals are generated in combination, the repair block selection signals XMATYF <0:15> corresponding to the block addresses XMATB0 <0:15> of the first memory bank Bank0 and the second block address are not combined. The number of transmission lines is reduced by half than when the repair block selection signals XMATYF <0:15> corresponding to the block addresses XMATB1 <0:15> of the memory bank Bank1 are simultaneously transmitted.

6 is a circuit diagram according to an embodiment of the column fuse of FIG. 4.

Referring to FIG. 6, the column fuse unit 600 includes a plurality of fuse sets 600_1, 600_2,..., 600_6, and the plurality of fuse sets 600_1, 600_2,. For example, the first fuse set 600_1 will be described in detail. For reference, the number of fuses SET is the same as the number of bits of the repair address. In the present embodiment, since the number of fuse sets SET is six, the number of bits of the column repair address YRA <0: 5> may be six bits in total. In addition, the number of fuses in the fuse set is equal to the number of cell blocks allocated to the memory bank in this embodiment. Therefore, when the first common repair block selection signal XMATYF <0> is activated among the plurality of common repair block selection signals XMATYF <0:15>, the first to sixth fuse sets 600_1, 600_2, ..., 600_6 The column repair address (YRA <0: 5>) corresponding to the electrical state of each first fuse of the C1 will be output.

The first fuse set 600_1 includes a precharge unit 610 for precharging the common node N0 in response to the precharge signal WLCBYFB, and a plurality of fuses connected to the common node N0 and connected in parallel with each other. 620 and a plurality of fuses 620 connected to the plurality of fuses 620 in response to the plurality of common repair block selection signals XMATYF <0:15> and the location information signal BA of the corresponding memory bank. A pull-down driver 630 for selectively pulling down the connection node, and an output unit 640 connected to the common node N0 to output the first column repair address bit signal YRA <0>.

In the present exemplary embodiment, the precharge unit 610 is configured of an NMOS transistor MN0 connected between the power supply voltage terminal VDD and the common node N0 and controlled by the precharge signal WLCBYFB. The precharge signal WLCBYFB is deactivated in the active mode and, when activated, precharges the common node N0 to the power supply voltage VDD. In addition, the pull-down driver 630 may be connected to each of the connection nodes of the plurality of fuses 620 and may be controlled by a plurality of common repair block selection signals XMATYF <0:15>. Each transistor of the NMOS transistor group is connected one-to-one and the other end of the second NMOS transistor group is connected to the ground voltage terminal VSS and is controlled by the position information signal BA of the corresponding memory bank. In addition, the output unit 640 includes a latch unit 641 for latching a signal output from the common node NO, and an inverter INV3 for inputting a signal output from the latch unit 641.

First, when the precharge signal WLCBYFB is activated, the first fuse set 600_1 precharges the common node N0 using the power supply voltage VDD, so that the output unit 640 outputs the common node N0. The signal is latched and finally the first column repair address bit signal YRA <0> is output at a high level which is an initial value.

Next, when entering the active mode, the precharge signal WLCBYFB is deactivated to stop the precharge operation on the common node N0, and the allocated memory bank is accessed to access the location information signal BA of the corresponding memory bank. When is activated, the voltage level of the common node N0 is increased by the activated common repair block selection signal XMATYF <i> and the electrical state of the fuse among the plurality of common repair block selection signals XMATYF <0:15>. The logic level of the first column repair address bit signal YRA <0> is determined according to the changed voltage level. For example, assuming that the first common repair block selection signal XMATYF <0> is activated and the first fuse is connected, the potential level of the common node N0 is lowered to the ground voltage level due to a pull-down operation. The first column repair address bit signal YRA <0> is output at a low level. This operation is performed in the first to sixth fuse sets 600_1 to 600_6, and finally the column repair address bit signals YRA <0: 5> are output.

In the above, the specific description was made according to the embodiment of the present invention. Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

For example, the configuration of an active high or an active low to indicate an activation state of a signal and a circuit may vary according to embodiments. In addition, the configuration of the transistor may be changed as necessary to implement the same function. That is, the configurations of the PMOS transistor and the NMOS transistor may be replaced with each other, and may be implemented using various transistors as necessary.

In particular, in order to clearly describe the technical idea of the present invention, the number of memory banks, the number of block addresses allocated to the memory banks, the number of repair address bits, the number of fuses of the fuse set, etc. are specified and described. Will vary. Such a change in the circuit is too many cases, and the change can be easily inferred by a person skilled in the art, so the enumeration thereof will be omitted.

1 is a block diagram of a semiconductor memory device of the prior art.

2 is a circuit diagram of a block select signal generator.

3 is a circuit diagram of the column fuse of FIG. 1.

4 is a configuration diagram of a semiconductor memory device according to an embodiment of the present invention.

5 is a circuit diagram according to an embodiment of a block selection signal generator.

6 is a circuit diagram according to an embodiment of the column fuse of FIG. 4.

* Explanation of symbols for the main parts of the drawings

500: block selection signal generation unit

610: precharge unit

620: multiple fuses

630: pull-down drive unit

In the figure, PMOS transistors and NMOS transistors are denoted by MPi and MNi (i = 0, 1, 2, ...), respectively.

Claims (8)

In a semiconductor memory device having a memory bank including a plurality of cell blocks, A block selection signal generator for generating a plurality of common repair block selection signals in response to block addresses of a first memory bank and block addresses of a second memory bank corresponding to cell block positions of the first memory bank; A plurality of transmission lines for transmitting the plurality of common repair block selection signals; And A column fuse unit for outputting a column repair address corresponding to the plurality of common repair block selection signals transmitted through the plurality of transmission lines in response to the position information signal of the memory bank to be accessed; A semiconductor memory device having a. The method of claim 1, The block selection signal generation unit, In the active operation mode, the plurality of common repair block selection signals corresponding to a result of ORing the block address of the first memory bank and the block address of the second memory bank corresponding to the cell block position of the first memory bank, respectively, may be generated. And a plurality of logic combinations for generating. The method of claim 2, Each of the plurality of logical combinations, First negative logic means for receiving an active signal and a refresh signal as inputs; Second negative logic means for inputting a block address bit signal of the first memory bank and a block address bit signal of the second memory bank; A first inverter configured to receive a signal output from the first negative logic means; A second inverter configured to receive a signal output from the second negative logic means; Third negative logic means for inputting signals output from the first and second inverters; A third inverter configured to receive a signal output from the third negative logic means; And And a fourth inverter configured to receive a signal output from the third inverter. The method of claim 1, The column fuse unit, And a plurality of fuse sets, each of the plurality of fuse sets, A precharge unit for precharging the common node in response to the precharge signal; A plurality of fuses connected to the common node and connected in parallel to each other; A pull-down driver connected to the plurality of fuses to selectively pull down the connection nodes of the plurality of fuses in response to the plurality of common repair block selection signals and the location information signal; And And an output unit connected to the common node to output a corresponding column repair address bit signal. The method of claim 4, wherein The precharge unit, And a transistor connected between a power supply voltage terminal and the common node to control the precharge signal. The method of claim 4, wherein The pull-down drive unit, A first transistor group connected to each of the connection nodes of the plurality of fuses and controlled by the plurality of common repair block selection signals; And And a second transistor group, one end of which is connected one-to-one with each transistor of the first transistor group, and the other end of which is connected to a ground voltage terminal to control the position information signal. The method of claim 4, wherein And the precharge signal is deactivated in an active operation mode. The method of claim 4, wherein The output unit, A latch unit for latching a signal output from the common node; And And an inverter for inputting a signal output from the latch unit.

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