KR20100055977A - Thin film transistor substrate for liquid crystal display device - Google Patents

Abstract

The present invention relates to a thin film transistor array substrate for a liquid crystal display device, wherein the thin film transistor array substrate for a liquid crystal display device intersects first and second gate lines formed adjacent to each other and the first and second gate lines. Common data lines defining first and second pixels, first and second gate electrodes protruding from the first and second gate lines, and the first and second gate lines. First and second auxiliary electrodes of a gate line protruding into a second pixel, and first and second source electrodes protruding from the common data line to the first and second gate electrodes, and the first and second sources First and second drain electrodes spaced apart from the electrode by a predetermined distance and overlapping the first and second gate electrodes, pixel electrodes formed in the first and second pixels, respectively, and the first and second electrodes in the pixel electrode. 2 protrudes into the gate line, the As the overlapping first and second auxiliary electrodes and a portion of the byte at the same time line includes a first, a second auxiliary electrode of the pixel electrode connected with the drain electrode.

Description

Thin film transistor array substrate for liquid crystal display device {THIN FILM TRANSISTOR SUBSTRATE FOR LIQUID CRYSTAL DISPLAY DEVICE}

The present invention relates to a liquid crystal display device, and more particularly, to a thin film transistor array substrate for a liquid crystal display device sharing data wiring.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. Recently, liquid crystal display (LCD), plasma display panel (PDP), electro luminescent display (ELD), and VFD (vacuum) Various flat panel displays such as fluorescent displays are used. Among flat panel displays, liquid crystal displays are widely used because they have advantages of miniaturization, light weight, thinness, and low power driving.

The liquid crystal display device includes a liquid crystal interposed between a thin film transistor substrate and a color filter substrate facing each other. In general, a liquid crystal display device is driven by displaying an image by changing a liquid crystal array by an electric field generated between a pixel electrode and a common electrode formed on two substrates.

A thin film transistor array substrate for a liquid crystal display device generally has thin film transistors arranged at the same position in the same column for one data wiring, but in order to reduce the number of data driver ICs, the data wirings are adjacent to the left and right pixels. A shared thin film transistor array substrate can be used.

1 is a plan view of a thin film transistor array substrate for a liquid crystal display device sharing a data wiring according to the prior art, FIG. 2A is a detailed view of the first thin film transistor of FIG. 1, and FIG. 2B is a line II ′ of FIG. 2A. It is a cross section of.

As shown in FIG. 1, a thin film transistor array substrate for a liquid crystal display according to the related art has a structure in which pixels disposed adjacent to left and right share a data line and time-division data to each pixel.

The thin film transistor array substrate for a liquid crystal display according to the present invention includes first and second gate lines 111a and 111b provided to neighboring first and second pixels P1 and P2, and the first and second gate lines ( A common data line 112 that vertically intersects 111a and 111b and supplies a time-divided data signal to the first and second pixels P1 and P2 is formed, and the first and second gate lines 111a and 111b are formed. First and second thin film transistors TFT1 and TFT2 are formed at an intersection point of the data line 112.

The first and second gate lines 111a and 111b are spaced apart from each other with the pixel interposed therebetween, and the first and second thin film transistors TFT1 and TFT2 are alternately symmetrical with the common data line 112 interposed therebetween. Is formed.

As shown in FIGS. 2A and 2B, the first thin film transistor TFT1 includes a gate electrode 121a protruding from the first gate line 111a and a gate formed on the gate electrode 121a. An insulating film 125, a semiconductor layer 116a formed on the gate insulating film 125, a source electrode 122a and a drain electrode 124a contacting a predetermined region on the semiconductor layer 116a, and the source electrode ( 122a and a passivation layer 127 formed on the drain electrode 124a, and a pixel electrode 113a formed on the passivation layer 127 in the first pixel P1 by being connected to the drain electrode 124a. .

Here, the first thin film transistor TFT1 forms a first gate-source capacitor Cgs1 between the gate electrode 121a and the drain electrode 124a, and a first pixel on the gate line 111a. A first auxiliary gate-source capacitor Cx1 is formed between the auxiliary electrode 131a that protrudes into the P1 and the drain electrode 124a which is formed to extend near the auxiliary electrode 131a.

A first gate-source capacitor Cgs1 value formed between the gate electrode 121a and the drain electrode 124a and a first auxiliary gate-source capacitor formed between the auxiliary electrode 131a and the drain electrode 124a. The sum of the (Cx1) values is almost constant.

That is, during the photo process for forming the source electrode 122a and drain electrode 124a patterns, a photo mask is twisted so that the source electrode 122a and drain electrode 124a patterns are twisted up, down, left, and right. In this case, the parasitic capacitance Cgs difference, which is the capacitance of the first gate-source capacitor, is generated, so that the level shift voltage is changed, and the luminance difference is generated between the left and right adjacent pixels. Such a difference in the level shift voltage causes a poor image quality in the form of a dim in the vertical direction. Accordingly, the increase and decrease of the value of the first gate-source capacitor Cgs1 of the first thin film transistor TFT1 may be compensated by the first auxiliary gate-source capacitor Cx1, and thus, the gate electrode 121a and the The sum of the value of the first gate-source capacitor Cgs1 formed between the drain electrode 124a and the value of the first auxiliary gate-source capacitor Cx1 formed between the auxiliary electrode 131a and the drain electrode 124a is Almost constant.

Meanwhile, the gate electrode, the source electrode (or the drain electrode), the gate line, and the data of the thin film transistor are formed by the conductive foreign material remaining after the thin film transistor and the gate line and / or data line are generated in the process of manufacturing the thin film transistor array substrate as described above. Short lines may occur.

In this case, the thin film transistor is cut through a welding process using a laser or the like to darken the thin film transistor, and a repairing method is used. The thin film transistor array substrate sharing the data wiring as described above is shown in FIG. 2B. As shown, the regions A and B where the gate electrode 121a and the drain electrode 124a overlap, that is, the first gate-source capacitor Cgs1 and the first auxiliary gate-source capacitor Cx1 are formed. Each pixel is irradiated with a laser to electrically conduct the gate electrode 121a and the drain electrode 124a so as to electrically darken the defective pixel.

However, the point B on which the first auxiliary gate-source capacitor Cx1 is formed, which is a region to which the laser is irradiated, is an area required to compensate the value of the first gate-source capacitor as described above. Considering the variation according to the electrode pattern formation has a limited area.

Therefore, when the welding process is performed in the limited area as described above, there is a problem that the success rate of the welding process is lowered and the yield improvement through dark ignition is lowered.

An object of the present invention for solving the above problems is to provide a thin film transistor array substrate for a liquid crystal display device that can improve the success rate of the welding process.

According to an exemplary embodiment of the present invention, a thin film transistor array substrate for liquid crystal display devices includes adjacent first and second gate lines and first and second gate lines intersecting the first and second gate lines. A common data line defined, first and second gate electrodes formed to protrude from the first and second gate lines, and gates protruded into the first and second pixels from the first and second gate lines. The first and second auxiliary electrodes of the line and the first and second source electrodes protruding from the common data line to the first and second gate electrodes, the first and second source electrodes being spaced apart from each other by a predetermined distance. First and second drain electrodes overlapping with the first and second gate electrodes, pixel electrodes formed in the first and second pixels, and protruding from the pixel electrode to the first and second gate lines, and First and second auxiliary electrodes and certain portions of the gate line As the overlap at the same time a first, a second auxiliary electrode of the pixel electrode connected with the drain electrode.

A capacitor is formed in an overlapping region of the first and second gate electrodes and the first and second drain electrodes, and the first and second auxiliary electrodes of the gate line and the first and second auxiliary electrodes of the pixel electrode. An auxiliary capacitor is formed in the overlap region.

The sum of the capacitor and the auxiliary capacitor capacity has a constant value.

The sum of the overlapping region of the first gate electrode and the first drain electrode and the overlapping region of the first auxiliary electrode of the gate line and the first auxiliary electrode of the pixel electrode is equal to that of the second gate electrode and the first drain electrode. It is equal to the sum of the overlapping region and the overlapping region of the second auxiliary electrode of the gate line and the second auxiliary electrode of the pixel electrode.

The first and second drain electrodes forming the capacitor and the first and second auxiliary electrodes of the pixel electrode forming the auxiliary capacitor are areas irradiated with a laser to perform a welding process.

A thin film transistor array substrate for a liquid crystal display according to the present invention for achieving the above object is formed by forming a first auxiliary gate-source capacitor through an auxiliary electrode of a gate wiring and an auxiliary electrode of the pixel electrode, thereby forming a first gate-source. Compensation of the capacitor value is increased and at the same time, it is possible to improve the success rate of the welding process performed when a short occurs between the gate electrode (or line) and the source electrode (or data line).

3 is a plan view showing a portion of a thin film transistor array substrate for a liquid crystal display device according to an exemplary embodiment of the present invention, FIG. 4A is a detailed view of the first thin film transistor of FIG. 2, and FIG. 4B is II- of FIG. 4A. FIG. 5A is a detailed view of the second thin film transistor of FIG. 2, and FIG. 5B is a cross-sectional view of the III-III ′ line of FIG. 5A.

As illustrated in FIG. 3, in the thin film transistor array substrate for a liquid crystal display according to the present invention, pixels arranged adjacent to the left and the right share a data line.

In an exemplary embodiment, a thin film transistor array substrate for a liquid crystal display device may include first and second gate lines 211a and 211b provided to neighboring first and second pixels P1 and P2, and the first and second gate lines ( A common data line 212 that vertically intersects 211a and 211b and supplies time-divided data signals to the first and second pixels P1 and P2 is formed, and the first and second gate lines 211a and 211b are formed. First and second thin film transistors TFT1 and TFT2 are formed at an intersection point of the data line 212.

The first and second gate lines 211a and 211b are spaced apart from each other with the pixel interposed therebetween, and the first and second thin film transistors TFT1 and TFT2 are alternately symmetrical with the common data line 212 interposed therebetween. Is formed.

As shown in FIGS. 4A and 4B, the first thin film transistor TFT1 may include a gate electrode 221a protruding from the first gate line 211a and a semiconductor layer formed on the gate electrode 221a. 216a, a source electrode 222a and a drain electrode 224a in contact with a predetermined region on the semiconductor layer 216a, and a pixel electrode formed in the first pixel P1 by being connected to the drain electrode 224a. 213a).

Here, the first thin film transistor TFT1 forms a first gate-source capacitor Cgs11 between the gate electrode 221a and the drain electrode 224a, and forms a first pixel (eg, a second pixel) in the gate line 211a. A first auxiliary gate-source capacitor Cx11 is formed between the auxiliary electrode 231a that protrudes into the P1 and the auxiliary electrode 233a that protrudes in the direction of the gate line 211a from the pixel electrode 213a. .

At this time, the auxiliary electrode 233a of the pixel electrode overlaps the drain electrode 224a while overlapping with the auxiliary electrode 231a of the gate wiring.

The auxiliary electrode 231a of the gate wiring and the auxiliary electrode 233a of the pixel electrode forming the first auxiliary gate-source capacitor Cx11 compensate for the increase and decrease of the value of the first gate-source capacitor Cgs11. It is formed and used as a region where a welding process is performed when a short occurs between the gate electrode (or line) and the source electrode (or data line).

In other words, as shown in FIG. 4B, the first auxiliary gate-source capacitor Cx11 includes the auxiliary electrode 231a of the gate electrode, the gate insulating layer 217, the passivation layer 227, and the auxiliary electrode 233a of the pixel electrode. By stacking the capacitors to form capacitance, a first gate-source which may be generated when the photo mask is twisted and the source and drain electrode patterns are twisted up, down, left, and right during the photo process for forming the source electrode and the drain electrode pattern. The increase or decrease of the capacitor Cgs11 value can be compensated.

Accordingly, the increase and decrease of the value of the first gate-source capacitor Cgs11 of the first thin film transistor TFT1 may be compensated by the first auxiliary gate-source capacitor Cx11, and thus the gate electrode 221a and the drain may be compensated for. The first gate-source capacitor Cgs11 formed between the electrodes 224a and the first auxiliary gate-source capacitor Cx11 formed between the auxiliary electrode 231a of the gate electrode and the auxiliary electrode 233a of the pixel electrode. The sum of) is almost constant.

In addition, a short circuit between a gate electrode (or a line) and a source electrode (or a data line) may occur in a process of forming the thin film transistor. The transistor is darkened.

As shown in FIG. 4B, the drain electrode 224a of the first gate-source capacitor Cgs11 and the pixel electrode of the first auxiliary gate-source capacitor Cx11 are disposed on the thin film transistor array substrate sharing the data line. The drain electrode 224a and the pixel electrode 233a are cut by irradiating a laser to 233a to penetrate through the gate electrode 222a and the auxiliary electrode 231a, respectively (in the paths C and D shown in FIG. 4B). Penetrates). At this time, since the auxiliary electrode 233a of the pixel electrode, which is the uppermost layer of the first auxiliary gate-source capacitor Cx11, has a larger area than the area of the conventional drain electrode, easy laser irradiation is performed, and thus, the welding process is performed. The success rate can be improved.

Meanwhile, in the neighboring second pixel P2 that shares the common data line 212 with the first pixel P1, the second thin film transistor TFT2 is formed as shown in FIGS. 5A and 5B. A gate electrode 221b protruding from the second gate line 211b, a semiconductor layer 216b formed on the gate electrode 221b, and a source electrode 222b contacting a predetermined region on the semiconductor layer 216b. ) And a drain electrode 224b and a pixel electrode 213b formed in the second pixel P2 in contact with the drain electrode 224b.

Here, the second thin film transistor TFT2 forms a second gate-source capacitor Cgs12 between the gate electrode 221b and the drain electrode 224b, and a second pixel on the gate line 211b. (P2) A second auxiliary gate-source capacitor Cx12 is formed between the auxiliary electrode 231b that protrudes into the inside and the auxiliary electrode 233b that protrudes in the direction of the gate line 211b from the pixel electrode 213b. do.

At this time, the auxiliary electrode 233b of the pixel electrode overlaps the drain electrode 224b while overlapping with the auxiliary electrode 231b of the gate wiring.

The auxiliary electrode 231b of the gate wiring and the auxiliary electrode 233b of the pixel electrode forming the second auxiliary gate-source capacitor Cx12 compensate for the increase and decrease of the value of the second gate-source capacitor Cgs12. It is formed and used as a region where a welding process is performed when a short occurs between the gate electrode (or line) and the source electrode (or data line).

In other words, the second auxiliary gate-source capacitor Cx12 forms a capacitance by stacking the auxiliary electrode 231b of the gate electrode, the gate insulating film 217, the passivation layer 227, and the auxiliary electrode 233b of the pixel electrode. In the photo process for forming the source electrode and the drain electrode pattern, the increase or decrease of the value of the second gate-source capacitor Cgs12 that may occur when the photo mask is twisted and the source electrode and drain electrode pattern is twisted up, down, left, and right. You can compensate.

Therefore, the increase and decrease of the value of the second gate-source capacitor Cgs12 of the second thin film transistor TFT2 may be compensated by the second auxiliary gate-source capacitor Cx11, and thus the gate electrode 221b and the drain may be compensated. The second gate-source capacitor Cgs1b formed between the electrodes 224b and the second auxiliary gate-source capacitor formed between the auxiliary electrode 231b of the gate electrode and the auxiliary electrode 233b of the pixel electrode. The sum of the Cx12) values is almost constant.

In addition, a short circuit between the gate electrode (or line) and the source electrode (or data line) may occur in the process of forming the thin film transistor. In this case, the thin film transistor is cut by a welding process using a laser or the like. Darkening.

As shown in FIG. 5B, the drain electrode 224b of the first gate-source capacitor Cgs12 and the pixel electrode of the first auxiliary gate-source capacitor Cx12 share a thin film transistor array substrate sharing the data line. The laser is irradiated to 233b to cut the drain electrode 224b and the pixel electrode 233b to penetrate through the gate electrode 222b and the auxiliary electrode 231b, respectively (as the paths C and D shown in FIG. Penetrates). At this time, since the auxiliary electrode 233b of the pixel electrode, which is the uppermost layer of the first auxiliary gate-source capacitor Cx12, has an area larger than that of the conventional drain electrode, easy laser irradiation is performed, and thus, the welding process is performed. The success rate can be improved.

Therefore, in the first thin film transistor TFT1 and the second thin film transistor TFT2 driven by the common data line 212, the pattern of the source electrodes 222a and 222b and the drain electrodes 224a and 224b. Is misaligned, the sum of the values of the first and second gate-source capacitors Cgs11 and Cgs12 and the values of the first and second auxiliary gate-source capacitors Cx11 and Cx12 is not only equal to the capacitance in the initial design. The sum of the value of the first gate-source capacitor value Cgs11 and the first auxiliary gate-source capacitor Cx11 is equal to the value of the second gate-source capacitor Cgs12 and the second auxiliary gate-source capacitor Cx12. It is almost equal to the value of.

That is, patterns of the source electrodes 222a and 222b and the drain electrodes 224a and 224b branched from the common data line 212 in the first and second pixels P1 and P2 using the common data line 212 are formed. Values of the first and second gate-source capacitors Cgs11 and Cgs12 respectively formed in the first and second thin film transistors TFT1 and TFT2 when shifted in one of the up, down, left, and right directions. Since is compensated by the first and second auxiliary gate-source capacitors Cx11 and Cx12, the overall gate-source capacitor capacity is uniform in the first and second pixels P1 and P2, and quality defects can be prevented.

In addition, the auxiliary electrodes 233a and 233b of the pixel electrode, which are the uppermost layers of the first and second auxiliary gate-source capacitors Cx12, have a larger area than that of a conventional drain electrode, which is a region where a welding process is performed. It is possible to improve the success rate of the welding process performed when a short occurs between the electrode (or line) and the source electrode (or data line).

1 is a plan view of a thin film transistor array substrate for a liquid crystal display device sharing data wiring according to the prior art.

FIG. 2A is a detailed view of the first thin film transistor of FIG. 1, and FIG. 2B is a cross-sectional view taken along line II ′ of FIG. 2A.

3 is a plan view illustrating a portion of a thin film transistor array substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

4A is a detailed view of the first thin film transistor of FIG. 2, and FIG. 4B is a cross-sectional view taken along line II-II ′ of FIG. 4A.

FIG. 5A is a detailed view of the second thin film transistor of FIG. 2, and FIG. 5B is a cross-sectional view taken along line III-III ′ of FIG. 5A.

Claims (5)

Adjacent first and second gate lines, A common data line crossing the first and second gate lines to define first and second pixels; First and second gate electrodes formed to protrude from the first and second gate lines; First and second auxiliary electrodes of the gate lines protruding from the first and second gate lines into the first and second pixels; First and second source electrodes protruding from the common data line to the first and second gate electrodes, and a first overlapping with the first and second gate electrodes spaced apart from the first and second source electrodes by a predetermined distance. 1, the second drain electrode, Pixel electrodes formed on the first and second pixels, respectively; First and second auxiliary electrodes of the pixel electrode protruding from the pixel electrode to the first and second gate lines and partially overlapping the first and second auxiliary electrodes of the gate line and simultaneously connected to the drain electrode; A thin film transistor array substrate provided for a liquid crystal display device. According to claim 1, A capacitor is formed in an overlapping region of the first and second gate electrodes and the first and second drain electrodes, and the first and second auxiliary electrodes of the first and second auxiliary electrodes of the gate line and the pixel electrode. A thin film transistor array substrate for a liquid crystal display device, characterized in that an auxiliary capacitor is formed in the overlapping region of the electrode. The method of claim 2, And the sum of the capacitors and the auxiliary capacitors has a constant value. The method of claim 2, The sum of the overlapping region of the first gate electrode and the first drain electrode and the overlapping region of the first auxiliary electrode of the gate line and the first auxiliary electrode of the pixel electrode is equal to that of the second gate electrode and the first drain electrode. And a sum of an overlapping region and an overlapping region of the second auxiliary electrode of the gate line and the second auxiliary electrode of the pixel electrode. 3. The region of claim 2, wherein the first and second drain electrodes forming the capacitor and the first and second auxiliary electrodes of the pixel electrode forming the auxiliary capacitor are irradiated with a laser to perform a welding process. A thin film transistor array substrate for a liquid crystal display device.

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