KR20100040425A - Method for bit line precharging of non volatile memory device - Google Patents

Abstract

A bit line precharge method of a nonvolatile memory device of the present invention includes precharging a sensing node of a page buffer to a high level, and a bit line sensing signal of a first level and a lower level than the first level. And sequentially connecting two levels of the bit line sensing signal to the sensing node and the bit line.

According to the present invention described above, it is possible to shorten the time required to precharge the bit line.

Description

Method for bit line precharging of non volatile memory device

The present invention relates to a bit line precharge method of a nonvolatile memory device.

Recently, there is an increasing demand for a nonvolatile memory device that can be electrically programmed and erased and that does not require a refresh function to rewrite data at regular intervals.

The nonvolatile memory cell is an electric program / eraseable device that performs program and erase operations by changing a threshold voltage of a cell while electrons are moved by a strong electric field applied to a thin oxide film.

A nonvolatile memory device typically includes a memory cell array in which cells in which data is stored is formed in a matrix form, and a page buffer for writing a memory to a specific cell of the memory cell array or reading a memory stored in the specific cell. The page buffer may include a pair of bit lines connected to a specific memory cell, a register for temporarily storing data to be written to the memory cell array, or a register for reading and temporarily storing data of a specific cell from the memory cell array, a voltage of a specific bit line or a specific register. It includes a sensing node for sensing a level, a bit line selection unit for controlling the connection of the specific bit line and the sensing node.

Various operations of precharging the bit line to a high level are performed in various operations of the nonvolatile memory device. For example, the bit line precharge operation may be performed as part of a program operation, a read operation, a verify operation, and the like. Therefore, it is necessary to shorten the time required for such a bit line precharge operation.

SUMMARY An object of the present invention is to provide a bit line precharge method of a nonvolatile memory device capable of shortening the time required for a bitline precharge operation.

The bit line precharge method of the nonvolatile memory device of the present invention for solving the above-mentioned problems is a step of precharging the sensing node of the page buffer to a high level, the bit line sensing signal of the first level and the bit line sensing unit; And sequentially applying a bit line sensing signal having a second level lower than the first level to connect the sensing node and the bit line.

According to the aforementioned problem solving means of the present invention, it is possible to shorten the time required to precharge the bit line. Since the bit line precharge operation is frequently used in various operations of the nonvolatile memory device, the time required for the entire operation can be shortened. In addition, the present invention can be widely applied not only to the nonvolatile memory device described in the present invention but also to precharge the electrically connected wires to a high level.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only these embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like numbers refer to like elements in the figures.

1 is a view showing the overall configuration of a nonvolatile memory device to which the present invention is applied.

The nonvolatile memory device 100 includes a memory cell array 102, a page buffer 108, an X / Y-decoder 104 and 106, a high voltage generator 110, a command interface logic unit 112, and a command register ( 114, an address register / counter 116, a data register 118, and an IO buffer unit 120.

An operation of the nonvolatile memory device will be described.

First, when the chip enable signal / CE is disabled and the write enable signal / WE is toggled with respect to the command interface logic unit 112, the command interface logic unit 112 may respond in response thereto. The command signal received through the IO buffer unit 110 and the command register 114 is received, and a program command, an erase command, or a read command is generated according to the command. In this case, the command signal includes a page program setup code for determining an operation mode of the nonvolatile memory device. Meanwhile, the operation state signal / R / B output from the command interface logic unit 112 is disabled for a predetermined time, and an external memory controller (not shown) transmits the operation state signal / R / B. Receives and recognizes that the nonvolatile memory device is in an operating state such as program / erase / read. That is, during the time when the operation state signal / R / B is disabled, program / erase / read of one page of the memory cell array is executed.

In addition, the address register / counter 116 receives an address signal received through the IO buffer unit 120 and generates a row address signal and a column address signal. The address signal corresponds to one of pages included in one of the memory cells.

The data register 118 temporarily stores various data received through the IO buffer unit 120 and transfers the data to the Y-decoder 106.

The high voltage generator 110 generates bias voltages in response to the program command, erase command or read command and supplies them to the page buffer 108, the X-decoder 104, and the like.

The X-decoder 104 supplies the bias voltages supplied from the high voltage generator 110 to the memory cell array 102 in one of the blocks of the memory cell array in response to the row address signal.

The Y-decoder 106 supplies a data signal to bit lines (not shown) shared by the blocks of the memory cell array through the page buffer in response to the column address signal.

The page buffer 108 latches data signals received through the IO buffer unit 110 and the Y-decoder 106 to share bit lines shared by the blocks of the memory cell array (not shown). Output to

Various operations of precharging the bit line to a high level are performed in various operations of the nonvolatile memory device. For example, the bit line precharge operation may be performed as part of a program operation, a read operation, a verify operation, and the like.

2 is a diagram for describing a bit line precharge operation of a nonvolatile memory device.

For simplicity, only the sensing node precharge unit 210 and the bit line sensing unit 220 are highlighted in the page buffer 108 of FIG. 1.

The sensing node precharge unit 210 applies a high level voltage VDD to the sensing node SO in response to the precharge signal Prechb. To this end, it includes a PMOS transistor (P210) connected between the power supply voltage terminal (VDD) and the sensing node. Accordingly, a high level power supply voltage is applied to the sensing node SO in response to a low level precharge signal.

The bit line sensing unit 220 includes an NMOS transistor N220 connected between the bit line selecting unit 230 and the sensing node SO. The bit line sensing unit 220 connects the bit line selecting unit 230 and the sensing node SO in response to the high level bit line sensing signal PBSENSE, and evaluates the voltage level of a specific bit line to determine the specific level. The voltage level of the data stored in the cell is applied to the sensing node. That is, a read or verify operation is performed according to the voltage level of the bit line sensing signal PBSENSE applied to the gate of the NMOS transistor N220.

Although the detailed configuration of the bit line selector 230 is not shown, the bit line and the sensing node are selected through the bit line sensing unit 170 by selecting any one of the even bit line BLe or the odd bit line BLo. The operation of connecting is apparent to those skilled in the art. In addition, although the detailed configuration of the register 240 is not shown, a latch for temporarily storing externally input data or data read from a memory cell, and the data of the latch is converted according to the level of the sensing node SO. It is apparent to those skilled in the art that the configuration of the sensing node sensing unit is included.

The bit line precharge operation will be described.

For the bit line precharge operation, the sensing node is first pulled up by applying a low level precharge signal to the sensing node precharge unit 210. Thereafter, a high level bit line sensing signal PBSENSE is applied to the bit line sensing unit 220 to connect the bit line and the sensing node to precharge the bit line to a high level.

On the other hand, in the case of the actual bit line, it took a considerable time to precharge the bit line under the influence of parasitic resistance and capacitance. This time causes a time increase in program operation, read operation, verify operation, and the like. Accordingly, in the present invention, the time required for precharging the bit line is reduced by differently applying the bit line sensing signal.

3 is a graph illustrating a method of applying a bit line sensing signal and a result of bit line precharge according to an embodiment of the present invention.

A method of applying the bit line sensing signal PBSENSE is shown at the bottom of the graph. That is, after applying the bit line sensing signal PBSENSE of the first voltage V1 for a predetermined period T1, the bit line sensing signal PBSENSE of the second voltage V2 lower than the first voltage V1 is applied. Is authorized. The level of the second voltage V2 is typically a bit line sensing signal PBSENSE. The first and second voltages are determined by a target voltage to be precharged. In order to precharge the bit line to a 1 V level, at least the second voltage should be equal to or greater than the sum of the threshold voltages of the NMOS transistor N220 included in the bit line sensing unit 220 with the target voltage 1V. .

Therefore, the second voltage V2 is set according to the target voltage to be precharged. In addition, the first voltage V1 is set larger than the second voltage V2, and the size of the first voltage V1 is limited so that the voltage precharged to the bit line reaches only the target voltage.

As shown in the drawing, when only the second voltage V2 is applied in the related art, it takes about 8 ms to reach the voltage of the bit line to 1V.

However, if the second voltage V2 is applied after the first voltage V1 is applied, the bit line is rapidly charged by the first voltage V1, so that the voltage of the bit line is approximately 4.7 kV until the voltage of the bit line reaches 1V. It can be seen that there is a significant time saving.

In this case, when the first voltage V1 is continuously applied or a voltage larger than the first voltage V1 is applied as the bit line sensing signal, the bit line is overcharged. Therefore, the first voltage V1 and the application time of the first voltage V1 may be set to prevent overcharging through experiments.

1 is a view showing the overall configuration of a nonvolatile memory device to which the present invention is applied.

2 is a diagram for describing a bit line precharge operation of a nonvolatile memory device.

3 is a graph illustrating a method of applying a bit line sensing signal and a result of bit line precharge according to an embodiment of the present invention.

Claims (5)

Precharging the sensing node of the page buffer to a high level; And sequentially applying a bit line sensing signal of a first level and a bit line sensing signal of a second level lower than the first level to a bit line sensing unit, thereby connecting the sensing node and the bit line. A bit line precharge method for a nonvolatile memory device. The method of claim 1, wherein precharging the sensing node of the page buffer to a high level includes applying a low level precharge signal to a sensing node precharge unit to apply a power supply voltage to the sensing node. And a bit line precharge method for a nonvolatile memory device. The method of claim 1, wherein the second level is greater than a sum of a voltage level of a target bit line and a threshold voltage of a transistor included in the bit line sensing unit. . The method of claim 1, wherein the value of the first level is set to be precharged to be larger than the second level but lower than a target voltage level. The method of claim 1, wherein the application time of the first level is set to precharge a bit line lower than a target voltage level.

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