KR20100007478A - Method of fabricating semiconductor apparatus and semiconductor apparatus fabricated thereby - Google Patents

Abstract

PURPOSE: A method of fabricating semiconductor apparatus and semiconductor apparatus fabricated thereby are provided to eliminate collision or fault between the contact plug and gate pattern. CONSTITUTION: In the semiconductor substrate(302), the active area and inactive area are classified. In the inactive area, the device isolation film(308) is formed. The oxide film(310) is formed on the semiconductor substrate and device isolation film. Using the etching of the device isolation film and oxide film, one trench is formed. The nitride film(314) is evaporated. The recess(316) is formed in the active area and inactive region. Using the deposition of the conductive substance, the gate electrode is formed. Using the evaporation and patterning of the gate hard mask film, each gate pattern is formed.

Description

TECHNICAL FIELD OF THE INVENTION AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE {METHOD OF FABRICATING SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR APPARATUS FABRICATED THEREBY}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a highly integrated semiconductor device, and more particularly, to a method for manufacturing a unit cell that operates stably in a highly integrated semiconductor memory device.

In general, a semiconductor is one of a class of materials according to electrical conductivity, and is a material belonging to an intermediate region between conductors and non-conductors. In a pure state, a semiconductor is similar to non-conductor, but the electrical conductivity is increased by the addition of impurities or other operations. Such a semiconductor is used to create a semiconductor device such as a transistor by adding impurities and connecting conductors. A device having various functions made using the semiconductor device is called a semiconductor device. A representative example of such a semiconductor device is a semiconductor memory device.

The semiconductor memory device includes a plurality of unit cells composed of a capacitor and a transistor, and a double capacitor is used to temporarily store data, and a transistor is used to control signals (word lines) by using a property of a semiconductor whose electrical conductivity varies depending on the environment. Correspondingly used to transfer data between the bit line and the capacitor. The transistor is composed of three regions: a gate, a source, and a drain, and charge transfer between the source and the drain occurs according to a control signal input to the gate. The transfer of charge between the source and drain occurs through the channel region, which uses the nature of the semiconductor.

When conventional transistors are made in a semiconductor substrate, a gate is formed on the semiconductor substrate and doped with impurities on both sides of the gate to form a source and a drain. As the data storage capacity of the semiconductor memory device increases and the degree of integration increases, the size of each unit cell is required to be made smaller and smaller. That is, the design rules of the capacitors and transistors included in the unit cell have been reduced. As a result, the channel length of the cell transistors has gradually decreased, and thus, short channel effects and drain induced barrier lower (DIBL) effects have been applied to conventional transistors. Occurred, and the reliability of the operation was lowered. Phenomena that occur as the channel length decreases can be overcome by maintaining the threshold voltage so that the cell transistor can perform normal operation. Typically, the shorter the channel of the transistor, the higher the doping concentration of impurities in the region where the channel is formed.

However, as the design rule decreases below 100 nm, increasing the doping concentration in the channel region further increases the electric field at the storage node (SN) junction, which deteriorates the refresh characteristics of the semiconductor memory device. Cause. To overcome this problem, a cell transistor having a three-dimensional channel structure having a long channel length in the vertical direction is used to maintain the channel length of the cell transistor even if the design rule is reduced. That is, even if the channel width in the horizontal direction is short, the doping concentration can be reduced by securing the channel length in the vertical direction, thereby preventing the refresh characteristics from deteriorating. Hereinafter, a structure and a manufacturing process of a transistor including a recess gate used as a cell transistor having a three-dimensional channel structure will be described.

1A to 1E are cross-sectional views for explaining a transistor forming method of a conventional semiconductor memory device.

Referring to FIG. 1A, a pad oxide film 104 is formed on a semiconductor substrate 102, and a pad nitride film 106 is deposited on the pad oxide film 104. At this time, the pad oxide film 104 is formed to a thickness of 50 ~ 150Å, the pad nitride film 106 is deposited to a thickness of about 500 ~ 15001.

Although not shown, a photoresist film (not shown) is applied on the pad nitride film 106 to define the active region and the inactive region, and the photoresist film is patterned using an ISO mask defining the active region. Thereafter, the pad oxide film 104 and the pad nitride film 106 are etched using the patterned photoresist film, and the remaining photoresist film is removed. Subsequently, the exposed semiconductor substrate 102 is etched using the pad oxide film 104 and the pad nitride film 106 as a mask to form a trench. The trench is filled with an insulating insulating film 108 and planarized by performing a chemical mechanical polishing process (CMP) until the pad nitride film 106 is exposed. Typically, these processes are called shallow trench isolation (STI) processes.

The depth of the trench formed in the above-described STI process is formed about 2500 ~ 4000Å. In addition, the isolation insulating layer 108 filling the trench may use a material such as a spin on dielectric (SOD) layer that may be deposited by spin coating, so that the space inside the trench is not empty. In addition, in order to completely fill the trench, it is deposited to about 3000 to 7000 깊은 deeper than the depth of the trench. The chemical mechanical polishing process (CMP) performed after the trench is filled with the insulating insulating film 108 is performed until the thickness of the pad nitride film 106 remains about 40 to 60%.

As shown in FIG. 1C, the pad oxide film 104 and the pad nitride film 106 are planarized to be removed, and then an ion implantation process is performed. At this time, it is necessary to remove the natural oxide film naturally occurring during the process step, to suppress the occurrence of moat, and to control the effective field-oxide height (EFH), in order to effectively control them. It is cleaned using. In the case of removing the pad nitride layer 106, it is preferred to use phosphoric acid (H ₃ PO ₄₎ of the high temperature. The pad oxide film 104 may be removed only by a cleaning operation performed immediately before the ion implantation process without performing a separate removal process. Subsequently, in the ion implantation process, ions are implanted only in a desired region by using a mask corresponding to formation of a well region and a channel region.

Referring to FIG. 1D, first and second recesses 110a and 110b for forming a fin gate or a recess gate are formed in the active region and the insulating insulating layer 108 of the semiconductor substrate 102. However, since the etching selectivity of the semiconductor substrate 102 and the insulating insulating film 108 is not the same, the second recess 110b formed in the insulating insulating film 108 is more than the first recess 110a formed in the active region. It is deep and wide.

Although not shown, a gate oxide layer (not shown) is formed on the structure including the first recess 110a and the second recess 110b. In particular, the size difference between the first recess 110a and the second recess 110b is widened by a cleaning operation performed immediately before the gate oxide film is formed in the recess, and a part of the isolation insulating film 108 is removed. Sometimes. As illustrated in FIG. 1E, a gate pattern including a gate lower electrode and an upper gate electrode is embedded by filling a conductive material (for example, polysilicon) in the first recess 110a and the second recess 110b. When forming 112, a portion of the insulating insulating film 108 is removed between the second recess 110b, which is larger than the first recess 110a, and the second recess 110b during the cleaning operation. Due to the phenomenon, the gate pattern 112 may be tilted. In addition, when the inclination of the gate pattern 112 is severe, a gate bridge phenomenon may occur in which neighboring gate patterns 112 are connected.

FIG. 2 is a scanning electron microscope (SEM) photograph for explaining a disadvantage of a transistor formed as shown in FIGS. 1A to 1E.

In particular, a cross-sectional view enlarged on the right side of FIG. 2 shows that a self-aligned contact (SAC) formed between the gate patterns on the insulating insulating film becomes poor. Explain the phenomenon. This is because, as shown in FIG. 1E, the process margin is reduced as the interval between adjacent first recesses 110b formed in the isolation insulating film 108 is narrowed by a subsequent process. Self-Aligned-Contact (SAC) failure between the gate pattern and the landing contact plug formed between the gate pattern causes a problem of deteriorating operation performance and deteriorating operation reliability of devices in the semiconductor device. .

In order to solve the above-mentioned conventional problems, the present invention provides a semiconductor device capable of preventing a pattern from collapsing in an inactive region of a highly integrated semiconductor device, thereby eliminating collisions or defects between the contact plug and the gate pattern and securing a process margin. It provides a manufacturing method.

The present invention provides a method of defining an active region and an inactive region in a semiconductor substrate, forming a nitride film in a contact plug region in an inactive region, and forming a recess in the active region and the inactive region where a gate electrode is to be formed. It provides a manufacturing method of a semiconductor device comprising.

Preferably, defining an active region and an inactive region in the semiconductor substrate comprises forming a pad oxide film on the semiconductor substrate, forming a pad nitride film on the pad oxide film, using an ISO mask defining the active region. Forming a trench in the inactive region, and forming an isolation layer in the trench.

Preferably, forming a trench in the inactive region using an ISO mask defining the active region comprises applying a photoresist on the pad nitride layer and performing an exposure process using an ISO mask, using a patterned photoresist Etching the pad nitride layer and the pad oxide layer, and etching the semiconductor substrate exposed between the pad nitride layer.

Preferably, forming a nitride film in the contact plug region in the non-active region includes forming an oxide layer on the active region and the non-active region, and etching the oxide layer and the device isolation layer on the contact plug region to form a trench. And embedding a nitride film in the trench.

Preferably, forming the trench by etching the oxide layer and the device isolation layer in the contact plug region comprises applying a photoresist layer on the oxide layer and patterning the same using a mask defining the contact plug region, using a patterned photoresist layer. Etching the oxide film, and etching the device isolation layer in the inactive region to a predetermined depth by using the etched oxide film.

Preferably, the contact region is a bit line contact plug region.

Preferably, embedding the nitride film in the trench includes depositing a nitride film over the structure including the trench, and planarizing the nitride film until the oxide film is exposed.

Preferably, forming the recess in which the gate electrode is to be formed in the active region and the inactive region comprises applying a photoresist on the structure including the nitride layer and patterning the same using a mask defining the recess. And etching the region exposed by the patterned photoresist.

Preferably, the recess formed in the inactive region is formed on both sides of the nitride film.

According to an exemplary embodiment of the present invention, the gate pattern may not be tilted while the size of the recess formed in the active region and the other region is changed due to a subsequent process performed after the formation of the recess gate or the fin gate formation recess. There is an advantage.

In addition, according to the present invention, the recesses formed on the active region and the other regions are different from each other, so that the distance between neighboring gate patterns formed on the recesses is different, thereby colliding with the gate pattern when the contact plug is formed and contact failure. This can be prevented from occurring.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

The method of manufacturing a semiconductor device according to the present invention can be applied to a cell transistor constituting a unit cell in a semiconductor memory device. In particular, a recess gate is applied to prevent short channel effects while reducing the size of the cell transistor due to high integration. Alternatively, a method of forming a transistor including a pin gate will be described as an example.

3A to 3E are cross-sectional views and plan views illustrating a method of forming a transistor in a semiconductor device according to an embodiment of the present invention. In particular, the transistor formation method illustrated in FIGS. 3A to 3E eliminates a defect in the gate pattern and the self-aligned contact (SAC) of the contact plug caused by a portion of the recess gate or the fin gate formed outside the active region. This is to prevent it.

Referring to FIG. 3A, an isolation region 308 is formed in an inactive region by separating an active region and an inactive region from a semiconductor substrate 302. Although not shown, the trench is deposited by sequentially depositing a pad oxide layer (not shown) and a pad nitride layer (not shown) on the semiconductor substrate 302, and then etching the inactive region corresponding regions using an ISO mask defining an active region. The device isolation layer 308 is formed in the trench. This process is commonly referred to as the STI process. A chemical mechanical polishing process (CMP) is performed to remove all of the pad oxide film and the pad nitride film remaining after the device isolation film 308 is formed.

Here, in order to form the above-mentioned trench, a photoresist (not shown) is coated on the semiconductor substrate 302, an exposure process using an ISO mask is performed, and then the pad nitride film and the pad oxide film are etched using the patterned photoresist, Subsequently, a method of etching the semiconductor substrate 302 exposed between the pad nitride layers is used.

Referring to (i) of FIG. 3B, an oxide layer 310 is formed on a semiconductor substrate 302 and an isolation layer 308 on which active and inactive regions are defined, and an oxide layer 310 and an isolation layer are formed on a plug region. 308 is etched to form first trenches 312. Although not shown, in order to form the first trenches 312, a photoresist film (not shown) is applied on the oxide film 310 and patterned using a mask defining a contact region, and then the oxide film 310 is formed using the patterned photoresist film. ) Is etched, and the device isolation layer 308 in the inactive region exposed by the etched oxide layer 310 is etched to a predetermined depth. As shown in (ii) of FIG. 3B, a mask used in this process may use a bit line contact mask, and it is preferable to etch the bit line contact region on the device isolation layer 308. .

In the following, FIGS. 3C to 3E (i) will be described in part based on the I-I 'axis shown in FIG. 3B (ii), and FIG. 3E (ii) will be II- shown in FIG. 3B (ii). Some are shown with respect to the II 'axis.

Referring to FIG. 3C, a nitride film 314 is deposited on the structure including the trench 312. Thereafter, as illustrated in FIG. 3D, the chemical mechanical polishing process (CMP) is performed until the oxide film 310 is exposed to planarize the nitride film 314. Through this process, the nitride film 314 is buried in the trench 312.

In the above-described process, it is not necessary to etch the lower portion of the device isolation film 308 when etching the device isolation film 308, and the nitride film 314 forms a recess around the device isolation film 308 so that it is excessively excessive. The device isolation layer 308 is formed to have a predetermined thickness to prevent the device isolation layer 308 from collapsing due to etching or recess.

Referring to FIG. 3E (i), a recess 316 is formed in both the active region and the inactive region on the semiconductor substrate 302. Specifically, after the photoresist is applied onto the nitride film 314 and the oxide film 310 and patterned using a mask defining the recess 316, the region exposed by the patterned photoresist is etched to recess ( 316). In particular, since the nitride film 314 is positioned between the recesses 316 formed on the device isolation film 308 which is an inactive region, even if the device isolation film 308 is additionally etched in a cleaning process or the like, a region between the recesses 316 may be formed. The nitride film 314 may be prevented from being collapsed or excessively etched.

For reference, referring to FIG. 3E (ii) showing a cross section in a direction orthogonal to (i) of FIG. 3E, the nitride film 314 may have a bit line contact shown in FIG. 3E (i). , BLC) regions, but not in the storage node contact (SNC) region shown in (ii) of FIG. 3E.

Although not shown, after the formation of the recesses 316, a gate electrode is formed by depositing polysilicon, tungsten, or the like, which is a conductive material, and then a gate hard mask film is deposited and then patterned to form gate patterns located in each recess 316. Complete

As described above, in the subsequent process of forming a fin gate or a recess gate after the recess 316 is formed by forming a nitride film after etching the portion where the bit line contact is to be formed in the region of the device isolation layer 308. It is possible to prevent the size (critical dimension, CD) of the recess 316 formed in the device isolation layer 308 from being wet etched and cleaned. Therefore, the gate pattern may be tilted or the distance between the gate patterns may be kept constant, so that the landing contact plug may be prevented from colliding with the gate pattern in the subsequent process, and the SAC defect may be prevented from occurring. . As a result, process margins may be increased in the manufacturing process of the semiconductor device, and reliability of the device in the semiconductor device may be increased.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

1A to 1E are cross-sectional views for explaining a transistor forming method of a conventional semiconductor memory device.

FIG. 2 is a SAM photograph for explaining a disadvantage of a transistor formed as shown in FIGS. 1A to 1E.

3A to 3E are cross-sectional views and plan views illustrating a method of forming a transistor in a semiconductor device according to an embodiment of the present invention.

Claims (9)

Defining an active region and an inactive region in the semiconductor substrate; Forming a nitride film in the contact plug region in the inactive region; And Forming a recess in which a gate electrode is to be formed in the active region and the inactive region. The method of claim 1, Defining an active region and an inactive region in the semiconductor substrate Forming a pad oxide film on the semiconductor substrate; Forming a pad nitride film on the pad oxide film; Forming a trench in the inactive area using an ISO mask defining the active area; And Forming a device isolation film in the trench. The method of claim 2, Forming a trench in the inactive region using an ISO mask defining the active region Applying a photoresist film on the pad nitride film and performing an exposure process using an ISO mask; Etching the pad nitride layer and the pad oxide layer using a patterned photoresist; And Etching the semiconductor substrate exposed between the pad nitride layers. The method of claim 1, Forming a nitride film in the contact plug region in the inactive region is Forming an oxide film on the active region and the inactive region; Forming a trench by etching the oxide layer and the device isolation layer in the contact plug region; And And embedding a nitride film in the trench. The method of claim 4, wherein Etching the oxide layer and the isolation layer in the contact plug region to form a trench Applying a photoresist film on the oxide film and patterning it using a mask defining the contact plug region; Etching the oxide film using the patterned photoresist; And And etching the device isolation film in the inactive region to a predetermined depth by using the etched oxide film. The method of claim 5, And said contact plug region is a bit line contact plug region. The method of claim 4, wherein Embedding a nitride film in the trench Depositing a nitride film over the structure including the trench; And Planarizing the nitride film until the oxide film is exposed. The method of claim 1, Forming recesses in which the gate electrode is to be formed in the active region and the inactive region, Applying a photoresist on top of the structure including the nitride and patterning using a mask defining the recess; And Etching the region exposed by the patterned photoresist. The method of claim 8, The recess formed in the inactive region is formed on both sides of the nitride film.

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