KR20090080397A - Manufacturing method of semiconductor device - Google Patents

Abstract

The present invention relates to a method for manufacturing a semiconductor device, and discloses a technology capable of preventing a threshold voltage variation of a transistor according to a position of an active region by removing ions accumulated on the surface of an active region on the upper side of the well, and then forming the active region again. do. To this end, the present invention provides a method of forming a device isolation trench by selectively etching a semiconductor substrate, forming an insulating film over the semiconductor substrate including the device isolation trench, and etching the insulating film to form a semiconductor substrate in an NMOS region. Exposing and forming a first well in the exposed semiconductor substrate; etching the insulating film to expose the semiconductor substrate in the PMOS region; forming a second well in the exposed semiconductor substrate; Removing ions collected on the exposed surface of the semiconductor substrate during the formation of the first and second wells; forming a silicon layer on the semiconductor substrate; and forming a device isolation layer by planarizing the silicon layer and the insulating layer.

Description

Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. In particular, a semiconductor device capable of preventing the variation of the threshold voltage of a transistor according to the position of an active region by removing the ions accumulated on the surface of the active region above the well, and then forming the active region again. It is a technique relating to the manufacturing method of.

1A to 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

Referring to FIG. 1A, a device isolation film 14 defining an active region 12 is formed in a semiconductor substrate 10 by performing a conventional shallow trench isolation (STI) process.

Next, a first photosensitive film pattern 16 is formed on the semiconductor substrate 10 to expose a region where the NMOS transistor is to be formed.

Next, an N-type impurity is implanted into the semiconductor substrate 10 using the first photosensitive film pattern 16 as an ion implantation mask to form the P-type well 18 in the semiconductor substrate 10. Next, the first photosensitive film pattern 16 is removed.

Here, in the process of forming the P-type well 18, ions are implanted by maintaining a predetermined tilt angle for the channel region. In this case, a shadowing phenomenon in which ions are implanted through the first photoresist pattern 16 may occur due to an ion implantation angle and a step between the semiconductor substrate 10 and the first photoresist pattern 16, or the first photoresist In the pattern 16, a phenomenon in which ions are scattered occurs. As a result, ions 18a are accumulated on the surface of the active region 12 above the P-type well 18.

Referring to FIG. 1B, a second photoresist pattern 20 exposing a region where a PMOS transistor is to be formed is formed on the semiconductor substrate 10.

Next, the P-type impurity is implanted into the semiconductor substrate 10 using the second photosensitive film pattern 20 as an ion implantation mask to form the N-type well 22 in the semiconductor substrate 10. Next, the second photosensitive film pattern 20 is removed.

Here, the N-type well 22 formation process is performed by the gradient ion implantation method similarly to the P-type well 18 formation process. Accordingly, ions 22a are also accumulated on the surface of the active region 12 above the N-type well 22.

As described above, in the method of manufacturing a semiconductor device according to the prior art, ions are accumulated on the surface of an active region by shadowing or scattering during the P-type and N-type well forming processes.

However, a folded semiconductor device, particularly a PMOS transistor and an NMOS transistor, which constitute a latched bit line sense amplifier, is a mismatch of a threshold voltage or an operating current depending on an active region, that is, a distance between a channel region and a well. Is likely to occur.

Therefore, the distance between the photoresist pattern for forming the well and the active region should be spaced a predetermined distance or more so as not to generate ions accumulated on the surface of the active region. In this case, there is a problem in that the size of the device isolation layer is increased and the overall chip size is increased.

SUMMARY OF THE INVENTION An object of the present invention is to prevent the variation of the threshold voltage of a transistor according to the position of an active region by removing the ions accumulated on the surface of the active region on the upper side of the well and then forming the active region again.

Method of manufacturing a semiconductor device according to the present invention comprises the steps of selectively etching the semiconductor substrate to form a device isolation trench; Forming an insulating film on the semiconductor substrate including the device isolation trench; Etching the insulating film to expose the semiconductor substrate in an NMOS region, and forming a first well in the exposed semiconductor substrate; Etching the insulating film to expose the semiconductor substrate in the PMOS region, and forming a second well in the exposed semiconductor substrate; Etching the semiconductor substrate over the entire surface to remove ions collected on the surface of the semiconductor substrate exposed when the first and second wells are formed; Forming a silicon layer on the semiconductor substrate; And planarizing the silicon layer and the insulating layer to form an isolation layer.

The forming of the isolation trench may include forming a pad oxide layer and a pad insulating layer on the semiconductor substrate; Etching the pad insulating film and the pad oxide film by a photolithography process using a device isolation mask to form a pad insulating film pattern and a pad oxide film pattern; And etching the semiconductor substrate using the pad insulating layer pattern and the pad oxide layer pattern as a mask.

The first well may be formed in a P type, the second well may be formed in an N type, the silicon layer may be formed by a selective epitaxial growth method, and the planarization process may include the pad insulating layer pattern and the pad. It is characterized in that it is performed until the oxide film pattern is removed.

The present invention provides an effect of preventing the threshold voltage variation of the transistor according to the position of the active region by removing the ions accumulated on the surface of the active region on the upper side of the well, and then forming the active region again.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

2A to 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

Referring to FIG. 2A, a pad oxide layer (not shown) and a pad nitride layer (not shown) are formed on the semiconductor substrate 100 in the sense amplifier region.

Next, the pad oxide film and the pad nitride film are etched by a photolithography process using an isolation mask to form the pad oxide film pattern 102 and the pad nitride film pattern 104.

Next, the semiconductor substrate 100 is etched to a predetermined depth using the pad oxide film pattern 102 and the pad nitride film pattern 104 as an etch mask to form a device isolation trench (not shown).

Next, an insulating film 106 is formed on the semiconductor substrate 100 on which the device isolation trench is formed.

Referring to FIG. 2B, a first photoresist layer pattern 108 is formed on the insulating layer 106 to expose the NMOS region.

Next, the semiconductor substrate 100 is exposed by etching the insulating layer 106, the pad nitride layer pattern 104, and the pad oxide layer pattern 102 using the first photoresist layer pattern 108 as an etching mask.

Next, an impurity ion implantation process is performed on the first photoresist layer pattern 108 using an ion implantation mask to form the P-type well 110 in the semiconductor substrate 100.

Here, the impurity ion implantation process uses an N-type impurity such as boron (B), and is preferably performed by a gradient ion implantation method.

At this time, ions 110a are accumulated on the surface of the semiconductor substrate 100 above the P-type well 110 by the shadowing phenomenon and the scattering phenomenon.

Next, the first photoresist pattern 108 is removed.

Referring to FIG. 2C, a second photoresist pattern 112 is formed on the entire surface to expose the PMOS region.

Next, the semiconductor substrate 100 is exposed by etching the insulating layer 106, the pad nitride layer pattern 104, and the pad oxide layer pattern 102 using the second photoresist layer pattern 112 as an etching mask.

Next, an impurity ion implantation process is performed on the second photoresist layer pattern 112 using an ion implantation mask to form an N-type well 114 in the semiconductor substrate 100.

Here, the impurity ion implantation process uses a P-type impurity such as phosphorus (P) or arsenic (As), and is preferably performed by a gradient ion implantation method.

At this time, the ions 114a are accumulated on the surface of the semiconductor substrate 100 above the N-type well 114 by the shadowing phenomenon and the scattering phenomenon.

Next, the second photosensitive film pattern 112 is removed.

Referring to FIG. 2D, the exposed semiconductor substrate 100 is etched to remove the ions 110a and 114b accumulated on the surface of the semiconductor substrate 100.

Referring to FIG. 2E, the silicon layer 116 is formed over the entire surface.

Here, the silicon layer 116 forming process is preferably performed by the selective epitaxial growth (SEG) method using the exposed semiconductor substrate 100 as a seed layer.

Referring to FIG. 2F, the pad nitride layer pattern 104 and the pad oxide layer pattern 102 are removed by performing a planarization process on the silicon layer 116. Accordingly, the device isolation layer 120 defining the active region 118 is completed.

That is, according to the present invention, after removing the ions 110a and 114b accumulated on the surface of the semiconductor substrate 100, the silicon layer 116 is grown to form the active region 118, thereby changing the threshold voltage Vt of the NMOS and PMOS transistors. Can be prevented.

1A to 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

2A to 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Claims (5)

Selectively etching the semiconductor substrate to form a device isolation trench; Forming an insulating film on the semiconductor substrate including the device isolation trench; Etching the insulating film to expose the semiconductor substrate in an NMOS region, and forming a first well in the exposed semiconductor substrate; Etching the insulating film to expose the semiconductor substrate in the PMOS region, and forming a second well in the exposed semiconductor substrate; Etching the semiconductor substrate over the entire surface to remove ions collected on the surface of the semiconductor substrate exposed when the first and second wells are formed; Forming a silicon layer on the semiconductor substrate; And Planarizing the silicon layer and the insulating layer to form an isolation layer Method of manufacturing a semiconductor device comprising a. The method of claim 1, wherein the forming trench for device isolation Forming a pad oxide film and a pad insulating film on the semiconductor substrate; Etching the pad insulating film and the pad oxide film by a photolithography process using a device isolation mask to form a pad insulating film pattern and a pad oxide film pattern; And Etching the semiconductor substrate using the pad insulating layer pattern and the pad oxide layer pattern as a mask Method of manufacturing a semiconductor device comprising a. The method of claim 2, wherein the first well is formed in a P-type, and the second well is formed in an N-type. The method of claim 2, wherein the silicon layer is formed by a selective epitaxial growth method. The method of claim 2, wherein the planarization process is performed until the pad insulating film pattern and the pad oxide film pattern are removed.

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