KR20090043740A - CMOS image sensor - Google Patents

Abstract

In the CMOS image sensor according to the present invention, a plurality of sensor units including a light receiving unit CMOS and an output unit CMOS are disposed in a unit pixel, and thus, an electric signal can be output according to the amount of light received, thereby allowing a separate operation to a user. A wide range of illuminance can be coped without requiring.

Image sensor, CMOS, NMOS, PMOS, subject, unit pixel

Description

CMOS image sensor

TECHNICAL FIELD The present invention relates to a CMOS image sensor, and more particularly, to a CMOS image sensor that exhibits a constant digital output regardless of the amount of light received, that is, provides a dynamic range from low to high illumination. .

An image sensor is a device that captures an image instantaneously by using a property of a semiconductor device that responds to light energy. Light generated from each subject existing in the natural world has a unique value in wavelength and the like. The pixel of the image sensor detects light generated from each subject and converts it into an electric value.

That is, the pixel of the image sensor generates an electrical value corresponding to the wavelength of light in response to the magnitude of light energy generated in the subject.

Among these, a charge coupled device (CCD) is a device in which charge carriers are stored and transported in a capacitor while individual MOS capacitors are located in close proximity to each other. A sensor is a device that employs a switching method of forming a pixel array using a CMOS integrated circuit manufacturing technology and sequentially detecting the output. The CMOS image sensor has the great advantage of low power consumption, making it very useful for personal portable systems such as mobile phones.

FIG. 1A is a diagram illustrating a conventional three-transistor CMOS active pixel, a cross-sectional view of a photo-diode including a circuit of peripheral components, and FIG. 1B is a conventional three-transistor seed of FIG. 1A. It is an equivalent circuit diagram of MOS active pixel.

1A and 1B, in a conventional three-transistor CMOS active pixel, an N + type impurity layer 11 and an N + type floating diffusion layer 13 constituting one junction of a photodiode are in contact with each other. Therefore, the capacitance component of the photodiode is substantially the sum of the capacitor components produced by the N + type impurity layer 11 and the N + type floating diffusion layer 13.

Accordingly, an image sensor employing a conventional three-transistor CMOS active pixel has a disadvantage of low sensitivity. The four-transistor CMOS active pixel is to compensate for the disadvantage of the three-transistor CMOS active pixel.

FIG. 2A is a diagram illustrating a conventional 4-transistor CMOS active pixel, showing a cross section of a photodiode including a circuit of peripheral components, and FIG. 2B is an equivalent of the conventional 4-transistor CMOS active pixel of FIG. 2A. It is a circuit diagram.

2A and 2B, the conventional 4-transistor CMOS active pixel includes a transfer transistor 25 controlled by a transmission control signal Tx to remove noise generated in the 3-transistor CMOS active pixel. Used. The N + type impurity layer 21 and the N + type floating diffusion layer 23 constituting one junction of the photodiode are separated from each other.

Therefore, in the conventional 4-transistor CMOS active pixel, the sensitivity of the image sensor may be increased and the image quality may be improved. However, the four-transistor CMOS active pixel has a disadvantage in that the light receiving area is reduced due to the addition of the transfer transistor.

FIG. 3A is a circuit diagram connected to a pixel portion formed of a combination of unit pixels shown in FIGS. 1A and 2A. The pixel unit 30 refers to one column of unit pixels. The pixel portion 30 is provided by the number of columns, and the number of unit pixels included in each pixel portion 30 is provided by the number of rows.

Generally, '640 × 480 VGA', '1024 × 768 XGA, 1280 × 1024 SXGA' means '640 columns × 480 rows', '1024 columns × 768 rows', '1280 columns × 1024', respectively. This means that the image resolution consists of 'rows'. In practice, the number of columns and rows is somewhat higher. 3B illustrates a signal applied to the unit pixel illustrated in FIGS. 1A and 2A.

The processing on the circuit and signal shown in FIGS. 3A and 3B is as follows. When a select signal is applied to a row including a plurality of unit pixels, an image data signal captured during a row enable period (R_en, row enable) in the plurality of unit pixels is captured from the common contact 31 of the column by the CDS (Correlated). Double Sampling) 36 is applied. The image data signal includes data signals corresponding to various levels of illuminance according to the surrounding environment, from a high illuminance signal that is a bright light data signal to a low illuminance signal that is a dark light data signal.

The data signal according to the various levels of illumination lowers the reference voltage applied to the circuit including the CDS 36 at each level. That is, the low light data signal lowers the reference voltage relatively less, while the high light data signal drops the reference voltage relatively much.

3C illustrates a voltage drop phenomenon of the data signal according to each illuminance level. Although three levels are illustrated in FIG. 3C for convenience of description, various levels of data signals may exist.

In the 'A' section and the 'C' section of FIG. 3C, a stable section without fluctuation of the signal voltage and a 'B' section are sections in which the drop of the signal voltage occurs. First, while the low enable signal R_en is disabled, the reset sampling drive signal SR is applied to the switch b 32b of the CDS 36 during the reset sampling period A to apply the reset voltage to the capacitor b 33b. Save it.

Thereafter, when the row enable signal R_en of the signal of FIG. 3B is applied to each unit pixel of the row, and the image data signal is applied to the common contact 31 of the column, the switch a 32a of the CDS 36 is external. Data sampling (SD, data sampling) is performed during the 'C' period by the data sampling driving signal applied from the multiplier 35 to store the value in the capacitor a 33a and through the buffer a 34a. Apply a data signal voltage.

After completion of the data sampling (SD), a reset (RST) signal is applied, and when low enable is completed, a reset is applied externally by a switch b32b of the CDS 36 for processing the next image processing data. Reset sampling (SR) is performed during the 'A' period by the sampling driving signal to store the reset voltage in the capacitor b 33b, and apply a signal to the MUX 35 via the buffer b 34b.

When the series of signals R_en, SD, RST, and SR progress for one period, image data stored in the unit pixel is acquired, and a differential amplifier (SHA: Sample and Hold Amplifier) (37) and a programmable gain amplifier (PGA) are used. (38) and the analog-digital converter (ADC) 39 output image data.

As a result, the conventional three-transistor CMOS active pixel has a disadvantage of low sensitivity, and the conventional four-transistor CMOS active pixel has a problem in that a light receiving area is small.

The solution to solve this problem will be described below, and the solution to solve the photocurrent saturation problem due to high sensitivity at high illumination in the solution solution will be described.

An object of the present invention is to provide a CMOS image sensor, which is created to improve the above problems and which can reduce the area of an image sensor by reducing a pitch size.

Another object of the present invention is to provide a CMOS image sensor capable of improving yield and reducing production costs in a process. Still another object of the present invention is to provide a CMOS image sensor capable of preventing the saturation of the photocurrent at high illumination.

In order to achieve the above object, the CMOS image sensor includes a sensor unit including a light receiving unit CMOS for receiving light and generating an electrical signal, and an output unit CMOS for outputting a signal received from the light receiving unit CMOS. The sensor unit may be disposed in a plurality of unit pixels.

Here, it is preferable to further include a plurality of current-voltage converter to correspond to the sensor unit in the unit pixel.

In addition, it is preferable that the light receiving unit CMOS provided in each sensor unit has a different length and width ratio (W / L ratio). In addition, the light measuring unit for measuring the amount of light received; The display unit may further include a selection unit that selects a sensor unit indicating an output satisfying a preset value according to the amount of received light among the plurality of sensor units according to the measurement result of the light measuring unit. Here, it is preferable that the first sensor unit is selected when the amount of light input is low, and the second sensor unit is selected when the amount of high light is input.

Each of the light receiving unit CMOS in the plurality of sensor units preferably has a structure in which a power supply terminal to which a power supply VDD is connected is shared.

Preferably, two sensor units are disposed in a unit pixel. In this case, the light receiving unit CMOSs provided in the two sensor units have different length and width ratios (W / L ratios) so that different current values are output for the same amount of light. It is desirable to have.

In addition, it is preferable that the light receiver CMOS is one PMOS, and the output CMOS is one NMOS. Here, the PMOS includes a well doped with an N-type on a P-type semiconductor substrate and receives light into a region of a gate and an N-well, and the NMOS receives a signal received from the PMOS on a P-type semiconductor substrate. It is preferable that it is a structure to output. In addition, it is preferable that a source and a drain are formed in the well of the PMOS, and the gate of the PMOS is floated.

In addition, the gate of the NMOS preferably receives a selection signal from the outside.

Preferably, the connection part further comprises a connection part formed in a part of the well to connect the gate of the PMOS to the well, and the connection part is preferably formed by doping with the same impurity type as the well, and the doping concentration of the connection part. Is preferably higher concentration than the doping concentration of the well.

In addition, it is preferable that a metal contact is formed on the connection part to connect the connection part and the gate of the PMOS.

As described above, in the CMOS image sensor according to the present invention, a plurality of sensor units including the light receiving unit CMOS and the output unit CMOS may be arranged in a unit pixel, and thus, the electrical signal may be output according to the amount of light received.

By selecting and using the output of the sensor unit according to the amount of light received through this, it is possible to continuously obtain an image corresponding to the photocurrent saturation caused by a very large illumination change.

In addition, instead of using a photodiode in the sensor unit, by forming an NMOS and a PMOS that can be manufactured by a general standard process, the area of the CMOS image sensor can be reduced.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is an equivalent circuit diagram conceptually showing the structure of the CMOS image sensor of the present invention. In a conventional photodiode type active pixel structure, the light receiving area of a photodiode as a light receiving portion is reduced due to CMOS such as Rx, Sx, and Tx. It is a circuit diagram proposed to solve the low characteristic. Referring to FIG. 4, in the CMOS image sensor of the present invention, the unit pixel including the light receiver 40 and the selection MOS 41 has a passive pixel structure, so that the size of the unit pixel can be relatively reduced compared to the prior art. In addition, since the signal is output as a voltage through the current-voltage converter 42, the advantage of using the signal processing method from the analog circuit (CDS 43) of the conventional CMOS image sensor to the ADC 47 as it is. have.

The CMOS pixel array captures an external subject image and divides the image of the subject in individual unit pixels evenly by the number of unit pixels to generate electrical signals corresponding to different brightnesses. In each unit pixel, the charge corresponding to the amount of light absorbed is present in the P-N heterojunction that joins the N-well of the PMOS and the P-type corresponding to the source and drain of the PMOS 40 and the N-type of the N-well, respectively. Electron hole pairs (EHPs) of the depletion layer are separated according to the amount of light and are generated as charge carriers to generate electrical current, and selectively move through the NMOS 41 connected to the PMOS to serve as a switch. .

Therefore, the large photocurrent generated from the PMOS used as the light receiving element is transferred to the current mirror without charge accumulation. In the current mirror 42, the current is amplified, the amplified current is algebraically converted, and the converted voltage is read using a circuit implemented by the CDS 43, the MUX 44, and the SHA 45. The image data is output through the PGA 46 and the ADC 47. Applying this to the pixels of the image sensor can significantly reduce the charge accumulation time.

FIG. 5 is a configuration diagram of the CMOS image sensor of FIG. 4, wherein the unit pixel is formed only by a MOS process of a general semiconductor in fabricating a unit pixel of the CMOS image sensor. The light receiving portion of the unit pixel structure is composed of a PMOS using a photoelectric conversion method by light incidence, and a unit pixel having a 2-transistor structure of 1PMOS and 1NMOS including an NMOS connected to the PMOS and serving as a switch. To form a structure.

That is, by implementing one conventional photodiode and a three-transistor or one photodiode and a four-transistor unit pixel in a two-transistor structure, the pitch size of the unit pixel is reduced, and the control such as the conventional reset ( Since there is no control signal, metal lines are reduced in the layout of the pixel, thereby simplifying the structure of the unit pixel.

The unit pixel forming method is as follows.

In order to implement PMOS and NMOS on the P-type semiconductor substrate 200, an N-well (well) 220 is formed in the PMOS region. In the process of forming the Nwell 220, an ion implantation process is performed on N-type impurities in a state in which a pattern is formed on the P-type semiconductor substrate 200 and only the region where the N-well 220 is to be opened is opened. Then, heat treatment to form the N-well 220. A gate oxide layer 260 and polysilicon are sequentially deposited on the entire surface of the substrate on which the N-well 220 is formed, patterned, and then etched to form a floating gate 240 in the PMOS and a select gate 250 in the NMOS. .

Subsequently, a mask in which only the source / drain formation region of the PMOS region is opened is formed, a high concentration P-type implantation process is performed to form the source / drain 230 in the PMOS region, and the source / drain of the NMOS region is sequentially A mask in which only the formation region is opened is formed, and a source / drain 270 is formed in the NMOS region by performing a high concentration N-type ion implantation process. In addition, a salicide process may be additionally performed to reduce the resistance in regions where the source / drain of PMOS and NMOS is formed. However, since the PMOS is an optical device that receives light, light must pass through the floating gate formed on the upper side of the PMOS. Therefore, it is essential not to perform the salicide process on the floating gate.

Referring to the driving principle of the CMOS image sensor of FIG.

When a voltage is applied to the source of the PMOS formed on the same substrate as the NMOS, the N-well of the PMOS forms a depletion region in an electrically neutral state. Subsequently, when a photon is incident on an N-well, which is a depletion region, by receiving light through a PMOS, which is a light receiving unit, an electron hole pair (EHP) is separated, thereby forming a P channel on a gate bottom of the PMOS device. A voltage is applied to the select gate formed in the NMOS connected to the PMOS, and an N channel is formed between the source and the drain formed in the NMOS to receive the signal charge formed in the PMOS and emit an output signal.

Referring to the graph of FIG. 6, in the conventional photodiode, the current flows when the light intensity is greater than or equal to a critical point, and the current tends to increase as the light intensity increases linearly. As the sensor pixel has a structure in which current flows immediately upon receiving light, there is no dark current, and as shown in area A of FIG. 6, the slope of the current change with respect to a small amount of light is very sharp. The slope of the current change with respect to the light change is relatively gentle.

Therefore, since there is no control signal as in the conventional reset, since the metal line is reduced in the layout of the pixel, the pitch size may be reduced compared to the conventional unit pixel, and in the case of the conventional CMOS image sensor, one photon While generating one electron-hole pair, the PMOS light-receiving device generates a photo current in which one photon is amplified, so that the current gain of the photocurrent reaches 100 to 1000, thereby realizing an image even in low light with a small amount of light incident. Since the charge accumulation time can be reduced by 100 ~ 1000 times compared with the conventional sensor, the charge accumulation time is enough for tens of clock delays instead of one frame or one line, so that integration time is unnecessary and high speed video is realized. To make it possible.

In addition, since the CMOS image sensor described above implements unit pixels in a general MOS process, a dedicated process of the existing CMOS image sensor is unnecessary. Since the present invention receives light from the PMOS without integration time and outputs it through the NMOS, it is possible to minimize the dark current of the sensor due to the long integration except the dark current caused by the leakage current of the switching NMOS.

Therefore, a process of forming an epitaxial layer on the surface of the light receiving unit is unnecessary to prevent dark current during the formation process of the conventional CMOS image sensor, and the PMOS light receiving device of the present invention generates a photocurrent in which one photon is amplified. In order to collect the light into the light-receiving portion of the unit pixel, a micro lens forming process is not necessary on the unit pixel. All of these processes can be omitted, thus reducing production costs.

FIG. 7 is a configuration diagram of a CMOS image sensor in which a gate of a PMOS is connected to an N-well of a PMOS. In manufacturing a unit pixel, a unit pixel is formed only by a MOS process of a general semiconductor. The light-receiving portion of the unit pixel structure is a two-transistor structure of 1 PMOS and 1 NMOS including a PMOS using a photoelectric conversion method by light incident and an NMOS connected to the PMOS and serving as a switch, and the gate of the PMOS And N-well form unit pixels.

Therefore, the CMOS image sensor has a conventional unit pixel having one photodiode and three-transistor or one photodiode and four-transistor structure in a two-transistor structure, thereby reducing the pitch size of the unit pixel. Since there is no control signal such as a reset of, the structure of the unit pixel can be simplified because the metal line is reduced in the layout of the pixel.

The unit pixel forming method of the CMOS image sensor of FIG. 7 is as follows.

In order to implement PMOS and NMOS on the P-type semiconductor substrate 200, an N-well 220 is formed in the PMOS region. In the formation process of the N-well, an ion implantation process is performed on an N-type impurity in a state in which a pattern is formed on a P-type semiconductor substrate and only the region where the N-well is to be formed is opened. Form. The gate oxide layer 260 and the polysilicon are sequentially deposited on the entire surface of the N-well, and are patterned and then etched to form a floating gate 240 in the PMOS and a select gate 250 in the NMOS.

Subsequently, a mask in which only the source / drain formation region of the PMOS region is opened is formed, a high concentration P-type implantation process is performed to form the source / drain 230 in the PMOS region, and the source / drain of the NMOS region is sequentially A mask in which only the formation region is opened is formed, and a source / drain 270 is formed in the NMOS region by performing a high concentration N-type ion implantation process.

In order to connect the gate 240 formed in the PMOS and the N-well 220, a connection portion 210 is formed on the surface of the N-well. The connection portion 210 of the Nwell injects N-type ions to a concentration higher than the formation concentration of the N-well, and forms a metal contact 280 in a region where the high concentration of N-type ions are implanted to electrically connect the PMOS and the N-well. Connect.

At this time, the CMOS image sensor of FIG. 7 is also an optical device that receives light, and since light passes through a gate formed on the PMOS, the gate of the PMOS does not perform a salicide process.

Referring to the driving principle according to the unit pixel of the CMOS image sensor of FIG.

When a voltage is applied to the source of the PMOS formed on the same substrate as the NMOS, the N-well of the PMOS forms a depletion region in an electrically neutral state. At this time, when the light is received by the light-receiving part of the PMOS, photons are incident on the N-well, which is a depletion region, and the electron hole pair (EHP) is separated. P serves as a substrate bias to lower the minimum voltage required to form the channel, thereby easily forming the P channel. In addition, a voltage is sequentially applied to the select gate 250 formed in the NMOS connected to the PMOS, and an N channel is formed between the source and the drain formed in the NMOS to receive the signal charge formed in the PMOS to emit an output signal.

Referring to the graph of FIG. 6, in the conventional photodiode, the current flows when the light intensity is greater than or equal to a critical point, and the current tends to increase as the light intensity increases linearly. When a turn on voltage is applied to the gate 250 of the NMOS, electrons remaining in the N-well connected to the PMOS gate 240 act as a bias to the N-type well substrate and the PMOS gate. As a result, V _th (threshold voltage: minimum voltage required to form a channel) is lowered, and the current has characteristics as shown in the graph of FIG. 6 according to light intensity. As shown in area A of FIG. 6, it can be seen that the slope of the current change with respect to the small amount of light change is more rapid than the change shown in the unit pixel of FIG. 5. The slope is gentler than the change shown in the unit pixel of FIG. 7.

Therefore, since the CMOS image sensor of FIG. 7 also has no control signal as in the conventional reset, since the metal lines are reduced in the layout of the pixels, the pitch size may be reduced compared to the existing unit pixels, and a small amount of light may be applied to the PMOS. Even when this incident, a large amount of current can flow, so that a clear phase can be realized at low light, and integration time is unnecessary, thereby enabling high speed video.

In addition, since the CMOS image sensor of FIG. 7 implements a unit pixel in a general MOS process, a dedicated process of the existing CMOS image sensor is not necessary, and thus, an effect of increasing process yield and reducing process cost may be induced in the future. Can be.

In the above, the CMOS image sensor, which has a high sensitivity and high-speed processing even at low light by configuring the unit pixel structure of the light receiving unit PMOS and the output NMOS, has been described. A light receiving unit CMOS for generating a typical signal is formed, and an output unit CMOS for outputting a signal received from the PMOS is formed using one NMOS.

However, the CMOS image sensor having such a structure may be problematic in that it is excellent in sensitivity to light. That is, there is no problem due to the high sensitivity at low illuminance, but may cause a problem of saturation of the photocurrent at high illuminance. In particular, this phenomenon is expected at 1000 lux or more, and will be described below.

8 is a circuit diagram illustrating a structure of a CMOS image sensor according to an exemplary embodiment of the present invention.

Referring to FIG. 8, the CMOS image sensor according to the present exemplary embodiment includes a light receiving unit CMOS 110 that receives electric light and generates an electrical signal, and an output CMOS 120 that outputs a signal received from the light receiving unit CMOS 110. Including a sensor unit 100 provided, a plurality of the sensor unit 100 is disposed in a unit pixel.

As described above, the light receiving unit CMOS 110 is a light receiving device, and receives an external light to generate an electrical signal corresponding to the brightness of the received light. This means imaging of an external subject image.

As described above, the output unit CMOS 120 is a kind of switch element, and serves as a switch for an electrical signal output from the light receiver CMOS 110, more specifically, a current.

The sensor unit 100 refers to an assembly consisting of the light receiving unit CMOS 110 and the output unit CMOS 120. In this embodiment, a plurality of sensor units 100 are disposed in a unit pixel.

9, a plurality of current-to-voltage converters (IVC) 130 corresponding to the respective sensor units 100 are disposed at the output terminals of the sensor units 100 as shown in FIG. 9. Preferably, an analog-digital converter (not shown) may be further disposed at the rear end of the current-voltage converter 130.

The analog-to-digital converter is a device for acquiring the digital information targeted by the CMOS image sensor. As the input signal, the current-to-voltage converter 130 is required because a voltage is required.

As described above, when the plurality of sensor units 100 are disposed in a unit pixel, the light receiving unit CMOS 110 included in each of the sensor units 100 has a different length and width ratio (W / L ratio). This produces the following effects.

The difference between the length and the width of the light receiving unit CMOS is that different electric signals are output for the same light quantity, which enables active coping with the light quantity received from the outside.

That is, in low light, by selecting the sensor unit 100 that outputs a larger electrical signal and converting the output signal of the selected sensor unit 100 to digital, it is possible to take a so-called high sensitivity, By selecting the sensor unit 100 for outputting a small electrical signal and converting the output signal of the selected sensor unit 100 to digital, so-called low sensitivity can be obtained.

This operation is made by the selection of the sensor unit 100 according to the amount of light received from the outside, it is preferable to configure a separate control unit in order to provide the convenience of such selection.

10 illustrates a configuration of the controller, the controller comprising: a light measuring unit 160 for measuring the amount of light received (light quantity); And a selection unit 170 for selecting a sensor unit indicating an output satisfying a preset value according to the amount of received light among the plurality of sensor units 100 according to the measurement result of the light measuring unit 160. As described above, an analog-digital converter 180 for converting the analog output of the selected sensor unit into digital may be further disposed at the output terminal.

The light measuring unit 160 converts the received light amount into an electrical signal and provides the light to the selection unit 170. The selection unit 170 receives a signal from the light measuring unit 160 and is preset. Will be compared with the value.

The preset value is preferably set to a section value corresponding to the number of sensor units 100 disposed in the unit pixel. For example, five sensor units (first to fifth sensor units) are located within the unit pixel. Assuming the arrangement, the zone can be set by dividing by 20 units when the amount of light handled by the CMOS image sensor is 1 to 100. After that, when the output signal satisfying the light amount of 1 to 20 is measured by the optical measuring unit 160, the first sensor unit is selected, and when the light amount of 21 to 40 is measured, the second sensor unit is selected. Will be the way. The determination of the section can be made according to the use purpose and the user's preference, and in some cases, a plurality of sensor units can be selected and the output values can be used in combination. For example, when photographing a bright subject in a dark place, or conversely, in photographing a dark subject in a bright place, output values of various sensor units may be averaged.

Alternatively, the sensor part after the second sensor part may include the range of the sensor part before it. For example, when the amount of light from 1 to 40 is measured, the second selection part is selected. In this case, a bright subject and a dark subject, such as when photographing a subject in a tunnel outside the tunnel during a clear day. This is useful for capturing images and vice versa.

Of course, the first to fifth sensor units should be provided with a light receiving unit CMOS that shows an optimal output signal for a predetermined amount of light.

In this manner, the selector 170 selects only the output signal of the selected sensor unit and transmits the selected output signal to the analog-to-digital converter 180, and the analog-to-digital converter 180 is digital optimized for the received light amount. Information (subject information) can be output.

The selector 170 may be a kind of switching element, and its position may be variously set.

In FIG. 10, the selection unit 170 is disposed between the sensor unit 100 and the analog-digital converter 180. However, in some cases, the selection unit 170 is disposed between the sensor unit 100 and the analog-digital converter 180. The selector 170 may be formed in the current-voltage converter 130 disposed at the.

Alternatively, the selector 170 may be disposed at the rear end of the analog-to-digital converter 180.

In this case, the analog-to-digital converter 180 receives the outputs of all the sensor units in the unit pixel, converts them to digital, and outputs a plurality of outputs. The selector 170 may select only the output value of the output of the sensor unit corresponding to the amount of light measured by the light measuring unit 160 among the outputs of the analog-digital converter 180 to be output.

In this case, if the memory to further store the output of the analog-to-digital converter 180 before the selection by the selection unit 170, it is possible to store the image of various light amount for the same imaging, The user can check the image of various amounts of light, thereby increasing the user's convenience and satisfying the requirements.

The selection unit 170 may be disposed in various positions in addition to the above.

In the CMOS image sensor described above, it is preferable that each light receiving unit CMOS 110 in the plurality of sensor units 100 share a power supply terminal to which a power source VDD is connected.

By allowing the power stages of the light receiving unit CMOS in the plurality of sensor units to be shared, it is possible to reduce the size of the unit pixel, but reducing the number of sensor units 100 disposed in the unit pixel has a greater effect on the size reduction of the unit pixel. Get mad.

Therefore, it is preferable that two sensor units 100 are arranged in a unit pixel. In this case, it is advantageous that each sensor unit has a width and a length suitable for low light and high light. With such a configuration, it is possible to perform imaging by using an output of a so-called high-sensitivity sensor unit at low illumination, and to perform imaging by using an output of a sensor unit having low sensitivity at high illumination. As a result, a desired result (digital information) can be obtained regardless of the illuminance of the external light source.

FIG. 11 illustrates a structure of a CMOS image sensor in which two sensor units 100a and 100b are disposed in a unit pixel, and shows one unit pixel.

Whether or not the power supply VDD is shared does not matter, but as described above, the power supply VDD is shared due to a decrease in the size of a unit pixel, and the sensor units 100a and 100b may be used. Each includes one PMOS as the light receiver CMOS 110 and one NMOS as the output CMOS 120.

Since the configuration, operation and characteristics of each sensor unit 100a and 100b are the same as described above with reference to FIGS. 4 to 7, detailed descriptions thereof will be omitted.

Instead, in brief, each PMOS includes a well doped with an N-type on a P-type semiconductor substrate and receives light into a portion of the gate and the N-well, and each NMOS is formed on the P-type semiconductor substrate. The signal received from the PMOS is output, and the PMOS has a source and a drain formed in the well.

In addition, the gates of the respective PMOS may be formed to float.

The well may also be formed to float, and the gate and the well of the PMOS may not be connected to each other.

The gate of each NMOS receives a selection signal (select) from the outside so that the NMOS serves as a switching, and may further include a connection portion formed in a part of the well to connect the gate and the well of each PMOS. have.

Preferably, the connection portion is doped with the same impurity type as the well, and the doping concentration of the connection portion is preferably higher than the doping concentration of the well.

A metal contact may be formed on the connection portion to connect the connection portion to the gate of the PMOS.

The unit pixels having such a structure are arranged as many as necessary on the plane as shown in FIG. 12, and the equivalent circuit thereof is shown in FIG.

Referring to FIG. 13, each of the sensor units 100a and 100b includes one PMOS 110a and 110b as a light receiving unit CMOS, and one NMOS 120a and 120b as an output CMOS, and the power stage of the PMOS. And a gate end to which light is applied are electrically connected in a circuit.

The NMOS has a gate terminal formed as a select terminal to which an external select signal is applied, and a drain, which is an input terminal, is connected to an output terminal of the PMOS, and a source, which is an output terminal, outputs output 1 and output 2 which are different output signals. do.

11 to 13 illustrate the case where two sensor units are arranged in a unit pixel, a plurality of sensor units may be arranged as described above, which is used for the CMOS image sensor and the CMOS image sensor in an imaging system. It should be decided in consideration of the size allocated to the system.

It can be applied to image sensor using CMOS.

1A is a schematic diagram illustrating CMOS active pixels of a conventional three-transistor image sensor.

1B is a circuit diagram illustrating an equivalent circuit of FIG. 1A.

2A is a schematic diagram showing CMOS active pixels of a conventional four-transistor CMOS image sensor.

FIG. 2B is a circuit diagram showing an equivalent circuit of FIG. 2A. FIG.

FIG. 3A is a circuit diagram connected with a pixel portion consisting of a combination of pixels shown in FIGS. 1A and 2A.

3B is a graph showing a signal applied to the pixels shown in FIGS. 1A and 2A.

3C is a graph illustrating voltage drop phenomenon of data signals according to conventional illumination levels.

4 is a schematic circuit diagram illustrating a process of transferring signal charge in a unit pixel of a CMOS image sensor to solve the problems of FIGS. 1 and 2.

5 is a cross-sectional view of a unit pixel of the CMOS image sensor of FIG. 4.

FIG. 6 is a graph illustrating a PMOS current change according to light intensity change in a unit pixel of FIG. 4. FIG.

7 is a cross-sectional view of another unit pixel of a CMOS image sensor according to another example of FIG. 4.

8 is a schematic view showing a CMOS image sensor according to an embodiment of the present invention.

FIG. 9 is a schematic diagram illustrating a state in which a current-voltage converter is added to FIG. 8. FIG.

10 is a block diagram illustrating a further embodiment of FIG. 8.

11 is a cross-sectional view of the CMOS image sensor according to an embodiment of the present invention.

12 is a schematic view showing the plane in which FIG. 11 is disposed;

FIG. 13 is a circuit diagram illustrating an equivalent circuit of FIG. 11. FIG.

* Description of the symbols for the main parts of the drawings *

100.Sensor section 110.Receiver section CMOS

120 CMOS CMOS output to current converter

160 ... Optical Measurement Unit 170 ... Selection Unit

180 ... analog to digital converter

Claims (17)

A sensor unit including a light receiving unit CMOS for receiving light to generate an electrical signal and an output unit CMOS for outputting a signal received from the light receiving unit CMOS; The sensor image sensor, characterized in that arranged in a plurality of unit pixels. The method of claim 1, The CMOS image sensor further comprises a plurality of current-voltage converter to correspond to the sensor unit in the unit pixel. The method of claim 1, The CMOS image sensor, characterized in that the light receiving unit CMOS provided in each sensor unit has a different length and width ratio (W / L ratio). The method of claim 3, wherein An optical measuring unit measuring an amount of the received light; A selection unit for selecting a sensor unit displaying an output satisfying a preset value according to the amount of received light among the plurality of sensor units according to a measurement result of the light measuring unit; CMOS image sensor further comprises. The method of claim 4, wherein The selector is a CMOS image sensor, characterized in that the first sensor unit is selected when the amount of light input is a low light amount, the second sensor unit is selected when the amount of light is high. The method of claim 1, Each of the light receiving unit CMOS in the plurality of sensor units has a structure sharing a power supply terminal to which a power supply (VDD) is connected. The method of claim 1, The CMOS image sensor, characterized in that two arranged in the unit pixel. The method of claim 7, wherein The CMOS image sensor having the two light receiving unit CMOS has a different length and width ratio (W / L ratio) so that different current values are output for the same amount of light. The method of claim 1, And the light receiver CMOS is one PMOS, and the output CMOS is one NMOS CMOS sensor. The method of claim 9, The PMOS includes a well doped with an N-type on a P-type semiconductor substrate, and has a structure for receiving light into a region of a gate and an N-well, The NMOS is a CMOS image sensor, characterized in that for outputting the signal received from the PMOS on a P-type semiconductor substrate. The method of claim 10, And the PMOS has a source and a drain formed in the well. The method of claim 10, And the gate of the PMOS is floated. The method of claim 10, The gate of the NMOS CMOS sensor, characterized in that for receiving a selection signal from the outside. The method of claim 10, And a connection part formed in a portion of the well to connect the gate of the PMOS to the well. The method of claim 14, And the connection part is formed by doping with the same impurity type as the well. The method of claim 14, And the doping concentration of the connection portion is higher than the doping concentration of the well. The method of claim 14, And a metal contact is formed on the connection part to connect the connection part and the gate of the PMOS.

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