KR20090016341A - LCD Display - Google Patents

Abstract

A liquid crystal display device is provided to secure the high aperture ratio by asymmetrically forming the storage wiring within a unit pixel region in a high frequency-driven liquid crystal display device of the TN mode. A liquid crystal display device comprises the followings: a plurality of gate lines(302) which are formed parallel to each other on the first substrate; a plurality of data lines(304) which cross the gate lines; a thin film transistor(TFT) which is formed in a region where the gate lines and data lines are crossed; a pixel electrode(314) which is formed in a unit pixel region partitioned by the gate and data lines; and a storage wire(320a) which a right and left asymmetry structure centering on the direction in which data voltage is applied.

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY DEVICE}

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device in which a storage wiring of a storage on common structure is asymmetrically formed for each unit pixel in a TN mode high frequency driving liquid crystal display device.

As the information society progresses rapidly, the field of displaying and processing large amounts of information is developing day by day. Recently, in order to meet the times of thinning, light weight, low power consumption, and the like, a need for a flat panel display (Flat Panel Display) has emerged. Accordingly, the focus is on a thin film transistor liquid crystal display device having excellent color reproducibility and thinness.

The display method of the liquid crystal display device uses the optical anisotropy and polarization property of the liquid crystal molecules. Since the structure of the liquid crystal molecules is thin and long and has a pretilt angle oriented in the arrangement, voltage is applied to the liquid crystal. When applied, the alignment direction of the liquid crystal molecules can be controlled by changing the pretilt angle of the liquid crystal molecules.

Accordingly, the liquid crystal display device arbitrarily adjusts the arrangement direction of the liquid crystal molecules by applying an appropriate voltage to the liquid crystal layer to change the molecular arrangement of the liquid crystal, and arbitrarily modulates the polarized light by the optical anisotropy of the liquid crystal. Represents image information.

In the liquid crystal panel, which is a basic element of a general liquid crystal display device, the upper color filter substrate and the lower TFT (Thin Film Transistor) array substrate are spaced apart from each other at a predetermined interval, and include liquid crystal molecules between the two substrates. It is a structure in which a liquid crystal is filled. In this case, the electrodes applying the voltage to the liquid crystal are the common electrode located on the color filter substrate and the pixel electrode located on the array substrate. When voltage is applied to these two electrodes, the vertical lines above and below are formed by the difference in the applied voltage. The manner in which the electric field controls the direction of the liquid crystal molecules positioned therebetween is used.

1 is a view showing the structure of a TFT array substrate according to the prior art.

As shown in FIG. 1, the TFT array substrate 10 is arranged in a longitudinal direction perpendicular to the plurality of gate wirings 4 formed in the transverse direction on the substrate and the gate wirings 4. A plurality of data wirings 2, TFTs formed at intersections of the gate wirings 4 and the data wirings 2, and a unit pixel region defined by crossing the gate wirings 4 and the data wirings 2; And a storage capacitor (not shown) for holding a signal applied from the data line 2 for a predetermined time.

In the above structure, a method of forming a storage capacitor in a liquid crystal display device is generally classified into a storage on gate method and a storage on common method. Here, the storage on gate structure means that the storage capacitor is formed in a predetermined region of the gate wirings, while the storage on common structure means that separate storage wirings are formed in the liquid crystal cell and the storage capacitor is formed in the constant region of the storage wirings. it means.

Next, a liquid crystal display device having the storage on common structure will be described with reference to the accompanying drawings.

FIG. 2 is a diagram illustrating a planar structure of unit pixels formed on the TFT array substrate of FIG. 1.

As shown in Fig. 2, the gate wirings 4 are uniformly spaced apart in the transverse direction on the substrate, and the data wirings 2 are constantly spaced apart in the longitudinal direction. As a result, the unit pixel area is defined by crossing the gate line 4 and the data line 2 with each other. At this time, the liquid crystal cell is located at each intersection of the data line 2 and the gate line 4, and each liquid crystal cell is provided with a TFT and a pixel electrode 14. In the unit pixel area where the gate wiring 4 and the data wiring 2 are defined to cross each other, the storage wiring 3 formed in parallel with the gate wiring 4 and the data wiring 2 by a predetermined distance is provided. do.

The TFT may include a gate electrode 10 connected to the gate line 4 and a source electrode extending and formed on the data line 2 to overlap a predetermined region with the gate electrode 10. 8) and a drain electrode 12 formed at a position corresponding to the source electrode 8 with respect to the gate electrode 10.

The pixel electrode 14 is formed in the entire region of the liquid crystal cell except for the TFT, and is electrically connected to the drain electrode 12 through the drain contact hole 16 formed on the drain electrode 12 of the TFT. .

In addition, the pixel electrode 14 and a portion of the storage line 3 overlap each other in the unit pixel area in which the storage lines 3 are formed to function as a storage capacitor 18 by interposing an insulating film (not shown) therebetween.

According to the above structure, when a gate signal is applied to each gate wiring 4 so that the channel of the TFT formed in the gate wiring 4 is turned on, the data signal is applied to the TFT while the TFT is turned on to drive the liquid crystal. Done. In this case, the voltage applied to the pixel electrode 14 forms the storage capacitor 18 together with the storage wiring 3 positioned below. That is, the storage capacitor 18 maintains a signal while the signal is not applied to the pixel electrode 14.

However, in the liquid crystal display device having the above structure, the storage wiring is formed in the edge region of each unit pixel, so that the aperture ratio is lowered. In addition, the margin for accurate bonding when the TFT array substrate and the color filter substrate forming the liquid crystal display device are bonded together. Margin should be taken into consideration, for example, in forming the black matrix of the color filter, which also lowers the aperture ratio.

If the bonding margin is not taken into consideration when the TFT array substrate and the color filter substrate are bonded together, light leakage occurs in a region where the storage wiring is formed due to a poor bonding, resulting in a lower contrast ratio and a decrease in luminance as a whole. This will lead to a decrease in yield of liquid crystal panels.

In addition, due to the parasitic capacitance Cdp formed between the storage wiring and the data wiring formed symmetrically with respect to the direction in which the data voltage is applied in the unit pixel area in consideration of a problem such as an aperture ratio, cross-talk at the site is performed. As a result of the talk, a poor image quality is caused.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a liquid crystal display device having asymmetric structure of storage wiring in a unit pixel area in a TN mode high frequency driving liquid crystal display device.

According to an aspect of the present invention, there is provided a liquid crystal display device comprising: a plurality of gate lines formed in parallel with each other on a substrate; A plurality of data lines formed to intersect the gate lines; A thin film transistor formed at an intersection of the gate line and the data line; A pixel electrode formed in a unit pixel area partitioned by the gate line and data line; And a storage line formed at an edge of the unit pixel region and having a left and right asymmetric structure with respect to a direction in which a data voltage is applied.

As a result of the above configuration, the liquid crystal display device according to the present invention can secure a high opening ratio by forming a storage wiring in an asymmetric structure in a unit pixel area, and also secures sufficient bonding margin when the TFT array substrate and the color filter substrate are bonded together. It is possible to prevent light leakage in advance, thereby improving the contrast, brightness and image quality degradation caused by the light leakage, as well as ensuring sufficient bonding margin when the TFT array substrate and the color filter substrate are bonded. This will reduce yields.

Hereinafter, the configuration will be described in detail with reference to the accompanying drawings.

3 is a view showing the structure of a TFT array substrate according to the first embodiment of the present invention, and FIG. 4 is a plan view showing unit pixels in the TFT array substrate having the storage on common structure of FIG.

As shown in FIGS. 3 and 4, the TFT array substrate 100 according to the first embodiment of the present invention has a plurality of gate wirings 102 formed in the lateral direction and vertically orthogonal to the gate wirings 102. A plurality of data lines 104 arranged in a direction, a TFT formed at an intersection area of the gate lines 102 and the data lines 104, and the gate lines 102 and the data lines 104 are defined to intersect. A pixel electrode 114 formed in a unit pixel region and a storage line 120a formed at an edge of the unit pixel region and having a “c” shaped left and right asymmetric structure with respect to a direction in which a data voltage is applied. At this time, at least one side of the storage line 120a formed at the edge of the unit pixel area overlaps the pixel electrode to hold the storage capacitor 118 for maintaining a signal applied from the data line 104 for a predetermined time. Form.

The TFT is formed near the intersection of the gate wiring 102 and the data wiring 104, and its detailed configuration extends to the gate electrode 102a and the data wiring 104 which are connected to the gate wiring 102. A source electrode 104a formed to overlap a predetermined region with the gate electrode 102a, and a drain electrode 104b formed at a position corresponding to the source electrode 104a based on the gate electrode 102a.

The pixel electrode 114 is formed in the entire region of the liquid crystal cell except for the TFT, and is electrically connected to the drain electrode 104b through the drain contact hole 116 formed on the drain electrode 104b of the TFT.

The storage wiring 120a is formed at an edge region of the unit pixel. In other words, the storage wiring 120a is formed at three edges of the unit pixel area defined by the gate wiring 102 and the data wiring 104. More specifically, the storage wiring 120a is horizontal to the gate wiring 102 on both sides. The storage wiring 120a is formed in each of the unit pixel regions, and the storage wiring 120a is horizontal to the data wiring 104 in one unit pixel region of the data wiring 104 by connecting the respective storage wirings 120a to each other. Is formed. As a result, the storage wiring 120a formed at three edges of the unit pixel region has an asymmetrical structure of a "c" shape when the data voltage is applied.

The storage capacitor 118 has a storage on common structure having a “c” shaped asymmetric structure formed in a liquid crystal cell and a pixel electrode 114 positioned on at least one side of the storage wiring 120a. Is formed by In this case, the storage wirings 120a overlap the pixel electrode 114 with an insulating film (not shown) in a predetermined region to act as a storage capacitor 118.

As described above, the storage wiring 120a having a “c” shaped asymmetric structure in the unit pixel region may be realized by reducing the capacity of the storage capacitor 118 during high frequency driving of the liquid crystal display.

For example, when an image of a liquid crystal display device is to be implemented based on 60 Hz, the image implementation time of one frame is T, and the charging time of one frame becomes about 16.7 ms by T = 1 / f. On the basis of 75Hz, which is a higher frequency than this, the charging time is reduced to about 13.3ms when the image of one frame is implemented. Therefore, the higher the driving frequency of the liquid crystal display device, the shorter the charging and discharging time of the storage capacitor becomes. Accordingly, the total amount of charge for driving the pixel is also reduced.

In this regard, it will be described with reference to the following equation.

Here, dQ is the amount of charge charged in the storage capacitor Cst during the unit time, and when both sides are integrated over time, the total charge is obtained.

In Equation 1, the voltage of the liquid crystal display is charged and discharged, but the charge amount Q varies depending on the frequency. In other words, the higher the frequency, the shorter the charging and discharging time, so the total amount of charge may be small. As a result, when the amount of charge decreases, the pixel can be driven even if Cst is small.

Since the storage wiring 120a is asymmetrically formed in the unit pixel area, the area occupied by the asymmetrical storage wiring 120a is smaller than the area occupied by the storage wiring 120a which forms the symmetrical structure. More suitable.

In addition, the TFT array substrate 100 on which the asymmetric structure wiring line 120a is formed is bonded to each other with a color filter substrate (not shown) with a liquid crystal layer interposed therebetween. At this time, on the color filter substrate, chromium / chromium oxide (Cr / CrOx) is formed on the corresponding portion to prevent light from being transmitted to the gate wiring 102, the data wiring 104, and the TFT on the TFT array substrate 100. A black matrix is provided, and color filters of R, G, and B are formed in an area partitioned by the black matrices, and an overcoat for flattening a color filter and the like on the black matrix and the color filter. The common electrode is formed on the overcoat layer and the overcoat layer, respectively.

Therefore, the TFT array substrate 100 having the asymmetrical storage wiring 120a can sufficiently secure the bonding margin when the TFT array substrate 100 is bonded with the color filter substrate, compared with the TFT array substrate 100 having the symmetrical storage wiring. This may reduce the defect of the liquid crystal panel due to a bonding error such as light leakage.

FIG. 5 is a cross-sectional view illustrating the first example taken along the cutting line II ′ of FIG. 4, to reduce the parasitic capacitance Cdp between the data line 104 and the storage line 120a and to further reduce the storage line 120a. And a structure for increasing the capacitance Cst of the storage capacitor by increasing an overlapping area between the pixel electrode 114 and the pixel electrode 114.

3 to 5, the TFT array substrate 100 of the present invention is formed on the glass substrate 101 at the same time as the gate electrode 102a and the gate wiring 102 to have a storage width having a predetermined width (W). Parasitic capacitance Cdp formed on the gate insulating film 103 formed on the entire region of the glass substrate 101 on the storage wiring 120a and the storage wiring 120a. In order to reduce the C), the data line 104 formed by securing a predetermined distance d, the protective film 105 formed on the glass substrate 101 on which the data line 104 is formed, and the predetermined width W And the pixel electrode 114 overlapping the entire area on the storage wiring 120a.

Here, the TFT array substrate 100 having the asymmetric structure wiring line 120a according to the present invention can realize high opening ratio by forming the storage line 120a on one side of the data line 104 in the unit pixel area. In addition, the distance d between the data line 104 and the storage line 120a can be sufficiently secured to reduce the parasitic capacitance Cdp between the data line 104 and the storage line 120a at the portion thereof. Will be. In this regard, it will be described with reference to the following equation.

Here, epsilon ₀ is the permittivity of the liquid crystal, A is the area overlapping between the storage wiring and the data wiring, and d is the distance between the storage wiring and the data wiring.

As can be seen from Equation 2 above, when the distance d between the storage wiring 120a and the data wiring 104 becomes larger, the parasitic capacitance Cdp becomes smaller, which is why the TFT array substrate 100 is used. In consideration of this, the pattern of the storage wiring 120a and the data wiring 104 is formed.

As a result, the predetermined distance d between the storage line 120a and the data line 104 becomes wider, thereby improving the crosstalk phenomenon caused by the parasitic capacitance Cdp.

In addition, as shown in FIG. 5, the pixel electrode formed on the TFT array substrate 100 having the asymmetrical storage wiring 120a according to the present invention overlaps with all regions on the storage wiring 120a having a predetermined width W. Since the area B of the 114 may be increased, the capacity of the storage capacitor Cst may be increased accordingly.

In other words, it is possible to secure a predetermined interval for reducing the parasitic capacitance Cdp between the asymmetrical storage wiring 120a and the data wiring 104, and as a result, on the storage wiring 120a having a predetermined width W The storage capacitor Cst may be formed by overlapping the pixel electrode 114 in the entire area, which is used to form the parasitic capacitance Cdp between the data line 104 and the pixel electrode 114 in manufacturing the TFT array substrate 100. It also means no consideration.

However, for example, the storage wiring 102a is made of aluminum alloy (AlNd) or the like to have a thickness of approximately 2500 to 2800 kPa, and the data wiring 104 made of molybdenum (Mo) is roughly considering the resistance of the lead wire. Assume that it is formed to be 1.5 times the thickness (h1) of the storage wiring (102a). In this case, as shown in FIG. 5, when the asymmetrical storage line 120a is formed, a light leakage problem may occur in one region A1 in which the storage line 120a is not formed based on the data line 104.

FIG. 6 is a diagram illustrating a structure of a data line for improving light leakage of FIG. 5, and is a cutaway view illustrating a second example along the cutting line I-I ′ of FIG. 4.

As shown in FIG. 6, the TFT array substrate 200 of the present invention is formed at the same time as the formation of the gate electrode and the gate wiring 202 on the glass substrate 201 and the storage wiring 220a having a predetermined width (W). ), A gate insulating film 203 formed over the entire area of the glass substrate 201 on the storage wiring 220a, and a predetermined distance formed on the gate insulating film 103 to reduce the parasitic capacitance generated from the storage wiring 220a. (d) a data line 204 for reducing the light leakage region A2 of the side portion by securing a cell gap and increasing a cell gap; and a passivation layer 205 formed on the glass substrate 201 where the data line 204 is formed. ) And the pixel electrode 214 overlapping the entire area on the storage wiring 220a having the predetermined width W.

The light leakage region A2 is formed on the gate insulating layer 203 to secure the predetermined distance d and increase the cell gap in order to reduce the parasitic capacitance Cdp generated from the storage wiring 220a. The reducing data line 204 can reduce its thickness h2 compared to the data line 104 shown in FIG.

For example, suppose that the thickness h2 of the data line 204 is reduced to an equivalent level of the storage line 220a in order to reduce the light leakage as described above. In this case, when the data line 204 is formed by using molybdenum (Mo) of the same material as described above, the resistance value of the data line 204 is relatively increased.

Therefore, in the present invention, in order to compensate for the resistance of the data line 204, copper (Cu) or the like having higher electrical conductivity than molybdenum may be more preferable. However, the present invention is not limited thereto.

On the other hand, with reference to Figure 6 briefly described with respect to the manufacturing method of the TFT array substrate 200 according to the first embodiment of the present invention.

First, the gate electrode, the gate wiring, and the storage wiring 220a are simultaneously formed on the glass substrate 201, and the gate is formed on the entire surface of the glass substrate 201 on which the gate electrode, the gate wiring, and the storage wiring 220a are formed. The insulating film 203 is formed.

In addition, an active layer is formed on the gate insulating layer 203 in which a semiconductor layer made of amorphous silicon and an ohmic contact layer made of n + amorphous silicon doped with phosphorus (P) at a high concentration are formed.

In addition, by forming source and drain electrodes on the active layer, a thin film transistor is formed together with the gate electrode, and at the same time, the data line 204 is patterned on the gate insulating layer 203. In this case, copper (Cu) having excellent electrical conductivity may be suitable for the data wire 204.

In addition, the passivation layer 205 is formed on the entire surface of the substrate 201 including the source electrode and the drain electrode. In this case, an inorganic insulating film such as silicon nitride (SiNx) or silicon oxide (SiOx) may be applied to the passivation layer 205. In order to improve the opening ratio of the liquid crystal display device, benzocyclobuten (BCB) having low dielectric constant, spin- An organic insulating film such as on glass or acrylic may be applied.

A contact hole exposing a part of the drain electrode is formed in the passivation layer 205.

The pixel electrode 214 is formed on the passivation layer 205, and the pixel electrode 214 and the drain electrode are electrically connected to each other through the contact hole.

FIG. 7 is a diagram illustrating a structure of a TFT array substrate according to a second embodiment of the present invention, and FIG. 8 is a plan view illustrating unit pixels in a TFT array substrate having a storage on common structure of FIG. 7.

As shown in FIGS. 7 and 8, the TFT array substrate 300 includes a plurality of gate wires 302 formed in a lateral direction and a plurality of data wires arranged in a longitudinal direction perpendicular to the gate wire 302. The pixel electrode 314 formed in the unit pixel region defined by the intersection of the 304, the TFT formed in the intersection of the gate wiring 302 and the data wiring 304, and the gate wiring 302 and the data wiring 304 intersect. And a storage line 320a formed at an edge of the unit pixel area and having a left-right asymmetric structure having an “L” shape with respect to a direction in which a data voltage is applied. At least one side of the formed storage line 320a overlaps the pixel electrode 314 to form a storage capacitor 318 for maintaining a signal applied from the data line 304 for a predetermined time.

Here, the storage line 320a is formed at an edge of the unit pixel area so as to have a left-right asymmetrical structure of "L" shape with respect to the direction in which the data voltage is applied.

At this time, the “L” shaped storage wiring 320a is not necessarily limited to the L shaped and is not shown in the drawing but is symmetrical with the “L” shaped with respect to the “L” shaped based on the direction in which the data voltage is applied in the unit pixel area. The opposite shape can be achieved.

Furthermore, the storage wiring according to the present invention may be "a" shaped based on the direction in which the data voltage is applied in the unit pixel area by deforming the "L" shape, or based on the direction in which the data voltage is applied. It can also take the form of a and symmetrical opposite shapes.

And other details except this part will be replaced with the above.

1 shows the structure of a TFT array substrate.

2 illustrates a planar structure of a unit pixel formed on the TFT array substrate of FIG.

3 shows the structure of a TFT array substrate according to a first embodiment of the present invention.

4 is a plan view illustrating unit pixels in a TFT array substrate having the storage on common structure of FIG.

5 is a cross-sectional view showing a first example seen along the cutting line I-I` of FIG.

FIG. 6 is a sectional view showing a second example along the cutting line I-I` of FIG.

7 shows the structure of a TFT array substrate according to a second embodiment of the present invention.

8 is a plan view illustrating unit pixels in a TFT array substrate of FIG. 7;

＊＊ Explanation of symbols for main parts of drawings *＊

102, 202, and 302: gate wirings 102a and 302a: gate electrodes

104, 204, 304: data wiring 104a, 304a: source electrode

104b, 304b: drain electrodes 114, 214, 314: pixel electrodes

116, 316: contact holes 118, 318: storage capacitor

120a, 220a, 320a: storage wiring

Claims (6)

A plurality of gate wires formed in parallel with each other on the first substrate; A plurality of data lines formed to intersect the gate lines; A thin film transistor formed at an intersection of the gate line and the data line; A pixel electrode formed in a unit pixel area partitioned by the gate line and data line; And And a storage line formed at an edge of the unit pixel region and having a left and right asymmetric structure with respect to a direction in which a data voltage is applied. The liquid crystal display device according to claim 1, wherein the asymmetrical storage wiring has an "L" shape with respect to the direction in which the data voltage is applied. The liquid crystal display of claim 1, wherein the asymmetrical storage wiring has a "-" shape with reference to a direction in which a data voltage is applied. The liquid crystal display of claim 1, wherein at least one side of the storage line formed in the unit pixel area overlaps the pixel electrode to form a storage capacitor. The liquid crystal display of claim 1, wherein the pixel electrode is formed to overlap an entire area of the storage wiring having a predetermined width. 2. The liquid crystal display device according to claim 1, wherein when the data line is formed of copper (Cu), its thickness (h) is formed in a range of 2500 k?

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