KR20080114200A - Internal Voltage Generator Control - Google Patents

Abstract

The internal voltage generator control apparatus of the present invention includes a first internal voltage generator group including an internal voltage generator for supplying internal voltages to banks included in a first bank group, and activation of banks included in the first bank group. A second internal voltage generator control unit configured to operate a specific internal voltage generator of the first internal voltage generator group and a second internal voltage generator supplying an internal voltage to banks included in the second bank group according to whether And a second internal voltage generator controller configured to operate a specific internal voltage generator of the second internal voltage generator group according to whether the internal voltage generator group and the banks included in the second bank group are activated.

Description

Controller of internal voltage generator

FIG. 1A is a diagram illustrating an internal voltage generator activator used in a method of allocating a power generator for each bank.

1B is a waveform diagram illustrating a voltage applied when the internal voltage generator activator is operated.

FIG. 2A is a diagram illustrating a circuit used in the case of a method of driving a power generator according to the number of activated banks.

2B is a waveform diagram showing a voltage applied in the operation of the circuit.

Figure 2c is a diagram showing the arrangement of the power generating device according to the above scheme.

3 is a block diagram showing an arrangement of a bank and an internal voltage generator according to an embodiment of the present invention.

4 is a circuit diagram illustrating an internal voltage generator control device according to an embodiment of the present invention.

5 is a circuit diagram showing a detailed configuration of the active bank number determination unit.

6A is a circuit diagram illustrating a logic circuit including the first, second, fifth, and sixth logic circuits.

6B is a circuit diagram illustrating a logic circuit including the third and fourth logic circuits.

7 is a circuit diagram illustrating in detail the first internal voltage generator activator.

8 is a waveform diagram illustrating an operation of an internal voltage generator control device according to an embodiment of the present invention.

9 is a block diagram showing an arrangement of a bank and an internal voltage generator according to another embodiment of the present invention.

10 is a circuit diagram illustrating an internal voltage generator control device according to another embodiment of the present invention.

Description of the main parts of the drawing

400: internal voltage generator control device

410: first internal voltage generator control unit

412: number of first active banks

414: First internal voltage generator activator

420: first internal voltage generator group

430: second internal voltage generator control unit

432: second active bank number determination unit

434: second internal voltage generator activation unit

440: second internal voltage generator group

The present invention relates to a control device for an internal voltage generator, and more particularly to a control device for an internal voltage generator for controlling the operation according to the number of active banks.

The semiconductor memory device uses an internal voltage generator as needed for internal circuit operation. In particular, in the case of DRAM, an internal power source, which is generated internally in addition to an externally applied power source (vdd), is used to operate stably regardless of an external voltage and to reduce power consumption. The internal power supply includes the core power supply (vcore) used as the cell's amplification power supply, the boost power supply (vpp) used to raise the word line voltage to a high level, and the bitline precharge power supply (vblp) used for the bit line precharge. Cell plate power (vcp).

The core power source (vcore) and the boost power source (vpp) are representative power sources whose current consumption varies greatly depending on whether the bank is active or in a standby state. These two power supplies are used to activate the word line (WL) and amplify the cell data, which greatly increases the current consumption during bank activation. Therefore, it is very important to control stably so that the voltage of this internal power supply does not lower at the time of bank activation. To this end, a core power driver (vcore driver) or a boosted power pump (vpp pump) that operates only when the bank is active will cover the increasing current consumption. The core power driver and the boost power pump are referred to as active vcore drivers and active vpp pumps, respectively.

There are two ways to control such a power generator.

The first control method is to allocate an active core power driver and an active boosting power pump to each bank, and when the bank is active, the active core power driver and the active boosting power pump are driven. In this method, since the number of banks requires an active core power driver and an active boosting power pump, there may be a case where more power generators are required than the actual number, and in this case, there is a disadvantage of increasing the size of the DRAM.

The second control method is to distribute the active core power driver and the active boosting power pump evenly across the DRAM, and then drive the power generator according to the number of banks that are activated. This method has the advantage that there can be as many power generators as necessary, but the distance between the active bank and the driven power generator is not uniform, so that sufficient power may not be supplied to the active bank. There are disadvantages. This problem increases as the number of memories of the DRAM increases and the size increases, and the number of banks increases.

In order to solve the above problems, the present invention is characterized by providing an internal voltage generator control device for classifying a plurality of banks into two or more groups, and different internal voltages are applied to each group.

An internal voltage generator control apparatus of the present invention for achieving the above object includes a first internal voltage generator group including an internal voltage generator for supplying an internal voltage to banks included in a first bank group, and the first bank. A first internal voltage generator controller for operating a specific internal voltage generator of the first internal voltage generator group according to whether the banks included in the group are activated, and an internal supplying internal voltage to the banks included in the second bank group A second internal voltage generator group including a voltage generator, and a second internal voltage generator controller configured to operate a specific internal voltage generator of the second internal voltage generator group according to whether the banks included in the second bank group are activated. It is characterized by.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1A illustrates an internal voltage generator activator used in a method of allocating a power generator for each bank, and FIG. 1B is a waveform diagram illustrating a voltage applied when an internal voltage generator activator is operated.

First, each signal is defined.

The bank active signal rastb <m> indicating that a specific bank is activated is outputted with a low level signal when the corresponding bank is activated. The bank active signal ractvbp <m> and the bank precharge signal rpcgbp <m> are signals generated from the bank active signal rastb <m>, and when the bank active signal is at a low level, The active signal goes low and when the bank active signal goes high, the bank precharge signal goes low.

The internal voltage generator activator is configured to supply a high level or low level voltage to the first node n1 in response to the bank reactive signal ractvbp <m> and the bank precharge signal rpcgbp <m>. The first power supply 110, a second power supply 120 supplying a high level voltage to the first node n1 according to a power-up signal pwrup, and a voltage applied to the first node n1 are temporarily stored. The latch unit 130 includes a storage unit 130, an inverting unit 140 for inverting the output of the latch unit, and a delay output unit 150 for outputting the core power active signal vcore_act by delaying the output of the inverting unit.

Referring to FIG. 1B, in operation, the low level bank active signal ractvbp <0> is output in response to the low level bank active signal rastb <0>. As a result, the NMOS transistor N110 is turned on, and a low level voltage is applied to the first node.

The low level voltage is applied to the NAND gate included in the delay output unit 150 via the latch unit 130 and the inverting unit 140. Therefore, a high level core power source active signal vcore_act is output.

Thereafter, in response to the high level bank active signal rastb <0>, a low level bank precharge signal rpcgbp <0> is output. As a result, the PMOS transistor P110 is turned on to apply a high level voltage to the first node.

The high level voltage is applied to the NAND gate included in the delay output unit 150 via the latch unit 130 and the inverting unit 140. On the other hand, another high level voltage is applied to the NAND gate after a predetermined time by the delay unit, and a low level core power source active signal vcore_act is output.

In this method, since the number of the active core power driver and the active boosting power pump must be as many as the number of banks, there may be a case in which more power generation devices than the actual number are required, and in this case, there is a disadvantage of increasing the size of the DRAM.

FIG. 2A illustrates a circuit used in the case of a method of driving a power generator according to the number of active banks, FIG. 2B is a waveform diagram illustrating a voltage applied when the circuit is operated, and FIG. According to the scheme, it is a view showing the arrangement of the power generator.

Referring to FIG. 2A, the internal voltage generator control apparatus 200 includes an active bank number determining unit 210, an internal voltage generator activating unit 220, and an internal voltage generator 230.

 The active bank number determination unit 210 determines the state value of a bank active signal rastb for activating each bank or performing an auto refresh, and determining how many banks are operated among a total of m banks. Judge.

The bank active signals rastb <m> are signals representing a row active state of a corresponding bank, respectively, and indicate that the corresponding bank is in an active state when the bank is at a low level. For example, rastb <1> represents the low active state of bank 1 (not shown).

The driving enable signal drv_en of the active bank number determination unit 210 is a signal (drv_en <0>) indicating whether the number of active banks is one, and a signal indicating whether the number of active banks is two ( drv_en <1>), a signal for whether there are three active banks (drv_en <2>), ..., a signal for whether an active bank is n, which is the number of the internal voltage generators (drv_en <n-1) >). Since the illustrated invention includes a total of four internal voltage generators, a total of four drive enable signals are generated.

The internal voltage generator activator 220 analyzes the drive enable signal of the active bank number determination unit 210 to determine the number of internal voltage generator activation signals corresponding to the number of active banks among the plurality of banks. drv_act <n>).

According to the driving enable signal drv_en <s> of the active bank number determination unit 210, an operation signal for activating as many internal voltage generators as necessary is output.

Referring to FIG. 2B, the detailed operation is as follows.

When a low level bank active signal rastb <0> is input among the bank active signals rastb <0: 7>, the number of active banks 210 determines that one bank is active, and thus, the high level zeroth level is generated. The first driving enable signal drv_en <0> is output, which is input to the internal voltage generator activator 220 to output the high level first internal voltage generator activation signal drv_act <0>.

When the low level bank active signal rastb <3>, which means that the third bank is active, is input, the active bank number determination unit 210 may activate the second bank of the high level since the two banks are active. A signal drv_en <1> is output, which is input to the internal voltage generator activator 220 to output a high level second internal voltage generator activation signal drv_act <1>.

In this manner, when four or more bank active signals are transitioned to the low level, the first to fourth internal voltage generator activation signals drv_act <0: 3> become high levels, and each bank active signal transitions to the high level again. In response to the number of the activated banks, the transition from the fourth voltage internal voltage generator activation signal drv_act <3> to the low level is sequentially performed.

In this case, however, since the distance between the active bank and the driven power generator is not uniform, a sufficient amount of power may not be supplied to the active bank.

Referring to FIG. 2C, a plurality of banks B0 to B7 and a plurality of internal voltage generators A0 to A3 are disposed. The internal voltage generator refers to an active core power driver, an active boosting power pump, and the like mentioned above. For example, if the fourth bank B3 is active and the first internal voltage generator A0 is operated, sufficient power is supplied to the fourth bank by a power drop caused by the distance between the first internal voltage generator and the fourth bank. This fails to supply.

In order to solve the above problems, the present invention divides each bank into several groups, and includes an internal voltage generator for each group.

3 is a block diagram showing an arrangement of a bank and an internal voltage generator according to an embodiment of the present invention.

In the present invention, the entire bank is divided into two groups, and the internal voltage generator for supplying the internal voltage is also controlled separately.

That is, the first to fourth banks B0 to B3 are referred to as a first bank group 310, and the fifth to eighth banks B4 to B7 are referred to as a second bank group 330.

The first internal voltage generator group 320 includes an internal voltage generator for supplying internal voltages to the banks included in the first bank group, and the internal voltages for the banks included in the second bank group. It includes a second internal voltage generator group 340 including an internal voltage generator for supplying the.

The first internal voltage generator group 320 includes first and second internal voltage generators A0 and A1. In addition, the second internal voltage generator group 340 includes third and fourth internal voltage generators A2 and A3.

 According to the present invention, when the bank belonging to the first bank group is activated, the internal voltage generator belonging to the first internal voltage generator group is controlled to operate, and when the bank belonging to the second bank group is activated, the second internal voltage generator group is activated. We want to control the internal voltage generator to belong to.

4 is a circuit diagram illustrating an internal voltage generator control device according to an embodiment of the present invention.

The internal voltage generator control device may include a first internal voltage generator controller 410 for operating a specific internal voltage generator of the first internal voltage generator group according to whether the banks included in the first bank group are activated, and the second bank group. And a second internal voltage generator controller 430 for operating a specific internal voltage generator of the second internal voltage generator group according to whether the included banks are activated.

The first internal voltage generator controller 410 may include a first active bank number determination unit 412 for identifying an activated bank among banks belonging to a first bank group, and a first active bank number determination unit according to an output of the first active bank number determination unit. A first internal voltage generator activator 414 for outputting a control signal for activating a specific internal voltage generator of the first internal voltage generator group.

On the other hand, the second internal voltage generator control unit 430 is connected to the output of the second active bank number determination unit 432 for identifying the active bank of the banks belonging to the second bank group, and the output of the second active bank number determination unit. Accordingly, the second internal voltage generator activator 434 outputs a control signal for activating a specific internal voltage generator of the second internal voltage generator group.

 The first active bank number determiner 412 receives a bank active signal rastb <0: 3> indicating that a specific bank is active among banks belonging to the first bank group and determines how many banks are active. .

Similarly, the second active bank number determiner 432 receives a bank active signal rastb <4: 7> indicating that a specific bank is active among banks belonging to the second bank group, and how many banks are active. To judge.

A detailed configuration of the active bank number determination unit will be described.

5 is a circuit diagram showing a detailed configuration of the active bank number determination unit.

The active bank number determination unit may include a first logic circuit unit 510 and a third and fourth bank active signals rastb <2: 3> that receive first and second bank active signals rastb <0: 1>. A second logic circuit portion 520 having an input as an input, a third logic circuit portion 530 having a first output of the first logic circuit portion as a first input and a second output of the second logic circuit portion as a second input, A fourth logic circuit portion 540 having a second output of the first logic circuit portion as the second input and a first output of the second logic circuit portion as the first input, and a first output of the third logic circuit portion as the first input And a fifth logic circuit unit 550 for outputting the driving enable signal drv_en <0: 1> as a second input as a first output of the fourth logic circuit unit, and a second output of the third logic circuit unit as a first input. And a sixth logic circuit portion 560 which serves as an input and uses a second output of the fourth logic circuit portion as a second input.

The first, second, fifth and sixth logic circuits include logic circuits identical to each other. The third and fourth logic circuit sections also include the same logic circuit.

6A is a circuit diagram illustrating a logic circuit included in the first, second, fifth, and sixth logic circuit parts, and FIG. 6B is a circuit diagram illustrating a logic circuit included in the third and fourth logic circuit parts.

The first, second, fifth, and sixth logic circuits negatively multiply two different input signals to output a first output signal, and a second negative logical sum of two different input signals. And a first negative AND gate NOR610 that outputs an output signal.

The truth table of this logic is as follows.

First input Second input First output Second output One One 0 0 One 0 One 0 0 One One 0 0 0 One One

That is, when both the first and second inputs are at the low level, both the first and second outputs are at the high level to output the first and second driving enable signals at the high level.

In addition, when only one of the first input and the second input is at the low level, only the first driving enable signal is applied at the high level.

In addition, the third and fourth logic circuits may perform a negative logic OR on two different input signals to output a first output signal, and the second logic signal may be negatively ANDed on two different input signals to generate a second output signal. And a second negative AND gate NAND620 for outputting.

The truth table of this logic is as follows.

First input Second input First output Second output One One 0 0 One 0 0 One 0 One 0 One 0 0 One One

Referring to FIG. 5 again, the operation of the active bank number determination unit is as follows.

For example, it is assumed that the third bank active signal rastb <2>, which means that the third bank B2 is activated, is input. If so, the first, second and fourth bank active signals are at a high level, and only the third bank active signal is at a low level.

That is, a high level signal is input to the first and second inputs of the first logic circuit unit 510, a low level signal is input to the first input of the second logic circuit unit 520, and a high level signal is input to the second input. Is input.

Accordingly, both the first and second outputs of the first logic circuit unit 510 become low level signals, the first output of the second logic circuit unit 520 becomes high level, and the second output becomes low level.

Next, since the third logic circuit unit 530 uses the first output of the first logic circuit unit as the first input and the second output of the second logic circuit unit as the second input, the first and second outputs of the high level are provided. Will print

In addition, the fourth logic circuit unit 540 uses the second output of the first logic circuit unit as the second input and the first output of the second logic circuit unit as the first input. Output a second output.

In addition, since the fifth logic circuit unit 550 uses the first output of the third logic circuit unit as the first input and the first output of the fourth logic circuit unit as the second input, the fifth logic circuit unit 550 has a high level of the first output and the low level. Output a second output. At this time, the high level first output is output as the first driving enable signal drv_en <0>.

In summary, when only one bank is activated, the active bank number determination unit outputs only the first driving enable signal drv_en <0> at a high level. When two or more banks are activated, the first and second driving enable signals drv_en <0: 1> are output at a high level.

That is, only the second driving enable signal drv_en <1> may not be at the high level alone, and only two driving enable signals are output even when three or four banks are activated.

Referring again to FIG. 4, the first active bank number determiner 410 outputs a driving enable signal according to the number of activated banks among the banks belonging to the first bank group. In addition, the second active bank number determination unit 410 outputs a driving enable signal according to the number of activated banks among the banks belonging to the second bank group.

Now, the first and second internal voltage generator activation units 420 and 450 will be described.

7 is a circuit diagram illustrating in detail the first internal voltage generator activator.

Meanwhile, the configuration of the second internal voltage generator activator is also substantially the same as that of the first internal voltage generator activator.

The internal voltage generator activator receives the first and second driving enable signals drv_en <0: 1> and outputs the delayed time. However, such a delay effect occurs only when the driving enable signal transitions from a high level to a low level. In other words, when the driving enable signal transitions from the low level to the high level, the signal is changed as soon as the transition is made.

To this end, the inverter includes an inverter INV710 for inputting the first driving enable signal, a negative AND gate NAND710 for inputting a signal of the output signal of the inverter and a delay of the output of the inverter for a predetermined time. In addition, a delay unit 710 delaying the output signal of the inverter for a predetermined time is included.

In addition, the inverter includes an inverter INV720 for inputting the second drive enable signal, a negative AND gate NAND720 for inputting a signal obtained by delaying the output signal of the inverter and the output of the inverter for a predetermined time. In addition, the delay unit 720 for delaying the output signal of the inverter for a predetermined time.

Therefore, when a high level driving enable signal is input, a low level signal is input to the negative AND gate, and accordingly a high level internal voltage generator activation signal drv_act <n> is output.

On the other hand, when the low level driving enable signal is input, since the low level signal through the delay unit is applied to the negative logic product gate for a predetermined time, a high level internal voltage generator activation signal is output during the predetermined time, After the elapse, a low level internal voltage generator activation signal is output.

Each of the internal voltage generators operates according to the internal voltage generator activation signal.

Now, the operation of the internal voltage generator control device will be described.

8 is a waveform diagram illustrating an operation of an internal voltage generator control device according to an embodiment of the present invention.

First, in response to the application of the low level first bank active signal rastb <0> indicating that the first bank belonging to the first bank group is activated, the first number of active banks determiner 410 determines whether the first bank belongs to a high level. A driving enable signal drv_en <0> is output. In addition, the first internal voltage generator activation unit 420 outputs a first internal voltage generator activation signal drv_act <0> according to the output of the high level first driving enable signal drv_en <0>. .

Next, in response to the application of the fourth bank active signal rastb <3> indicating that the fourth bank belonging to the first bank group is activated, the first number of active banks determiner 410 determines whether the first and second banks have a high level; The second driving enable signal drv_en <0: 1> is output. In addition, according to the output of the high level first and second driving enable signals drv_en <0: 1>, the first internal voltage generator activator 420 may include the first and second internal voltage generator activation signals ( drv_act <0: 1>).

On the other hand, when the activation of the fourth bank is stopped, the fourth bank active signal rastb <3> transitions to a high level, and accordingly, the first number of active banks determiner 410 is a second driving at a high level. The enable signal drv_en <1> transitions to the low level. However, even when the second driving enable signal transitions to the low level, the internal voltage generator activation signal delays the corresponding signal for a predetermined period, and outputs the high level internal voltage generator activation signal during the corresponding period.

Next, in response to the application of the low level eighth bank active signal rastb <7> indicating that the eighth bank belonging to the second bank group is activated, the number of the second active banks 440 is determined to be high level. The third driving enable signal drv_en <2> is output. In addition, the second internal voltage generator activation unit 450 outputs a third internal voltage generator activation signal drv_act <2> according to the output of the high level third driving enable signal drv_en <2>. .

Next, in response to the application of the seventh bank active signal rastb <6> indicating that the seventh bank belonging to the second bank group is activated, the second active bank number determination unit 440 determines that the third bank has a high level of third. And a fourth driving enable signal drv_en <2: 3>. In addition, according to the output of the high level third and fourth driving enable signals drv_en <2: 3>, the second internal voltage generator activation unit 450 may generate the third and fourth internal voltage generator activation signals ( drv_act <2: 3>).

Next, in response to the application of the fifth bank active signal rastb <4> indicating that the fifth bank belonging to the second bank group is activated, the second number of active banks determiner 440 may generate the third and third high-level banks. The fourth driving enable signal drv_en <2: 3> is output. In addition, according to the output of the high level third and fourth driving enable signals drv_en <2: 3>, the second internal voltage generator activation unit 450 may generate the third and fourth internal voltage generator activation signals ( drv_act <2: 3>). That is, even if the number of banks to be activated is added, since the two internal voltage generators are already activated, there is no change in the state of each control signal.

In summary, the internal voltage generator included in the first internal voltage generator group operates according to the operation of the bank included in the first bank group, and the internal voltage generator that operates according to the number of operations of the bank varies. In addition, the internal voltage generator included in the second internal voltage generator group operates according to the operation of the bank included in the second bank group, and the internal voltage generator that operates according to the number of operations of the bank may also vary.

9 is a block diagram showing an arrangement of a bank and an internal voltage generator according to another embodiment of the present invention.

The entire bank is divided into four groups, with the internal voltage generator supplying the internal voltage separately controlled separately.

That is, the first and second banks B0 and B1 are referred to as a first bank group 910 and include an first voltage generator A0 as an internal voltage generator that supplies an internal voltage to the first bank group. have.

In addition, the third and fourth banks B2 and B3 may be referred to as a second bank group 920, and include a second voltage generator A1 as an internal voltage generator that supplies an internal voltage to the second bank group. have.

In addition, the fifth and sixth banks B4 and B5 are referred to as a third bank group 930, and include a third voltage generator A2 as an internal voltage generator that supplies an internal voltage to the third bank group. have.

In addition, the seventh and eighth banks B6 and B7 are referred to as a fourth bank group 940 and include an fourth voltage generator A3 as an internal voltage generator that supplies an internal voltage to the fourth bank group. have.

According to the present invention, when the bank belonging to the first bank group is activated, the first internal voltage generator is controlled to operate. When the bank belonging to the second bank group is activated, the second internal voltage generator is controlled to operate. The third internal voltage generator is controlled to operate when the bank belonging to the third bank group is activated, and the fourth internal voltage generator is controlled to operate when the bank belonging to the fourth bank group is activated.

10 is a circuit diagram illustrating an internal voltage generator control device according to another embodiment of the present invention.

The internal voltage generator control device may include a first internal voltage generator controller 1010 for operating a specific internal voltage generator of the first internal voltage generator group according to whether the banks included in the first bank group are activated, and the second bank group. A second internal voltage generator controller 1020 that operates a specific internal voltage generator of the second internal voltage generator group according to whether the included banks are activated, and a third internal voltage according to whether the banks included in the third bank group are activated A third internal voltage generator controller 1030 for operating a specific internal voltage generator of the generator group, and a fourth for operating a specific internal voltage generator of the fourth internal voltage generator group according to whether the banks included in the fourth bank group are activated An internal voltage generator control unit 1040.

The first internal voltage generator controller 1010 may include a first active bank number determination unit 1012 for identifying an activated bank among banks belonging to a first bank group, and a first active bank number determination unit according to an output of the first active bank number determination unit. The first internal voltage generator activator 1014 outputs a control signal for activating a specific internal voltage generator of the internal voltage generator group.

On the other hand, the second internal voltage generator control unit 1020 is a second active bank number determination unit 1022 for identifying the active bank of the banks belonging to the second bank group and the output of the second active bank number determination unit Accordingly, the second internal voltage generator activator 1024 outputs a control signal for activating a specific internal voltage generator of the second internal voltage generator group.

Meanwhile, the third internal voltage generator controller 1030 may include a third active bank number determination unit 1032 for identifying an activated bank among banks belonging to a third bank group, and an output of the third active bank number determination unit. Accordingly, the third internal voltage generator activator 1034 outputs a control signal for activating a specific internal voltage generator of the third internal voltage generator group.

Meanwhile, the fourth internal voltage generator control unit 1040 may include a fourth active bank number determination unit 1042 for checking an activated bank among banks belonging to a fourth bank group, and an output of the fourth active bank number determination unit. Accordingly, the fourth internal voltage generator activator 1044 outputs a control signal for activating a specific internal voltage generator of the fourth internal voltage generator group.

The detailed operation principle is almost the same as the embodiment of FIG.

That is, the first internal voltage generator operates according to the operation of the bank included in the first bank group, and the second internal voltage generator operates according to the operation of the bank included in the second bank group and is included in the third bank group. The third internal voltage generator operates according to the operation of the bank, and the fourth internal voltage generator operates according to the operation of the bank included in the fourth bank group.

According to the above-described configuration of the present invention, each bank may be divided into groups, and internal voltages may be applied independently. This allows the internal voltage generator, which is the shortest distance from the bank, to supply the internal voltage when a particular bank is activated. As a result, power drop due to the distance between the internal voltage generator and the specific bank can be reduced.

Claims (8)

A first internal voltage generator group including an internal voltage generator supplying an internal voltage to banks included in the first bank group; A first internal voltage generator controller configured to operate a specific internal voltage generator of the first internal voltage generator group according to whether the banks included in the first bank group are activated; A second internal voltage generator group including an internal voltage generator supplying an internal voltage to banks included in the second bank group; And a second internal voltage generator controller configured to operate a specific internal voltage generator of the second internal voltage generator group according to whether the banks included in the second bank group are activated. The method of claim 1, wherein the first internal voltage generator control unit comprises: a first active bank number determination unit identifying an activated bank among banks belonging to a first bank group; And an internal voltage generator activator for outputting a control signal for activating a specific internal voltage generator of the first internal voltage generator group according to the output of the first active bank number determination unit. The method of claim 1, wherein the second internal voltage generator control unit comprises: a second active bank number determination unit identifying an activated bank among banks belonging to a second bank group; And a second internal voltage generator activator for outputting a control signal for activating a specific internal voltage generator of a second internal voltage generator group according to the output of the second active bank number determination unit. The apparatus of claim 1, wherein the first bank group and the second bank group include an equal number of banks. The apparatus of claim 1, wherein the first internal voltage generator control unit activates one internal voltage generator when one bank is activated. The apparatus of claim 1, wherein the first internal voltage generator control unit activates two internal voltage generators when two or more banks are activated. 3. The apparatus of claim 2, wherein the first active bank number determiner outputs a first driving enable signal having a high level when one bank is activated. 3. The apparatus of claim 2, wherein the first number of active banks determiner outputs first and second driving enable signals having a high level when two or more banks are activated. 4.

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