KR20080074652A - Semiconductor Chip Mounting Board - Google Patents

Abstract

A semiconductor chip mounting substrate is disclosed. The semiconductor chip mounting substrate may include a base substrate, a first metal pattern layer deposited and patterned on an upper surface of the base substrate, a first solder resist layer covering and protecting the first metal pattern layer, and a material deposited and patterned on a lower surface of the base substrate. A chip mounting region in which a semiconductor chip is mounted on a top surface including a second metal pattern layer, a second solder resist layer covering and protecting the second metal pattern layer, and a first metal pattern layer and a first solder resist layer is arranged in a plurality of columns and rows. Arranged, the mounting blocks formed by tying a row of chip mounting regions in a row in the direction in which the molding resin flows in the molding process, and the respective mounting blocks at the edge of the upper surface of the molding resin flows. And formed one by one, and formed smaller than the width of the mounting block and spaced apart from each other.

Description

Substrate mounting semiconductor chip

1 is a plan view of a semiconductor chip mounting substrate according to a first embodiment of the present invention.

FIG. 2 is an enlarged view illustrating an enlarged portion A of FIG. 1.

3 is a cross-sectional view taken along line II ′ of FIG. 2.

4 is a plan view of a semiconductor chip mounting substrate according to a second embodiment of the present invention.

The present invention relates to a semiconductor chip mounting substrate, and more particularly, to a semiconductor chip mounting substrate in which a mold gate, which is an inlet through which a molding resin flows, is formed for each unit to which a semiconductor chip is attached, thereby minimizing bending of the mounting substrate. will be.

In general, semiconductor chip mounting refers to a piece of semiconductor chip mounted on a lead frame and a mounting substrate, that is, a printed circuit board, in order to protect the semiconductor chips cut from the wafer from the external environment and to be packaged for mounting on other electronic devices. Means attaching semiconductor chips.

Recently, demands for high integration of semiconductor devices, increased memory capacities, multi-functions, and high-density packaging have been accelerated, and semiconductor packages in the form of ball grid array (BGA) have been developed to satisfy these requirements. The BGA type semiconductor package (hereinafter, referred to as a BGA semiconductor package) is a solder ball attached to a semiconductor chip on a flat printed circuit board and used as an external connection terminal on a lower surface of the printed circuit board. ) Is a semiconductor package attached to the form.

Since the external connection terminals are arranged on the lower surface of the printed circuit board, thickness and size can be reduced compared to the semiconductor package using the lead frame, so the size of the semiconductor package is almost the same as that of the semiconductor chip, and a large number of external connections are provided. Terminals can be formed.

In the BGA semiconductor package having the above-described characteristics, the printed circuit board to which the semiconductor chips are attached may have a flat plate shape and may have a size in which several to several dozen semiconductor chips may be mounted in parallel. The printed circuit board is a base substrate for supporting the semiconductor chips to be mounted, and to prevent bending due to its own weight or the weight of the mounted semiconductor chip, a metal pattern layer deposited on the upper and lower surfaces of the base substrate and patterned, respectively And a solder resist layer applied over the metal pattern layer to protect the metal pattern layer.

Chip mounting regions are provided on the upper surface of the printed circuit board configured as described above, and the chip mounting regions are arranged in a plurality of columns and rows. Each chip mounting region again includes a chip attaching portion, which is a region to which the semiconductor chip is attached, and bonding pads arranged outside the chip attaching portion or inside the chip attaching portion, and electrically connected to the semiconductor chip. Here, the bonding pads are formed on the metal pattern layer deposited on the upper surface of the base substrate, and the solder resist layer is opened at portions corresponding to the bonding pads so that the bonding pads are exposed to the outside of the solder resist layer.

In addition, a mold gate is formed at an edge of the upper surface of the printed circuit board (ie, a mold inflow edge) in which a molding resin flows in a subsequent process, that is, a molding process. The mold gate is formed by opening the solder resist layer to expose the metal pattern layer to the outside, and is formed along the mold inflow edge. Thus, the length of the mold gate is formed slightly smaller than the length of the mold inlet edge.

Meanwhile, ball lands to which solder balls used as external connection terminals are connected are formed on the bottom surface of the printed circuit board, and the ball lands and the bonding pads are electrically connected by circuit patterns and via holes. The ball lands are formed on the metal pattern layer deposited on the lower surface of the base substrate, and a solder resist layer is opened at a portion corresponding to the ball lands so that the ball lands are exposed to the outside of the solder resist layer.

However, after attaching the semiconductor chip to the chip attachment portion of the above-described printed circuit board, electrically connecting the bumps and bonding pads formed on the semiconductor chip, and molding the printed circuit board including the semiconductor chip to protect the semiconductor chip In the molding process of wrapping, a problem arises in that bending occurs due to a long mold gate.

In more detail, since the thermal expansion coefficients of the base substrate, the metal pattern layer and the solder resist layer constituting the printed circuit board are different from each other, the total area and distribution ratio of the metal pattern layer and the solder resist layer formed on the upper surface of the base substrate are different. If the total area and the ratio of the metal pattern layer and the solder resist layer formed on the lower surface of the base substrate are different from each other, the warpage of the printed circuit board becomes more severe in the molding process.

In order to minimize warpage generated in the molding process, the total area and distribution ratio of the metal pattern layer and the solder resist layer formed on the upper surface of the base substrate are the total area and distribution ratio of the metal pattern layer and solder resist layer formed on the lower surface of the base substrate. And should be as similar as possible to each other.

However, as described above, when the mold gate is formed long along the mold inflow edge and the solder resist layer is opened to expose the mold gate to the outside, the total area and distribution ratio of the metal pattern layers on the upper and lower surfaces of the base substrate. The total area and distribution ratio of the solder resist layer are greatly different, but warping occurs as described above.

SUMMARY OF THE INVENTION The present invention has been made in view of such a conventional problem, and an object of the present invention is to determine the distribution ratio of the metal pattern layer formed on the upper surface of the base substrate and the ratio of the solder resist layer, The present invention provides a semiconductor chip mounting substrate which minimizes warpage by matching the solder resist layer to about the same ratio.

The semiconductor chip mounting substrate for implementing the object of the present invention is a base substrate, a first metal pattern layer deposited and patterned on the upper surface of the base substrate, a first solder resist layer covering and protecting the first metal pattern layer A second metal pattern layer deposited and patterned on a lower surface of the base substrate, a second solder resist layer covering and protecting the second metal pattern layer, an upper portion including the first metal pattern layer and the first solder resist layer Chip mounting regions in which semiconductor chips are mounted on a surface are arranged in a plurality of columns and rows, and mounting blocks are formed by grouping a plurality of rows in which the chip mounting regions are arranged in a row in a direction in which a molding resin flows in a molding process. And one formed at the edge of the upper surface of the upper surface to correspond to each of the mounting blocks. It is formed smaller than the width includes a mold gate spaced apart from each other.

Hereinafter, a semiconductor chip mounting substrate according to exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Semiconductor Chip Mounting Board

Example  One

1 is a plan view of a semiconductor chip mounting substrate according to a first exemplary embodiment of the present invention, FIG. 2 is an enlarged view of an enlarged portion A of FIG. 1, and FIG. 3 is a cross-sectional view taken along line II ′ of FIG. 2. to be.

Referring to FIG. 1, a semiconductor chip mounting substrate 100 according to the present invention is a flat printed circuit board having a semiconductor chip (not shown) attached to an upper surface thereof and electrically connected to an attached semiconductor chip. Dozens of semiconductor chips have a size that can be mounted in parallel. Hereinafter, in this embodiment, the semiconductor chip mounting substrate is referred to as a printed circuit board.

Therefore, when the printed circuit board 100 is viewed in plan view, the chip mounting regions 110 are arranged in a plurality of columns and rows on the upper surface of the printed circuit board 100 as illustrated by a dotted line in FIG. 1.

Referring to FIG. 2, a chip attaching portion 112, which is a region where a semiconductor chip is attached, is provided at the center of each chip mounting region 110, and is spaced apart from an edge of the chip attaching portion 112. Outside, the bonding pads 122 are electrically connected to bumps of the semiconductor chip by conductive wires.

Although not shown, when the semiconductor chip is mounted in the chip mounting region by a flip chip bonding method directly connecting the bumps and the bonding pads of the semiconductor chip, the bonding pads are arranged inside the chip attaching portion, It is located in correspondence with the bumps.

In addition, as shown in FIG. 1, the upper side of the printed circuit board 100 may be formed at the edge of the upper surface of the printed circuit board 100 in which the molding resin flows in the molding process (hereinafter referred to as a mold inflow edge). The mold gates 124 are formed so that the molding resin can be smoothly supplied to the surface.

The mold gates 124 according to the present exemplary embodiment are formed in each column 110a in which the chip mounting regions 110 are arranged in a line in a direction in which the molding resin flows, and the length of each mold gate 124 is a chip. The mold gates 124 are formed to be smaller than the width of the mounting region 110 so that the mold gates 124 are spaced apart from the mold gates 124 adjacent to each other.

Meanwhile, ball lands 142 are arranged on the bottom surface of the printed circuit board 100 to correspond to each chip mounting area 110, and each ball land 142 is used as an external connection terminal in a semiconductor package manufacturing process. Solder balls are attached. The ball lands 142 are electrically connected to the bonding pads 122 formed on the printed circuit board 100 by connection lines and via holes.

As shown in FIG. 3, when the printed circuit board 100 is cut and viewed in cross section, the printed circuit board 100 includes a base substrate 102, a first metal pattern layer 120, and a first solder resist layer 130. The second metal pattern layer 140 and the second solder resist layer 150 are included.

The base substrate 102 is a flat plate having the same size and shape as the printed circuit board 100, becomes a center of the printed circuit board 100, and supports semiconductor chips mounted on the upper surface of the printed circuit board 100. The bending of the printed circuit board 100 may be prevented by the weight of the printed circuit board 100 or the weight of the semiconductor chip to be mounted.

The first metal pattern layer 120 and the first solder resist layer 130 are sequentially formed on the base substrate 102. The first metal pattern layer 120 is formed by layering a metal layer covering the entire upper surface of the base substrate 100 and patterning the deposited metal layer. The first metal pattern layer 120 may include bonding pads 122. And connection wirings and mold gates 124.

The first solder resist layer 130 covers and protects the remaining first metal pattern layer 120 except for the bonding pads 122 and the mold gates 124 of the first metal pattern layer 120.

The second metal pattern layer 140 and the second solder resist layer 150 are sequentially formed under the base substrate 102. The second metal pattern layer 140 is formed by depositing a metal layer covering the entire lower surface of the base substrate 102 and patterning the deposited metal layer. The second metal pattern layer 140 may include ball lands 142. And connection wirings.

As in the present embodiment, the mold gates 124 are formed one by one corresponding to each column 110a in which the chip mounting regions 110 are arranged in a line in the direction in which the molding resin flows, and each mold gate 124 is formed. If the length is smaller than the width of the chip mounting region 110, the area of the entire mold gate 124 may be reduced. As such, when the area of the mold gate 124 is reduced, the total area and the distribution ratio of the first metal pattern layer 120 and the first solder resist layer 130 disposed on the base substrate 102 may be determined. The total area and distribution ratio of the second metal pattern layer 140 and the second solder resist layer 150 disposed under the 102 may be approximately equally matched. Therefore, the bending of the printed circuit board 100 may be minimized in a process in which heat is applied, such as a molding process.

Example  2

4 is a plan view of a semiconductor chip mounting substrate according to a second embodiment of the present invention.

The semiconductor chip mounting substrate according to the second embodiment of the present invention has a structure and structure substantially the same as those of the semiconductor chip mounting substrate of the first embodiment described above except for the mold gate. Therefore, the same reference numerals and names are assigned to the same components, and only the mold gates different from those of the first embodiment will be described.

In the first embodiment, the mold gate 124 is formed corresponding to each row 110a in which the chip mounting regions 110 are arranged in a line in the direction in which the molding resin flows from the mold inflow edge. The columns 110a of the 110 are formed one by one in correspondence with at least two mounting blocks 110b. Referring to FIG. 4, the mounting block 110b is formed by tying four rows 110a of the chip mounting regions 110 into one.

The length of each mold gate 120 according to the present embodiment is formed to be smaller than the width of the mounting block 110b so that each mold gate 124 is spaced apart from the adjacent mold gate 124.

As in the present embodiment, when one mold gate 124 is formed corresponding to each mounting block 110b, and the length of each mold gate 124 is smaller than the width of the mounting block 110b, Embodiment 1 As can be reduced the area of the entire mold gate 124.

Although the present invention has been shown and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. And one of ordinary skill in the art that the present invention can be modified.

As described in detail above, if the mold gates are formed one by one in correspondence with the rows of the chip mounting regions, or one mold gate is formed in correspondence with two or more mounting blocks in which two or more rows of the chip mounting regions are formed, the mold gates are separated into a plurality of base substrates. The area and distribution ratio of the metal pattern layer and the solder resist layer disposed on the upper and lower surfaces of the base substrate are approximately the same, thereby minimizing the warpage of the printed circuit board.

Claims (4)

A base substrate; A first metal pattern layer deposited and patterned on an upper surface of the base substrate; A first solder resist layer covering and protecting the first metal pattern layer; A second metal pattern layer deposited and patterned on a bottom surface of the base substrate; A second solder resist layer covering and protecting the second metal pattern layer; A chip mounting region in which a semiconductor chip is mounted on an upper surface including the first metal pattern layer and the first solder resist layer is arranged in a plurality of columns and rows, and the chip mounting regions are formed in a direction in which a molding resin flows in a molding process. Mounting blocks formed by grouping rows arranged in a row as a selected number; And The semiconductor chip mounting substrate of the upper surface is formed one by one corresponding to each of the mounting blocks at the edge of the molding resin inflow, and formed smaller than the width of the mounting block and spaced apart from each other. The semiconductor chip mounting substrate according to claim 1, wherein the mounting block includes only one of the rows. The semiconductor chip mounting substrate of claim 1, wherein the mounting block comprises two or more rows. The semiconductor chip mounting substrate of claim 1, wherein the mold gates are formed by exposing the first metal pattern layer to the outside of the first solder resist layer.

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