KR20080067533A - Semiconductor package having flow-inducing grooves, laminated structure thereof and manufacturing method thereof - Google Patents

Abstract

A semiconductor package, a laminated structure thereof, and a manufacturing method thereof are disclosed. In a semiconductor package, the package substrate has slits and run-in guide grooves. The semiconductor chip is mounted on the package substrate. Wires electrically connect the semiconductor chip and the package substrate through the slits. An encapsulant is then formed in the slit to surround the wire and fills at least a portion of the runoff induction groove. Accordingly, by controlling the thickness of the encapsulant, the thickness of the semiconductor package can be reduced, and the stacking and connection reliability of the stacked semiconductor package can be improved.

Description

Semi-conductor package having an flowing guide groove and method of fabricating the same}

1 and 2 are cross-sectional views showing a conventional stacked semiconductor package structure;

3 is a plan view schematically showing a semiconductor package according to a first embodiment of the present invention;

4 is a cross-sectional view taken along line IV-IV 'of the semiconductor package of FIG. 3;

FIG. 5 is a cross-sectional view taken along line VV ′ of the semiconductor package of FIG. 3; FIG.

6 is a plan view schematically showing a semiconductor package according to a second embodiment of the present invention;

FIG. 7 is a cross-sectional view taken along line VII-VII ′ of the semiconductor package of FIG. 6; FIG.

8 is a plan view schematically showing a semiconductor package according to a third embodiment of the present invention; And

9 to 12 are cross-sectional views illustrating a method of manufacturing a semiconductor package according to an embodiment of the present invention.

<Description of main parts in the drawing>

104 ... shedding groove 106 ... semiconductor chip

108 Pad 110 ... Package Board

112 ... Adhesive member 114 ... Circuit pattern

115 ... Slit 116 ... Wire

118 Insulation layer 120 Encapsulant

The present invention relates to a structure of a semiconductor package and a method of manufacturing the same, and more particularly, to a structure of a semiconductor package having a wire ball grid array (WBGA) structure and a method of manufacturing the same.

In the assembly process of a typical WBGA semiconductor package, the semiconductor wafer is cut into unit semiconductor chips (wafer sawing step). Subsequently, the cut semiconductor chip is attached onto the package substrate (die attach step). Subsequently, the semiconductor chip and the package substrate are electrically connected using a wire (wire bonding step). Subsequently, a portion of the semiconductor chip, the wire and the package substrate are covered with an encapsulant (encapsulation step). Then, the solder ball is attached to the solder ball pad under the package substrate (solder ball attaching step).

1 and 2 are cross-sectional views illustrating a conventional stacked semiconductor chip package.

Referring to FIG. 1, the stacked semiconductor package 10 may include an upper semiconductor package and a lower semiconductor package of a WBGA type stacked up and down. By electrically connecting the solder balls 21 of the upper semiconductor package and the package substrate 15 of the lower semiconductor package, the upper semiconductor package and the lower semiconductor package may be electrically connected.

The upper and lower semiconductor packages can mount the semiconductor chips 12 and 22, and use the package substrates 15 and 25 having slits in the center as basic skeletons. The semiconductor chips 12 and 22 may be mounted on the package substrates 15 and 25 by using the adhesive members 13 and 23 so that pads (not shown) used as external terminals face the package substrates 15 and 25. have. The wires 14 and 24 may connect the package substrates 15 and 25 and the semiconductor chips 12 and 22 through slits. The pads and wires 14 and 24 of the semiconductor chips 12 and 22 exposed by the slit may be sealed by the encapsulant 16 and 26. Solder balls 11 and 21 may be attached to lower surfaces of the package substrates 15 and 25 so as to be connected to an external circuit device.

In addition, in the case of the upper semiconductor package, a molding material 27 may be further formed on the package substrate 25 and the semiconductor chip 22 to protect the semiconductor chip 22 from external impact and improve its reliability. have.

Referring to FIG. 2, the stacked semiconductor package 30 is similar to the stacked semiconductor package 10 of FIG. 1 except that the structure of the lower semiconductor package and the upper semiconductor package is the same. The semiconductor chips 32 and 42 may be mounted on the package substrates 35 and 45. The wires 14 and 44 may connect the package substrates 35 and 45 and the semiconductor chips 32 and 42 through slits. The pads and wires 34 and 44 of the semiconductor chips 32 and 42 exposed by the slits may be sealed by the encapsulants 36 and 46. The solder balls 31 and 41 may be attached to the lower surfaces of the package substrates 35 and 45. In addition, a protective plate 52 supported by the solder ball 51 may be further disposed on the upper semiconductor package to protect the semiconductor chip 42 from the outside.

However, in the above-described stacked semiconductor packages 10 and 30, the thickness of the encapsulant 16 and 26 is difficult to control and may interfere with the electrical connection of the upper and lower semiconductor packages. If the heights of the encapsulants 16, 26, 36, 46 are excessively high, the encapsulants 16, 26, 36, 46 are in contact with each other such that the solder balls 21, 41 and the package substrates 15, 35 are in contact with each other. Non-wet. Thus, the contact reliability of the upper and lower semiconductor packages can be greatly reduced.

The technical problem to be achieved by the present invention is to provide a semiconductor package which can increase the stacking reliability by controlling the thickness of the encapsulant.

Another technical problem to be achieved by the present invention is to provide a method of manufacturing a semiconductor package that can increase the stacking reliability by controlling the thickness of the encapsulant.

In the semiconductor package of one embodiment of the present invention for achieving the above technical problem, the package substrate has a slit and a falling guide groove. The semiconductor chip is mounted on the package substrate. Wires electrically connect the semiconductor chip and the package substrate through the slits. An encapsulant is then formed in the slit to surround the wire and fills at least a portion of the runoff induction groove.

The downflow guide groove may be arranged to surround a portion or a round of the slit.

The downflow guide grooves may be arranged in two or more pieces, and further, the steps of the plurality of downflow guide grooves may be the same.

In the stacked structure of a semiconductor package according to another aspect of the present invention for achieving the above technical problem, a plurality of the semiconductor package is stacked up and down.

Among the plurality of semiconductor packages, the size of the induction groove may be adjusted so that the encapsulant of the upper semiconductor package does not contact the lower semiconductor package.

The manufacturing method of the semiconductor package which concerns on one form of this invention for achieving the said another technical subject is provided. Slits are formed in the package substrate. A flow guide groove is formed in the lower surface of the package substrate. The semiconductor chip is mounted on an upper surface of the package substrate. The semiconductor chip and the package substrate are connected with a wire passing through the slit. Then, the slit is filled to surround the wire, and an encapsulant is formed to fill at least a portion of the downflow guide groove.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. In the accompanying drawings, the thicknesses of various layers and regions are highlighted for clarity.

3 is a plan view schematically illustrating a semiconductor package according to a first embodiment of the present invention. 4 is a cross-sectional view taken along line IV-IV 'of the semiconductor package of FIG. 3, and FIG. 5 is a cross-sectional view taken along line V-V ′ of the semiconductor package of FIG. 3.

3 to 5, the semiconductor package 100 may use a package substrate 110 having slits 115 formed therein as a basic skeleton material. For example, the package substrate 110 may refer to a printed circuit board (PCB). The package substrate 110 may include wiring patterns 114, and the wiring patterns 114 may be electrically separated by the insulating layer 118.

The package substrate 110 may include a flow down hole 104 disposed to surround a portion of the slit 115. For example, the downflow hole 104 may be symmetrically disposed near both ends of the slit 115. Preferably, the downflow hole 104 may be disposed near both ends of the slit 115 along the shape of the slit 115.

The semiconductor chip 106 may be mounted on the package substrate 110. The semiconductor chip 106 may have a pad 108 to be electrically connected to the package substrate 110. For example, the semiconductor chip 106 may be attached on the package substrate 110 by the adhesive member 112 so that the pad 108 may be exposed to the slit 115. The semiconductor chip 106 and the package substrate 110 may be electrically connected by a wire 108 extending through the slit 115. The solder ball 102 may be attached to the bottom of the package substrate 110 to be connected to the external circuit device.

Encapsulant 120 may fill slit 115 to surround and seal wire 108 and pad 108. Furthermore, the encapsulant 120 can be elongated to further fill at least a portion of the downflow guide groove 104. The thickness of the encapsulant 120 filled in the flow-inducing groove 104 may be smaller than the thickness of the encapsulant 120 filled in the slit 115. The flow-inducing groove 104 may prevent the encapsulant 120 filling the slit 115 from overflowing and stacking high on the package substrate 110.

This is because the encapsulant 120 can flow into the downflow guide groove 104. Therefore, the downflow guide groove 104 may reduce the thickness of the encapsulation material 120. When the depth of the downflow guide groove 104 is adjusted, the overall thickness of the encapsulation material 120 may be controlled. Thus, the downflow guide groove 104 may contribute to reducing the height of the encapsulant 120 and reducing the overall height of the semiconductor package 100.

The semiconductor package 100 of this embodiment may be used as the upper or lower semiconductor package of the stacked semiconductor package as described with reference to FIG. 1 or 2. For example, a plurality of semiconductor packages 100 of this embodiment may be stacked vertically to form a stacked semiconductor package. In such a stacked semiconductor package, the encapsulant 120 of the upper semiconductor package may be adjusted in size so that the encapsulant 120 does not come into contact with the lower semiconductor package. Accordingly, unlike the related art, the solder balls 102 of the upper semiconductor package may be reliably connected to the lower semiconductor package.

6 is a plan view schematically illustrating a semiconductor package according to a second exemplary embodiment of the present invention, and FIG. 7 is a cross-sectional view taken along line VII-VII ′ of the semiconductor package of FIG. 6. The semiconductor package according to this embodiment is similar to that of the shape of the downflow grooves in the semiconductor package of FIGS. 3 to 5. Thus, duplicate descriptions are omitted in both embodiments.

6 and 7, in the semiconductor package 300, a pair of downflow guide grooves 104a and 104b may be disposed in the package substrate 110 around the slit 115. Flowing guide grooves 104a and 104b may be arranged to surround a portion of the slit 115, such as both ends. At least a portion of the flow guide grooves 104a and 104b may be filled with the encapsulant 120. The flow-inducing grooves 104a and 104b may reduce the thickness of the encapsulant 120 at both ends of the slit 115 to prevent the encapsulant 120 from agglomerating or increasing its thickness. Steps of the flow-inducing grooves 104a and 104b may be the same, and the thickness of the encapsulant 120 may be sequentially reduced with respect to the slit 120.

In this embodiment, as the downflow guide grooves 104a and 104b are provided in two layers, the height of the encapsulant 120 may be lower than in FIGS. 1 to 3. Therefore, the height of the semiconductor package 300 is further reduced, and the stacking reliability of the stacked semiconductor package using the semiconductor package 300 may be further increased.

In a modified example of this embodiment, it is apparent that the number of the downfall grooves 104a and 104b is not limited to two, but may be provided in plural.

8 is a plan view schematically illustrating a semiconductor package according to a third exemplary embodiment of the present invention. The semiconductor package according to this embodiment is similar to that of the shape of the downflow grooves in the semiconductor package of FIGS. 3 to 5. Thus, duplicate descriptions are omitted in both embodiments.

Referring to FIG. 8, in the semiconductor package 500, the downflow guide groove 104c may be disposed to surround the slit 115. The flow-inducing groove 104c completely surrounds the slit 115 and the semiconductor substrate 106 so that the thickness of the encapsulant (see 120 in FIG. 4) at all positions can be uniformly maintained. In addition, since the overall space in which the encapsulant 120 may be filled has been increased, the thickness control of the encapsulant 120 may be easier by using the downflow guide groove 104c.

9 to 12 are cross-sectional views illustrating a method of manufacturing a semiconductor package in accordance with an embodiment of the present invention.

Referring to FIG. 9, the slit 115 is formed in the package substrate 110. For example, the slit 115 may be formed near the center of the package substrate 110. Subsequently, a portion of the package substrate 110 is etched to form a flow guide groove 104. For example, a hard mask (not shown) is formed on the upper surface of the package substrate 110, and a photoresist is formed on the hard mask. Subsequently, after removing the photoresist and the hard mask in the predetermined region, the downflow groove 104 may be formed by etching the package substrate 110 by dry or wet etching.

Preferably, the photoresist may be formed on the upper surface of the package substrate 110 on which the induction groove 104 is formed. When the package substrate 110 is etched, it is desirable to secure an etch selectivity so that the wiring pattern 104 and the insulating layer 118 therein are not etched. Accordingly, the downflow guide groove 104 may be formed to expose the wiring pattern 114.

Referring to FIG. 10, the package substrate 110 is further etched to form a slope on the sidewall of the downflow guide groove 104 in the direction of the slit 115. That is, the downflow guide groove 104 may be disposed obliquely in the direction of the slit 115 so that the encapsulant (see 120 of FIG. 12) flows well.

For example, since the sidewalls were etched damaged during the etching of the run-down induction groove 104, further etching may proceed to the front etch. In this case, since the etching speed of the sidewalls of the flow-inducing groove 104 which is etched in damage is faster than that of the other portions of the package substrate 110, a slope as shown in FIG. 10 may be formed. As another example, a method of forming and etching only the package substrate 110 region having a desired slope section by using a photoresist process may be performed. The etching process may use both dry and wet etching.

Referring to FIG. 11, the semiconductor chip 106 is mounted on the package substrate 110 using the adhesive member 112. Subsequently, the wire 116 is bonded through the slit 115 to electrically connect the semiconductor chip 106 and the package substrate 110. The wire 116 may be in physical contact with the pad 108 formed on the semiconductor chip 106 and the wiring pattern 114 of the package substrate 110.

Subsequently, the encapsulant 120 is filled in the slit 115 to completely enclose the wire 116 using the encapsulant mask 122. Preferably, the encapsulant mask 122 is used as a metal mask, and the encapsulant 120 may be formed by a printing method.

Referring to FIG. 12, the encapsulant mask 122 is removed. Accordingly, the encapsulant 120 flows down about the slit 115. At this time, the encapsulant 120 flowed down flows into the induction groove 104 to reduce the overall thickness of the encapsulant 120. If necessary, a curing process can be performed.

Thereafter, although not shown, the solder ball 102 may be additionally attached to the edge of the package substrate 110 as shown in FIG. 3. Furthermore, a stacked semiconductor package can be formed by stacking a plurality of completed semiconductor packages.

So far, the present invention has been described with reference to the drawings shown in the drawings, but the embodiments of the present invention are merely exemplary, and those skilled in the art may have various modifications and other equivalent implementations therefrom. It will be appreciated that examples are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, since the semiconductor package according to the present invention has the induction grooves flowing down the package substrate, the thickness control of the encapsulant can be facilitated. Accordingly, the overall height of the semiconductor package can be lowered.

Furthermore, when the semiconductor package according to the present invention is used as a stacked semiconductor package, the thickness of the encapsulant may be lowered to increase stacking and connection reliability of the upper and lower semiconductor packages.

Claims (15)

A package substrate having slits and downflow guide grooves; A semiconductor chip mounted on the package substrate; A wire electrically connecting the semiconductor chip and the package substrate through the slit; And And an encapsulant formed in the slit to surround the wire, the encapsulant filling at least a portion of the downflow guide groove. According to claim 1, And the flow-inducing groove is disposed to surround a portion of the slit. The method of claim 2, The flow-inducing groove is a semiconductor package, characterized in that arranged to surround both ends of the slit. According to claim 1, The flow-inducing groove is a semiconductor package, characterized in that arranged obliquely in the slit direction. According to claim 1, The flow-inducing groove is a semiconductor package, characterized in that arranged to surround the slit. According to claim 1, The flow-inducing groove is a semiconductor package, characterized in that arranged in at least two. The method of claim 6, And the steps of the plurality of falling guide grooves are the same. The laminated structure of the semiconductor package in which the semiconductor package of Claim 1 is laminated | stacked up and down in plurality. The method of claim 8, The stack structure of the semiconductor package, characterized in that the size of the flow guide groove is adjusted so that the encapsulant of the upper semiconductor package does not contact the lower semiconductor package of the plurality of semiconductor packages. Forming a slit inside the package substrate; Forming a flow guide groove in a lower surface of the package substrate; Mounting a semiconductor chip on an upper surface of the package substrate; Connecting the semiconductor chip and the package substrate with a wire passing through the slit; And Filling the slit to surround the wire and forming an encapsulant to fill at least a portion of the downflow guide groove. The method of claim 10, The flow-inducing groove is formed to surround part or all of the slit. The method of claim 10, The thickness of the encapsulant formed in the flow guide groove is smaller than the thickness of the encapsulant formed in the slit. The method of claim 10, The flow-inducing groove is formed by etching the package substrate, and the flow-inducing groove is further etched to be disposed obliquely in the slit direction. The method of claim 10, Forming the encapsulant is a manufacturing method of a semiconductor package, characterized in that using a printing method using a metal mask. The method of claim 10, Forming a solder ball on the upper surface of the package substrate further comprising the step of manufacturing a semiconductor package.

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