KR20080060653A - Method of inspecting thin film transistor array substrate and thin film pattern - Google Patents

Abstract

The present invention relates to a thin film transistor array substrate and a thin film pattern inspection method capable of accurately measuring and determining the degree of alignment between thin film patterns.

The thin film transistor array substrate according to the present invention includes thin film patterns formed on the display area of the substrate; An alignment inspection pattern formed in the non-display area of the substrate and used for alignment inspection of the thin film patterns, wherein the alignment inspection pattern includes:

A first inspection line and a second inspection line formed parallel to each other; First finger parts extending in the direction from the first test line to the second test line and having equal intervals; And second fingers extending in the direction of the first inspection line from the second inspection line and having equal intervals, and the first and second fingers are arranged side by side and alternately arranged at the same time.

Description

THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD FOR TESTING THIN FILM PATTERN}

1 is a plan view showing a conventional alignment inspection pattern.

2 is a plan view showing a thin film transistor array substrate according to the present invention.

3 is a cross-sectional view illustrating a thin film transistor formed on the thin film transistor array substrate of FIG. 2.

Figure 4 is a cross-sectional view showing an alignment inspection pattern according to the present invention.

FIG. 5 is a cross-sectional view taken along line II ′ of FIG. 4;

6 is experimental data of measuring the capacitance of the capacitor (C) of 5.

<Description of Symbols for Main Parts of Drawings>

10,110: Alignment inspection pattern

80,180: thin film transistor array substrate

15,115: first inspection line 19,119: second inspection line

11,111: first finger portion 13,113: second finger portion

106: thin film transistor 118: pixel electrode

108: gate electrode 102: gate line

The present invention relates to a liquid crystal display panel, and more particularly, to a thin film transistor array substrate and a method of inspecting a thin film pattern for accurately measuring and determining the degree of alignment between thin film patterns.

In today's information society, display elements are more important than ever as visual information transfer media. Cathode ray tubes or cathode ray tubes, which are currently mainstream, have problems with weight and volume. Many kinds of flat panel displays have been developed to overcome the limitations of the cathode ray tube.

The flat panel display device includes a liquid crystal display device (LCD), a field emission display (FED), a plasma display panel (PDP), and an electroluminescence (EL). Most of these are commercially available and commercially available.

Liquid crystal display devices can meet the trend of light and short and short of electronic products and mass production is improving, and are rapidly replacing cathode ray tubes in many applications.

In particular, an active matrix type liquid crystal display device that drives a liquid crystal cell using a thin film transistor (hereinafter referred to as "TFT") has the advantages of excellent image quality and low power consumption, and secures the latest mass production technology. As a result of research and development, it is rapidly developing into larger size and higher resolution.

Manufacturing process for manufacturing active matrix type liquid crystal display device includes substrate cleaning process, array substrate forming process, thin film pattern inspection process, substrate bonding process, scribing process, liquid crystal injection process, grinding process, mounting process, defective pixel It is divided into inspection process and repair process.

In the substrate cleaning process, foreign substances contaminated on the substrate surface of the liquid crystal display device are removed by the cleaning liquid.

In the array substrate forming process, the color filter array substrate is divided into a forming process and a thin film transistor array substrate forming process.

The inspection process of the thin film pattern is a process of confirming that the thin film patterns formed on the thin film transistor array substrate are normally formed.

In the liquid crystal injection process, the liquid crystal is injected into the liquid crystal display panel through the liquid crystal inlet, and then the liquid crystal inlet is sealed.

FIG. 1 is a diagram illustrating an alignment inspection pattern 10 in which an inspection process of a thin film pattern is used.

The alignment check pattern illustrated in FIG. 1 is formed in the non-display area of the thin film transistor array substrate.

The alignment inspection pattern 10 illustrated in FIG. 1 has a first inspection line 15 and a second inspection line 19 formed in parallel with each other, and a direction of the second inspection line 19 from the first inspection line 15. And first fingers 11 extending in the direction and second fingers 13 extending in the direction of the first inspection line 15 from the second inspection line 19. The first and second fingers 11 and 13 are disposed to face each other so that the first and second fingers 11a and 13 are positioned at the center of the first fingers 11a and among the second fingers 13a. The ends of the second finger portion 13a located at the center are designed to completely overlap each other (A).

Accordingly, the end of the first finger portion 11a positioned at the center of the first finger portions 11 and the end of the second finger portion 13a positioned at the center of the second finger portions 13a overlap. The degree of misalignment may be determined to determine the accuracy of alignment of the thin film patterns formed in the display area P1. That is, the error can be confirmed by discriminating the distance from 0 탆.

According to the degree of error, it is determined whether the thin film patterns formed in the display area of the thin film transistor array substrate are normally formed.

However, when the alignment of the conventional thin film pattern is discriminated, the degree of error is confirmed by directly checking through the microscope. As a result, there arises a problem that determination of the degree of error itself has another error, and as a result, the reliability of the alignment inspection process of the thin film pattern is degraded.

Accordingly, an object of the present invention is to provide a thin film transistor array substrate and a thin film pattern inspection method in which an alignment inspection pattern is formed to accurately measure and determine the degree of alignment between the thin film patterns.

In order to achieve the above object, the thin film transistor array substrate according to the present invention comprises a thin film pattern formed on the display area of the substrate; An alignment inspection pattern formed in the non-display area of the substrate and used to align the thin film patterns, wherein the alignment inspection pattern comprises: a first inspection line and a second inspection line parallel to each other; First finger parts extending in the direction from the first test line to the second test line and having equal intervals; And second fingers extending in the direction of the first inspection line from the second inspection line and having equal intervals, and the first and second fingers are arranged side by side and alternately arranged at the same time.

The alignment inspection pattern may further include a gate insulating layer and a protective layer positioned between the first finger portion and the second finger portion.

A capacitor is formed between the first finger portion and the second finger portion.

The thin film patterns formed in the display area may include a gate line and a data line formed to cross each other, a thin film transistor formed at an intersection of the gate line and the data line, and a pixel electrode connected to the thin film transistor.

The first test line and the first finger parts may be simultaneously formed of the same material as the gate line, and the second test line and the second finger parts may be simultaneously formed of the same material as the pixel electrode.

The present invention relates to a thin film pattern inspection method for inspecting alignment of thin film patterns formed in a display area of a substrate, wherein the first fingers have equal intervals and are equally spaced from each other and are parallel to the first fingers. And forming an alignment test pattern including second fingers parts alternately arranged in the same manner. Measuring the capacitance of the capacitor formed between the first and second fingers; And comparing the capacitance with a preset reference capacitance to determine the position at which the first and second finger portions are formed.

Determining the degree of alignment of the thin film patterns based on the positions at which the first and second fingers are formed; And correcting the process condition according to the comparison result of the capacitance and the preset reference capacitance.

The capacitance of the capacitor increases as the overlapping area between the first and second fingers increases.

As the distance between the first and second fingers increases, the capacitance of the capacitor is reduced.

Correcting the process condition according to the comparison result of the capacitance and the preset reference capacitance is characterized in that the process conditions are corrected so that the magnitude of the capacitance of the capacitor matches the magnitude of the reference capacitance.

Other objects and features of the present invention in addition to the above object will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 2 to 6.

2 is a plan view schematically illustrating a thin film transistor array substrate 180 according to an exemplary embodiment of the present invention.

The thin film transistor array substrate illustrated in FIG. 2 is divided into a display area P1 and a non-display area P1 surrounding the display area P1.

In the display area P1 of the thin film transistor array substrate 180, the thin film transistor 106 formed at the intersection of the gate line 102 and the data line 104, the gate line 102 and the data line 104 formed to cross each other. ) And a pixel electrode 118 connected to the thin film transistor 106.

3 is a cross-sectional view illustrating the thin film transistor 106 and the pixel electrode 118 in FIG. 2 in detail.

The thin film transistor 106 includes a gate electrode 108 connected to the gate line 102, a gate insulating film 144 formed to cover the gate electrode 108, and a semiconductor pattern 147 formed on the gate insulating film 144. And a source electrode 130 formed on the semiconductor pattern 147 and connected to the data line 104, and a drain electrode 132 facing the source electrode 130. The semiconductor pattern 147 may include an active layer 148 that forms a channel between the source electrode 130 and the drain electrode 132, and an ohmic contact layer for ohmic contact between the active layer 148 and the source and drain electrodes 130 and 132. 114).

The pixel electrode 118 is in contact with the drain electrode 132 of the thin film transistor 106 through the contact hole 151 passing through the passivation layer 150.

In the non-display area P2 of the thin film transistor array substrate 180, the gate pad 103 extended on the gate line 102, the data pad 105 extended on the data line 104, and the alignment check pattern 110 are provided. Is formed.

4 is a plan view specifically illustrating the alignment inspection pattern 110 in FIG. 2, and FIG. 5 is a cross-sectional view taken along line II ′ of FIG. 4.

The alignment inspection pattern 110 illustrated in FIG. 4 has a first inspection line 115 and a second inspection line 119 formed in parallel with each other, and a direction of the second inspection line 119 from the first inspection line 115. And first fingers 111 extending in the second direction and second fingers 113 extending in the direction of the first inspection line 115 from the second inspection line 119. The first and second finger parts 111 and 113 are alternately arranged in parallel with each other. The line widths D1 of the first and second finger parts 111 and 113 are equal to each other, and the distance D2 between the first finger parts 111 is the same as the distance D2 between the second finger parts 113. Do.

The first inspection line 115 and the first finger part 111 are simultaneously formed of the same material as the gate electrode 108 and the gate line 102 of the display area P1.

The second inspection line 119 and the second finger part 113 are simultaneously formed of the same material as the pixel electrode 118 of the display area P1.

Referring to FIG. 4, the first and second fingers 111 and 113 are formed to partially overlap each other. The gate insulating layer 144 and the passivation layer 150 are formed between the first and second fingers 111 and 113.

Accordingly, a capacitor C is formed between the first and second fingers 111 and 113. In this case, the capacitance of the capacitor C formed between the first and second fingers 111 and 113 is measured. The capacitance of the capacitor C formed between the first and second fingers 111 and 113 satisfies Equation 1 below.

C = ε × (A / d) (A: cross-sectional area of electrode, d: distance between electrodes, ε: dielectric constant)

It can be seen that the capacitance of the capacitor C is proportional to the cross-sectional area A of the electrode.

In addition, the total capacitance when the capacitors C are connected in parallel may be calculated by the sum of the capacitances of the capacitors C. FIG. Substantially the capacitance between one of the first and second fingers 111 and 113 is so small that the total of each capacitor C is measured.

By using the above principles, the total capacitance of the capacitors C formed between the first and second fingers 111 and 113 is measured, compared with the reference capacitance already set, and the display area P1 according to the comparison result. The degree of error of the thin film patterns such as the thin film transistor 106 can be determined.

For example, the cross-sectional area (A) of the electrode constituting the capacitor (B) becomes larger and the distance (d) becomes closer as the degree of overlapping each other between the first finger portion 111 and the second finger portion 113 increases. As it increases, the capacitance increases. On the contrary, when the degree of overlapping the first finger part 111 and the second finger part 113 becomes small or non-overlapping, the capacitance becomes small.

Using this principle, the capacitance value when the thin film patterns are formed in the right position is measured, and the error degree is determined using the measured capacitance, and in the later formation process, the process can be performed with the error corrected. .

As described above, in the inspection process of the thin film pattern according to the present invention, the degree of alignment of the thin film patterns formed in the display area can be accurately and precisely determined by using the capacitance rather than the conventional conventional error determination.

Accordingly, the reliability of the alignment inspection process of the thin film pattern can be improved.

6 is experimental data obtained by measuring the capacitance of the capacitor (C).

In FIG. 6, the X axis represents the degree of alignment between the electrodes facing each other, and the Y axis represents the capacitance of the capacitor C formed between the electrodes. The straight line E in Fig. 6 shows the ideal relationship of the capacitance values according to the alignment state between the electrodes.

In FIG. 6, when the alignment value on the X axis is “O” μm, the capacitance value on the Y axis is about 250 (fF). That is, when the capacitance value between the first and second fingers 111 and 113 is about 250 (fF), the alignment state between the first and second fingers 111 and 113 is determined to be “0” μm. When the alignment state is "0", the first and second finger parts 111 and 113 are formed at the correct position, which means that the thin film patterns are normally formed at the correct position in the display area P1.

In contrast, an increase in the value of the capacitance means that the area where the first and second fingers 111 and 113 overlap with each other is widened, and the alignment value of the X axis indicates the overlap width between the first and second fingers 111 and 113. it means.

The smaller value of the capacitance means that the first and second fingers 111 and 113 are separated from each other.

Thus, not only is the alignment value greater than " 0 " but also smaller means that it is further away from the home position.

The points in FIG. 6 represent values measured by actual experiments. The distribution of points reveals a slight error but the same pattern as curve E.

As a result of measuring the capacitance, the user corrects the process conditions so that the capacitance is not overlapped with the first and second fingers 111 and 113 when the capacitance value is greater than the reference value, and when the capacitance value is smaller than the reference value, the first value is measured. And the process conditions are corrected to narrow the distance between the second fingers 111 and 113.

That is, the process conditions such that the capacitance between the first and second fingers 111 and 113 match or close to the reference capacitance are corrected, and the first and second fingers 111 and 113 and the thin film patterns formed thereafter are corrected. It forms by process conditions.

As a result, the reliability of the alignment inspection process of the thin film pattern can be improved and the thin film patterns can be formed in place.

As described above, in the thin film transistor array substrate and the thin film pattern inspection method using the same, an alignment inspection pattern is formed on the thin film transistor array substrate, and the capacitance of the alignment inspection patterns is measured to freeze. It is determined whether the in-situ inspection patterns are formed in place. Then, the process conditions for forming the thin film pattern are corrected based on the measured capacitance value. Accordingly, the degree of alignment of the thin film patterns formed in the display area of the thin film transistor array substrate can be more accurately and precisely compared to conventional error determination, and the process deviation and the error can be corrected accurately.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. For example, although the technical concept of the present invention has been described with reference to the electrical inspection of the liquid crystal display panel in the embodiment, the same may also be applied to the electrical inspection of signal wires formed on the other flat panel display device. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (10)

Thin film patterns formed on the display area of the substrate; An alignment inspection pattern formed in the non-display area of the substrate and used for alignment inspection of the thin film patterns, The alignment inspection pattern, A first inspection line and a second inspection line formed parallel to each other; First finger parts extending in the direction from the first test line to the second test line and having equal intervals; Second fingers extending from the second inspection line in the direction of the first inspection line and having equal intervals with each other; The thin film transistor array substrate of claim 1, wherein the first and second fingers are arranged side by side and alternately arranged at the same time. The method of claim 1, The alignment inspection pattern, The thin film transistor array substrate of claim 1, further comprising a gate insulating layer and a passivation layer disposed between the first and second fingers. The method of claim 1, A thin film transistor array substrate, characterized in that a capacitor is formed between the first finger portion and the second finger portion. The method of claim 1, In the thin film patterns formed on the display area, A thin film transistor array substrate comprising: a gate line and a data line formed to cross each other, a thin film transistor formed at an intersection of the gate line and the data line, and a pixel electrode connected to the thin film transistor. The method of claim 4, wherein The first inspection line and the first finger parts are simultaneously formed of the same material as the gate line, The thin film transistor array substrate of claim 2, wherein the second test line and the second finger parts are formed of the same material as the pixel electrode. In the thin film pattern inspection method for inspecting the alignment degree of the thin film patterns formed in the display area of the substrate, Forming an alignment check pattern including first finger parts having equal intervals to each other and second finger parts having equal intervals to each other and parallel with the first finger parts, and alternately mean heat; Measuring the capacitance of the capacitor formed between the first and second fingers; And comparing the capacitance with a predetermined reference capacitance to determine the position at which the first and second finger parts are formed. The method of claim 6, Determining the degree of alignment of the thin film patterns based on the positions at which the first and second fingers are formed; And correcting process conditions according to a result of comparing the capacitance with a preset reference capacitance. The method of claim 7, wherein The method of claim 1, wherein the capacitance of the capacitor increases as the overlap region between the first and second fingers increases. The method of claim 7, wherein And the capacitance of the capacitor decreases as the distance between the first and second fingers increases. The method of claim 7, wherein Compensating the process conditions according to the comparison result of the capacitance and the preset reference capacitance The thin film pattern inspection method, characterized in that for correcting the process conditions to match the size of the capacitance of the capacitor to the size of the reference capacitance.

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