KR20080053596A - Liquid Crystal Display and Manufacturing Method Thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a method of manufacturing the same for preventing a channel short phenomenon of a thin film transistor caused by static electricity.

According to an exemplary embodiment of the present invention, a liquid crystal display includes a first thin film transistor configured to apply a high grayscale data signal input from a first data line to a first pixel electrode, and is connected to the first pixel electrode through a first contact hole, A second thin film including an upper electrode directly connected and applying a first storage capacitor to accumulate a high gray data signal and a low gray data signal input from a second data line to a second pixel electrode connected through a second contact hole; An upper electrode connected to the second pixel electrode through a transistor and a third contact hole, and a second storage capacitor configured to accumulate a low gradation data signal.

Description

Liquid crystal display and its manufacturing method {LIQUID DISPLAY DEVICE AND METHOD FOR MANUFACTURING THEREOF}

1 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention;

FIG. 2A illustrates a structure of a pixel of the liquid crystal display illustrated in FIG. 1;

FIG. 2B is a sectional view taken along line II ′ of the first storage capacitor shown in FIG. 2A; FIG.

3A to 3E are views for explaining a method of manufacturing a thin film transistor substrate of the liquid crystal display shown in FIG. 1, and

4 is a block diagram illustrating a liquid crystal display according to another exemplary embodiment of the present invention; and

FIG. 5 is a diagram illustrating a pixel structure of the liquid crystal display shown in FIG. 4.

 <Description of Symbols for Main Parts of Drawings>

110: liquid crystal panel 120: gate driver

130: data driver 140: timing controller

150: gamma voltage unit 152: high gray level gamma voltage unit

154: low gray gamma voltage unit 156: gamma voltage switch

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a method of manufacturing the same, which prevent a channel short phenomenon of a thin film transistor due to static electricity.

In general, a liquid crystal display device refers to a device that displays an image by driving liquid crystal molecules according to an electric field to adjust light transmittance. Since the liquid crystal display device displays light by transmitting light in a direction not shielded by the liquid crystal, the viewing angle is relatively narrower than that of other display devices.

As a representative wide viewing angle technology of the liquid crystal display, a vertical alignment mode is used. In the vertical alignment mode, liquid crystal molecules having negative dielectric anisotropy are vertically oriented and driven perpendicular to the electric field direction to adjust light transmittance. The vertical alignment mode technology is classified into a multi-domain vertical alignment (MVA) technology, a patterned-ITO vetical alignment (PVA) technology, and an S-patterned-ITO vetical alignment (S-PVA) technology according to a domain formation method.

MVA (Multi-domain Vertical Alignment) technology is a VA mode using protrusions, which form protrusions on the upper and lower plates to apply voltage in a state in which liquid crystal molecules form a pre-tilt symmetric with respect to the protrusions. Thereby forming a multi-domain by being driven in the pre-tilted direction.

PVA (Patterned-ITO Vetical Alignment) technology is a VA mode using a slit pattern, in which liquid crystal molecules are formed by forming a slit on the common electrode and the pixel electrode of the upper and lower plates and using a fringe electric field generated by the slit. Multi-domains are formed by being driven symmetrically with respect to the slits.

S-Patterned-ITO Vetical Alignment (S-PVA) technology divides one pixel into a high gray subpixel and a low gray subpixel representing data by different gamma curves, and divides each subpixel into It is driven independently through the gradation transistor and the low gradation transistor.

However, in the manufacturing process of the liquid crystal display using the S-PVA technology, there is a problem in that a short circuit of the channel due to static electricity, in particular, a channel of the high gradation transistor is shorted by the static electricity, resulting in a poor manufacturing yield of the liquid crystal display.

Accordingly, an object of the present invention is to provide a liquid crystal display device and a method for manufacturing the same, which directly remove a contact hole between the drain electrode and the high gray pixel electrode by directly connecting the drain electrode of the transistor for switching the high gray data signal to the upper electrode of the storage capacitor. To provide.

In order to achieve the above object, the liquid crystal display device of the present invention, the first thin film transistor for applying a first data signal voltage input from the first data line to the first pixel electrode; A first storage capacitor including a terminal electrode connected to the first pixel electrode through a first contact hole and directly connected to the first thin film transistor, and accumulating the first data signal voltage; A second thin film transistor configured to apply a second data signal voltage input from the second data line to a second pixel electrode connected through the second contact hole; And a second storage capacitor configured to be connected to the second pixel electrode through a third contact hole, and accumulate the second data signal voltage.

Here, the first data signal voltage and the second data signal voltage are preferably generated by different gray voltage curves.

The first thin film transistor may include a source electrode connected to the first data line and a drain electrode directly connected to the terminal electrode of the first storage capacitor.

The second thin film transistor may include a source electrode connected to the second data line and a drain electrode connected to the second pixel electrode.

Moreover, it is preferable that a said 1st storage capacity | capacitance is larger than a said 2nd storage capacity | capacitance.

The first thin film transistor may apply the first data signal voltage to the first pixel electrode for a predetermined period of one horizontal period, and the second thin film transistor may apply the second data signal voltage to a first period of the horizontal period. It is preferable to apply to the second pixel electrode for the remaining period.

In addition, the liquid crystal display of the present invention includes a data driver for applying a first data signal voltage to a first data line and a second data signal voltage to a second data line; A gate driver for applying a gate driving signal to the gate line; A first thin film transistor configured to apply the first data signal voltage to a first pixel electrode in response to the gate driving signal; A first storage capacitor connected to the first pixel electrode through a first contact hole and directly connected to the first thin film transistor to accumulate the first data signal voltage; A second thin film transistor configured to apply the second data signal voltage to a second pixel electrode connected through a second contact hole in response to the gate driving signal; And a second storage capacitor connected to the second pixel electrode through a third contact hole to accumulate the second data signal voltage.

The liquid crystal display of the present invention further includes a gamma voltage unit configured to supply a first gray gamma voltage for generating the first data signal voltage and a second gray gamma voltage for generating the second data signal voltage to the data driver. .

The liquid crystal display of the present invention is defined by a plurality of first data lines transferring a first data signal voltage, a plurality of second data lines transferring a second data signal voltage, and a plurality of gate lines transferring a gate driving signal. A liquid crystal display device comprising a plurality of pixels, the pixel comprising: a first pixel electrode configured to display the first data signal voltage; A first thin film transistor configured to apply the first data signal voltage to the first pixel electrode; A first storage capacitor connected to the first pixel electrode through a first contact hole and directly connected to the first thin film transistor, and configured to accumulate the first data signal voltage; A second pixel electrode displaying the second data signal voltage; A second thin film transistor connected to the second pixel electrode through a second contact hole and configured to apply the second data signal voltage to the second pixel electrode; And a second storage capacitor connected to the second pixel electrode through a third contact hole and accumulating the second data signal voltage.

Here, the first storage capacitor includes a first terminal electrode, a second terminal electrode connected to the first thin film transistor and the first pixel electrode, and an insulating film between the first terminal electrode and the second terminal electrode.

The second storage capacitor may include a third terminal electrode connected to the first terminal electrode, a fourth terminal electrode connected to the second pixel electrode, and an insulating film between the third terminal electrode and the fourth terminal electrode.

In addition, the second pixel electrode may be formed separately from the first pixel electrode and surround the first pixel electrode.

The liquid crystal display of the present invention includes: a first thin film transistor configured to apply a first data signal voltage input from a data line to a first pixel electrode in response to a first gate driving signal; A first storage capacitor including a terminal electrode connected to the first pixel electrode through a first contact hole and directly connected to the first thin film transistor, and accumulating the first data signal voltage; A second thin film transistor configured to apply a second data signal voltage input from the data line to a second pixel electrode connected through a second contact hole in response to a second gate driving signal; And a second storage capacitor configured to be connected to the second pixel electrode through a third contact hole, and accumulate the second data signal voltage.

The first gate driving signal and the second gate driving signal may be applied to the first and second thin film transistors sequentially during one horizontal period.

A liquid crystal display device manufacturing method of the present invention includes a gate line forming step of forming a gate line including a first gate electrode and a storage capacitor line including a first terminal electrode on a glass substrate; An active layer forming step of forming an active layer on the glass substrate on which the gate line and the storage capacitor line are formed, the active layer being overlapped with the first gate electrode; A first data line transferring a first data signal voltage, a first source electrode and a first drain electrode of a first transistor connected to the first data line, a second terminal electrode facing the first terminal electrode, and the first terminal A source / drain forming step of forming a source / drain pattern including a first drain line connecting a first drain electrode and the second terminal electrode; And forming a first contact hole to form an organic insulating layer on the glass substrate on which the source / drain pattern is formed, and to remove the formed organic interfacial layer to expose the second terminal electrode.

The forming of the gate line may include forming a gate line including a second gate electrode and a storage capacitor line including a third terminal electrode on a glass substrate, and the forming of the active layer may include forming the gate line. Forming an active layer overlapping the second gate electrode with a gate insulating layer interposed therebetween on a glass substrate on which a capacitor line is formed, wherein the source / drain forming step includes a second data line transferring a second data signal voltage; And a second source electrode and a second drain electrode of the second transistor connected to the second data line, a fourth terminal electrode facing the third terminal electrode, and a second drain line connected to the second drain electrode. And forming a source / drain pattern, wherein the forming of the contact hole removes a portion of the formed organic insulating layer, Forming a second contact hole exposing a second drain line connected to the lane electrode and a third contact hole exposing the fourth terminal electrode.

In addition, in the method of manufacturing a liquid crystal display of the present invention, transparent conductive patterning is performed on a first pixel electrode displaying a first data signal voltage and a second pixel electrode displaying the low gradation data signal on a glass substrate on which the contact hole is formed. The method further includes forming a pixel electrode.

The forming of the pixel electrode may include forming the first pixel electrode by connecting the first contact hole and connecting the second pixel electrode to the second contact hole and the third contact hole. .

In the forming of the gate line, the storage capacitor line may be formed such that the first terminal electrode has a larger area than the third terminal electrode. In the forming of the source / drain, the second terminal electrode may include the fourth terminal electrode. It is desirable to form the source / drain pattern to have a larger area.

According to an exemplary embodiment of the present invention, a method of manufacturing a liquid crystal display includes: forming a gate line including first and second gate electrodes and a storage capacitor line including first and second terminal electrodes on a glass substrate; An active layer forming step of forming an active layer on the glass substrate on which the gate line and the storage capacitor line are formed so as to overlap the first and second gate electrodes, respectively; First and second data lines transferring first and second data signal voltages, respectively, and a first source electrode and a first drain electrode of a first transistor connected to the first data line, and connected to the second data line, respectively. A second source electrode and a second drain electrode of the second transistor, third and fourth terminal electrodes facing the first and second terminal electrodes, and a drain line connecting the first drain electrode and the third terminal electrode; A source / drain formation step of forming a source / drain pattern comprising; An organic insulating layer is formed on the glass substrate on which the source / drain pattern is formed, and a portion of the organic interfacial layer is removed to expose the first contact hole exposing the third terminal electrode and the drain line connected to the second drain electrode. Forming a contact hole for exposing the second contact hole and the third contact hole to expose the fourth terminal electrode; And displaying a first data signal voltage on the glass substrate on which the contact hole is formed, displaying a first pixel electrode and the second data signal voltage connected to the first contact hole, and displaying the second contact hole and the third contact hole. And forming a second pixel electrode connected to the substrate by transparent conductive patterning.

Other objects and advantages of the present invention in addition to the above object will be apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

1 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention. As shown in FIG. 1, the liquid crystal display 100 according to an exemplary embodiment of the present invention may include a liquid crystal panel 110 and a gate driver 120 driving the gate lines GL1 and GL2 of the liquid crystal panel 110. ), The data driver 130 driving the data lines DL1 to DL4 of the liquid crystal panel 110, the timing controller 140 and the high gray gamma controlling the gate driver 120 and the data driver 130. And a gamma voltage unit 150 for selectively supplying a voltage and a low gray gamma voltage.

The liquid crystal panel 110 includes a plurality of pixels P1 to P4 defined by one gate line GL1 and GL2 and two data lines DL1 and DL2 and DL3 and DL4. One pixel P1 is disposed in each of the first pixel electrode VH, the second pixel electrode VL, the first pixel electrode VH, and the second pixel electrode VL formed in each of the low and high gray areas. The first thin film transistor T1 and the second thin film transistor T2, which are independently connected, and the gate line GL1 and the first thin film commonly connected to the first thin film transistor T1 and the second thin film transistor T2. Data lines DL1 and DL2 are connected to the transistor T1 and the second thin film transistor T2, respectively. Here, the first pixel electrode VH and the second pixel electrode VL formed in each of the low gray level region and the high gray level region represent data according to gray level voltages generated by different gray voltage curves Gamma-curve.

In the odd-numbered pixel P1 connected to the odd-numbered gate line GL1, the first thin film transistor T1 is connected to the first pixel electrode VH, and the second thin film transistor T2 is connected to the second pixel electrode ( The even-numbered pixel P2 connected to the odd-numbered gate line GL1 has a structure connected to the VL, and the first thin film transistor T3 is connected to the second pixel electrode VL, and the second thin film transistor T3 is connected. Has a structure connected to the first pixel electrode VH.

In the odd-numbered pixel P3 connected to the even-numbered gate line GL2, the first thin film transistor T5 is connected to the second pixel electrode VL, and the second thin film transistor T6 is connected to the first pixel electrode VH. In the even-numbered pixel P4 connected to the even-numbered gate line GL2, the first thin film transistor T7 is connected to the first pixel electrode VH, and the second thin film transistor T8 is connected to the even-numbered pixel P4. It has a structure connected to the second pixel electrode VL.

The timing controller 140 generates a gate control signal for controlling the gate driver 120 and a data control signal for controlling the data driver 130 by using a synchronization signal and a clock signal input from the outside, and inputs it from the outside. The data signal is rearranged and supplied to the data driver 130. In addition, the timing controller 140 generates a switching signal for controlling the gamma voltage unit 150. The switching signal controls the gamma voltage switch 156 to switch the output of the high gray gamma voltage unit 152 and the low gray gamma voltage unit 154 during one horizontal period.

The gamma voltage unit 150 includes a high gray gamma voltage unit 152 for generating a plurality of high gray gamma voltages, a low gray gamma voltage unit 154 for generating a plurality of low gray gamma voltages, and a high gray gamma voltage. And a gamma voltage switch 156 for switching the output of the unit 152 and the low gray gamma voltage unit 154. The gamma voltage switch 156 receives the high gray level gamma voltage from the high gray level gamma voltage unit 152 for the 1/2 horizontal period, and the low gray level gamma voltage from the low gray level gamma voltage unit 154 for the remaining 1/2 horizontal period. Is switched to supply to the data driver 130.

The gate driver 120 sequentially applies the gate driving signals to the gate lines GL1 and GL2 of the liquid crystal panel 110 in response to the gate control signal from the timing controller 140. Drive.

In response to the data control signal from the timing controller 140, the data driver 130 converts the data signal from the timing controller 140 into the high gray data signal using the high gray gamma voltage during the 1/2 horizontal period. Converts and supplies the data line to the data line DL1, converts the data signal from the timing controller 140 to the low gradation data signal using the low gray gamma voltage for the remaining 1/2 horizontal period, and supplies the data line to the data line DL2. do.

2A and 2B, the pixel structure of the liquid crystal display according to the exemplary embodiment of the present invention will be described in more detail. FIG. 2A is a plan view illustrating a pixel structure of the liquid crystal display of FIG. 1. As shown in Figure 2a. The pixel of the liquid crystal display according to the exemplary embodiment of the present invention includes a first pixel electrode 260, a second pixel electrode 262, a first thin film transistor T1, a second thin film transistor T2, and a gate line 210. ), A first data line 220, a second data line 225, a first storage capacitor CST1, and a second storage capacitor CST2.

The first pixel electrode 260 is connected to the drain electrode 254 of the first transistor T1 and the upper electrode 250 of the first storage capacitor CST1 through the contact hole 268. The first pixel electrode 260 receives the high gray data signal from the first data line 220 through the first transistor T1 to represent the high gray data signal.

The second pixel electrode 262 is separated from the first pixel electrode 260 and formed to surround the first pixel electrode 260. The second pixel electrode 262 is connected to the drain electrode 259 of the second transistor T2 through the contact hole 264, and the upper electrode of the second storage capacitor CST2 through the contact hole 266. 255). The second pixel electrode 262 receives the low gray level data signal from the second data line 225 through the second transistor T2 to represent the low gray level data signal.

The first thin film transistor T1 may include a gate electrode 212 connected to the gate line 210, a source electrode 222 connected to the first data line 220, and a drain electrode connected to the drain line 252. 254, and an active layer 230 overlapping the gate electrode 212 via an insulating layer. The first thin film transistor T1 receives the high gray level data signal supplied from the first data line 220 during the 1/2 horizontal period in response to the gate driving signal applied to the gate line 210 to drain electrode 254. Through the drain line 252.

The second thin film transistor T2 may include a gate electrode 214 connected to the gate line 210, a source electrode 227 connected to the second data line 225, and a drain electrode connected to the drain line 257. 259, an active layer 232 overlapping the gate electrode 214 via the insulating layer. The second thin film transistor T2 receives the high gray level data signal supplied from the second data line 225 for the remaining 1/2 horizontal period in response to the gate driving signal applied to the gate line 210, and drain electrode 259. It is applied to the drain line 257 through.

The gate line 210 is connected to the gate electrode 212 of the first thin film transistor T1 and the gate electrode 214 of the second thin film transistor T2. The gate line 210 applies a gate driving signal input from the gate driver to the gate electrode 212 of the first thin film transistor T1 and the gate electrode 214 of the second thin film transistor T2.

The first data line 220 is formed at one side of the pixel and is perpendicular to the gate line 210 to be connected to the source electrode 222 of the first thin film transistor T1. The first data line 220 applies a high grayscale data signal input from the data driver to the source electrode 222 of the first thin film transistor T1 during the 1/2 horizontal period.

The second data line 225 is formed on the other side of the pixel and is formed to cross the gate line 210 perpendicularly to the source electrode 227 of the second thin film transistor T2. The second data line 225 applies the low grayscale data signal input from the data driver to the source electrode 227 of the second thin film transistor T2 for the remaining 1/2 horizontal period.

The first storage capacitor CST1 includes a lower electrode 244 connected to the storage capacitor line 240, and an upper electrode 250 overlapping the lower electrode 244 through an insulating layer. The upper electrode 250 is connected to the drain electrode 254 of the first thin film transistor T1 through the drain line 252. The lower electrode 244 and the upper electrode 250 of the first storage capacitor CST1 preferably have a larger area than the lower electrode 242 and the upper electrode 255 of the second storage capacitor CST2.

The upper electrode 250 connected to the drain line 252 is connected to the first pixel electrode 260 through the contact hole 268. Therefore, the high gradation data signal input through the drain line 252 connected to the drain electrode 254 of the first thin film transistor T1 is applied to the first pixel electrode 260 and simultaneously applied to the first storage capacitor CST1. Can accumulate.

The second storage capacitor CST2 includes a lower electrode 242 connected to the storage capacitor line 240 and an upper electrode 255 overlapping the lower electrode 242 through an insulating layer. The upper electrode 255 is connected to the second pixel electrode 262 connected to the drain electrode 259 of the second thin film transistor T2 through the contact hole 266. Therefore, the low grayscale data signal input through the drain line 257 connected to the drain electrode 259 of the second thin film transistor T2 is applied to the second pixel electrode 262 and accumulated in the second storage capacitor CST2. Can be.

The first storage capacitor CST1 will be described in more detail. FIG. 2B is a sectional view taken along the line II ′ of the first storage capacitor of FIG. 2A. As illustrated in FIG. 2B, the first storage capacitor CST1 includes a lower electrode 244 formed on the glass substrate 202 and an upper electrode formed by overlapping the lower electrode 244 via the insulating layer 204. 250). The upper electrode 250 is connected to the drain electrode of the first thin film transistor through the drain line 252 and is connected to the first pixel electrode 260 through the contact hole 268 formed in the passivation layer 206.

In the liquid crystal display according to the exemplary embodiment, the drain electrode 254 of the first thin film transistor T1, the upper electrode 250 of the first storage capacitor CST1, and the first pixel electrode 260 are connected to each other. The second contact hole 264 and the second pixel electrode 262 and the second contact hole 268 for connecting the first contact hole 268, the drain electrode 259 of the second thin film transistor T2, and the second pixel electrode 262. And a third contact hole 266 for connecting the upper electrode 255 of the second storage capacitor CST2.

In other words, in the liquid crystal display according to the exemplary embodiment, a contact hole for connecting the first pixel electrode 260 and the upper electrode 255 of the first storage capacitor CST1 may be removed, and the first thin film may be removed. Since the drain electrode 254 of the transistor T1 is directly connected to the upper electrode 255 of the first storage capacitor CST1, static electricity flows into the first thin film transistor T1 during the manufacturing process of the liquid crystal display. The path is blocked and the generated static electricity is accumulated in the first storage capacitor CST1 before flowing into the first thin film transistor T1. Therefore, in the manufacturing process of the liquid crystal display, the short circuit of the channel caused by static electricity, in particular, the short circuit of the channel of the high gradation transistor by the static electricity can be solved.

In the present exemplary embodiment, the contact hole for connecting the first pixel electrode 260 and the upper electrode 255 of the first storage capacitor CST1 is removed, and the drain electrode 254 of the first thin film transistor T1 is directly connected. A structure connected to the upper electrode 255 of the first storage capacitor CST1 has been described, but is not limited thereto. The contact hole for connecting the second pixel electrode 262 and the second storage solution CST2 may be removed. The drain electrode 257 of the second thin film transistor T2 may be directly connected to the upper electrode 255 of the second storage electrode CST2.

Hereinafter, a method of manufacturing the thin film transistor substrate of the liquid crystal display of FIG. 1 will be described with reference to FIGS. 3A to 3E.

3A illustrates a gate line forming process. The gate line forming process forms a gate line 210 including gate electrodes 212 and 214 and a storage capacitor line 240 including lower electrodes 242 and 244 on a glass substrate. The storage capacitor line 240 is formed in parallel with the gate line 210. Specifically, a metal layer is deposited on the glass substrate by a method such as a sputtering method. The metal layer may have a single layer or a multilayer structure of molybdenum (Mo), aluminum (Al), chromium (Cr), and the like. The metal layer is patterned by a photolithography process and an etching process using a first mask to form the gate line 210 and the storage capacitor line 240. The metal layer patterning may be performed such that an area of the lower electrode 244 of the first storage capacitor CST1 is larger than an area of the lower electrode 242 of the second storage capacitor CST2.

3B shows an active layer forming process. The active layer forming process forms a gate insulating film on the glass substrate on which the gate line 210 and the storage capacitor line 240 are formed, and forms the active layers 230 and 232 on the gate electrodes 212 and 214 by using a second mask process thereon. . The active layers 230 and 232 may further include an ohmic contact layer. Specifically, the gate insulating film, the amorphous silicon layer, and the n ⁺ amorphous silicon layer are sequentially formed on the glass substrate subjected to the first mask process by a deposition method such as plasma enhanced chemical vapor deposition (PECVD). The active layers 230 and 232 are formed of an amorphous silicon layer and an n ⁺ amorphous silicon layer by a photolithography process and an etching process using a second mask. The gate insulating film is preferably an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx). In addition, the active layer may be formed at a portion where the gate line 210 and the data line cross or at a portion where the storage capacitor line 240 and the data line cross.

3C illustrates a source / drain pattern forming process. The source / drain pattern forming process forms a source / drain metal pattern on the gate insulating layer on which the active layers 230 and 232 are formed. The source / drain metal pattern includes the first data line 220, the source electrode 222 and the drain electrode 254 of the first thin film transistor, the upper electrode 250 of the first storage capacitor CST1, and the first thin film transistor ( A drain line 252, a second data line 225, and a source electrode of the second thin film transistor T2 connecting the drain electrode 254 of T1 and the upper electrode 250 of the first storage capacitor CST1. And a drain line 257 connected to the drain electrode 259, the upper electrode 255 of the second storage capacitor CST2, and the drain electrode 259 of the second thin film transistor T2.

The first data line 220 is connected to the source electrode 222 of the first thin film transistor T1, and the second data line 225 is connected to the source electrode 227 of the second thin film transistor T2. Meanwhile, the upper electrode 250 of the first storage capacitor CST1 is formed corresponding to the lower electrode 244 of the first storage capacitor CST1, and the upper electrode 255 of the second storage capacitor CST2 is second The lower electrode 242 of the storage capacitor CST2 is formed. Therefore, the area of the upper electrode 250 of the first storage capacitor CST1 is larger than the area of the upper electrode 255 of the second storage capacitor CST2.

Specifically, a source / drain metal layer is formed on the glass substrate that has undergone the second mask process by a sputtering method. The source / drain metal layer is patterned by a photolithography process and an etching process using a third mask. The ohmic contact layers exposed between the source electrodes 222 and 227 and the drain electrodes 254 and 259 are removed to separate the source electrodes 222 and 227 and the drain electrodes 254 and 259. Through this, the first thin film transistor T1 connected to the gate line 210 and the first data line 220 and the second thin film transistor T2 connected to the gate line 210 and the second data line 225 are formed. Is formed.

3D illustrates a contact hole forming process. In the contact hole forming process, the organic insulating film 206 is formed on the gate insulating film on which the source / drain metal pattern is formed, and a portion of the organic insulating film 206 is removed by a fourth mask process to thereby remove the first contact hole 268 and the second. The contact hole 264 and the third contact hole 266 are formed. The first contact hole 268 is used to connect the drain electrode 254 of the first thin film transistor T1, the upper electrode 250 of the first storage capacitor CST1, and the first pixel electrode to be formed in the next process. will be. The second contact hole 264 is for connecting the drain electrode 259 of the second thin film transistor T2 and the second pixel electrode to be formed in the next process. The third contact hole 266 is for connecting the second pixel electrode and the upper electrode 255 of the second storage capacitor CST2.

Specifically, an organic insulating layer 206 is formed by coating an organic insulating material such as an acrylic organic compound on a glass substrate subjected to a third mask process by spin coating, spinless coating, or the like. . The upper electrode 250 of the first storage capacitor CST1 and the drain electrode 259 of the second thin film transistor T2 are removed by removing a portion of the organic insulating layer 206 by a photolithography process and an etching process using a fourth mask. The first contact hole 268, the second contact hole 264, and the third contact hole 266 are exposed by exposing the distal end of the drain line 257 connected to the upper electrode 242 of the second storage capacitor CST2. To form.

3E illustrates a pixel electrode forming process. In the pixel electrode forming step, the first pixel electrode 260 and the second pixel electrode 262 of the transparent conductive pattern are formed on the organic insulating film. Specifically, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is coated on the glass substrate that has undergone the fourth mask process by a deposition method such as sputtering. The first pixel electrode 260 and the second pixel electrode 262 are formed by patterning the photolithography process and the etching process using the fifth mask.

In the pixel electrode forming process, the first pixel electrode 260 is connected to the upper electrode 250 of the first storage capacitor CST1 through the first contact hole 268. In addition, the second pixel electrode 262 is connected to the drain line 257 connected to the drain electrode 259 of the second thin film transistor T2 through the second contact hole 264, and opens the third contact hole 266. It is connected to the upper electrode 255 of the second storage capacitor (CST2) through.

The thin film transistor substrate manufactured by the above-described method may be assembled with a color filter substrate on which a common electrode and a color filter are formed, and may be used in a manufacturing process of a liquid crystal display.

4 is a block diagram illustrating a liquid crystal display according to another exemplary embodiment of the present invention. As illustrated in FIG. 4, the liquid crystal display 300 according to the exemplary embodiment of the present invention may include a liquid crystal panel 310 and a gate driver 320 driving the gate lines GL1 to GL4 of the liquid crystal panel 310. ), A data driver 330 for driving the data lines DL1 and DL2 of the liquid crystal panel 310, a timing controller 340 and a high gray gamma voltage for controlling the gate driver 320 and the data driver 330. And a gamma voltage unit 350 for selectively supplying the low gray level gamma voltage.

The liquid crystal panel 310 includes a plurality of pixels P1 to P4 defined by two gate lines GL1 and GL2 and GL3 and GL4 and one data line DL1 and DL2. One pixel P1 is disposed in each of the first pixel electrode VH, the second pixel electrode VL, the first pixel electrode VH, and the second pixel electrode VL formed in each of the low and high gray areas. The first thin film transistor T1 and the second thin film transistor T2, which are independently connected, and the data line DL1 and the first thin film commonly connected to the first thin film transistor T1 and the second thin film transistor T2. Gate lines GL1 and GL2 are respectively connected to the transistor T1 and the second thin film transistor T2. Here, the first pixel electrode VH and the second pixel electrode VL formed in each of the low gray level region and the high gray level region represent data according to gray level voltages generated by different gray voltage curves Gamma-curve.

The timing controller 340 generates a gate control signal and a data control signal, and switches the gamma voltage switch 356 to switch outputs of the high gray gamma voltage unit 352 and the low gray gamma voltage unit 354 during one horizontal period. ). The gamma voltage unit 350 receives the high gray level gamma voltage from the high gray level gamma voltage unit 352 during the 1/2 horizontal period, and the low gray level gamma from the low gray level gamma voltage unit 354 for the remaining 1/2 horizontal period. The voltage is switched and supplied to the data driver 330.

The gate driver 320 applies a gate driving signal to the gate line GL1 for 1/2 horizontal period time in response to the gate control signal from the timing controller 340 and the gate line (for the remaining 1/2 horizontal period time). The gate drive signal is sequentially applied to GL2).

In response to the data control signal from the timing controller 340, the data driver 330 converts the data signal from the timing controller 340 into the high gradation data signal using the high gradation gamma voltage for a 1/2 horizontal period. Converts and supplies the data line to the data line DL1, converts the data signal from the timing controller 340 to the low gradation data signal using the low gray gamma voltage for the remaining 1/2 horizontal period, and supplies it to the data line DL1. do.

Referring to FIG. 5, a structure of a pixel of a liquid crystal display according to another exemplary embodiment will be described in more detail. FIG. 5 is a plan view illustrating a pixel structure of the liquid crystal display illustrated in FIG. 4. As shown in FIG. 5. Pixels of the liquid crystal display according to another exemplary embodiment may include a first pixel electrode 460, a second pixel electrode 462, a first thin film transistor T1, a second thin film transistor T2, and a first gate line. 410, a second gate line 415, a data line 220, a first storage capacitor CST1, and a second storage capacitor CST2.

The first pixel electrode 460 is connected to the drain electrode 454 of the first transistor T1 and the upper electrode 450 of the first storage capacitor CST1 through the contact hole 468. The first pixel electrode 460 receives the high gray data signal from the data line 420 through the first transistor T1 to represent the high gray data signal.

The second pixel electrode 462 is separated from the first pixel electrode 460 to form a shape surrounding the first pixel electrode 460. The second pixel electrode 462 is connected to the drain electrode 459 of the second transistor T2 through the contact hole 464, and the upper electrode 455 of the second storage capacitor CST2 through the contact hole 466. ) The second pixel electrode 462 receives the low gray data signal from the data line 420 through the second transistor T2 to represent the low gray data signal.

The first thin film transistor T1 may include a gate electrode 412 connected to the first gate line 410, a source electrode 422 connected to the data line 520, and a drain electrode connected to the drain line 452. 454 and an active layer 430 overlapping the gate electrode 412 via an insulating layer. The first thin film transistor T1 receives the high gray level data signal supplied from the data line 420 during the 1/2 horizontal period in response to the gate driving signal applied to the first gate line 410 to drain the drain electrode 454. Through the drain line 452.

The second thin film transistor T2 may include a gate electrode 414 connected to the second gate line 415, a source electrode 427 connected to the data line 420, and a drain electrode connected to the drain line 457. 459 and an active layer 432 overlapping the gate electrode 414 via an insulating layer. The second thin film transistor T2 drains the high gray level data signal supplied from the data line 420 for the remaining 1/2 horizontal period in response to the gate driving signal applied to the second gate line 415. ) Is applied to the drain line 457 through the.

The first gate line 410 is connected to the gate electrode 412 of the first thin film transistor T1. The first gate line 410 applies a gate driving signal input from the gate driver to the gate electrode 412 of the first thin film transistor T1 during the 1/2 horizontal period.

The second gate line 415 is connected to the gate electrode 414 of the second thin film transistor T2. The second gate line 412 applies a gate driving signal input from the gate driver to the gate electrode 414 of the second thin film transistor T2 for the remaining 1/2 horizontal period.

The data line 520 is formed on one side of the pixel and is perpendicularly intersected with the first and second gate lines 410 and 412 so that the source electrode 422 and the second thin film transistor (T1) of the first thin film transistor T1 ( It is connected to the source electrode 427 of T2. The data line 420 applies a high gradation data signal input from the data driver for a half horizontal period to the source electrode 422 of the first thin film transistor T1 and the data driver for the remaining half horizontal period. A low gradation data signal input from the source is applied to the source electrode 427 of the first thin film transistor T2.

The first storage capacitor CST1 includes a lower electrode 444 connected to the storage capacitor line 440, and an upper electrode 450 overlapping the lower electrode 444 through an insulating layer. The upper electrode 450 is connected to the drain electrode 454 of the first thin film transistor T1 through the drain line 452. The lower electrode 444 and the upper electrode 450 of the first storage capacitor CST1 preferably have a larger area than the lower electrode 442 and the upper electrode 455 of the second storage capacitor CST2.

The upper electrode 450 connected to the drain line 452 is connected to the first pixel electrode 460 through the contact hole 468. Therefore, the high gradation data signal input through the drain line 452 connected to the drain electrode 454 of the first thin film transistor T1 is applied to the first pixel electrode 460 and accumulated in the first storage capacitor CST1. Can be.

The second storage capacitor CST2 includes a lower electrode 442 connected to the storage capacitor line 440, and an upper electrode 455 overlapping the lower electrode 442 through an insulating layer. The upper electrode 455 is connected to the second pixel electrode 462 connected to the drain electrode 459 of the second thin film transistor T2 through the contact hole 466. Therefore, the low grayscale data signal input through the drain line 457 connected to the drain electrode 459 of the second thin film transistor T2 is applied to the second pixel electrode 462 and accumulated in the second storage capacitor CST2. Can be.

In other words, in the liquid crystal display according to another exemplary embodiment, a contact hole for connecting the first pixel electrode 460 and the upper electrode 455 of the first storage capacitor CST1 may be removed, and the first thin film transistor may be used. Since the drain electrode 454 of the T1 is directly connected to the upper electrode 450 of the first storage capacitor CST1, static electricity flows into the first thin film transistor T1 during the manufacturing process of the liquid crystal display. The path is blocked and the generated static electricity is accumulated in the first storage capacitor CST1 before flowing into the first thin film transistor T1. Therefore, in the manufacturing process of the liquid crystal display, the short circuit of the channel caused by static electricity, in particular, the short circuit of the channel of the high gray transistor by the static electricity can be solved.

As described above, the liquid crystal display according to the present invention has a structure in which a contact hole between the drain electrode and the high gray pixel electrode is removed by directly connecting the drain electrode of the transistor for switching the high gray data signal to the upper electrode of the storage capacitor. Therefore, the short circuit of the channel of the thin film transistor for switching the high gradation data signal by the static electricity flowing into the contact hole is eliminated, thereby improving the yield.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (25)

A first thin film transistor configured to apply a first data signal voltage input from the first data line to the first pixel electrode; A first storage capacitor including a terminal electrode connected to the first pixel electrode through a first contact hole and directly connected to the first thin film transistor, and accumulating the first data signal voltage; A second thin film transistor configured to apply a second data signal voltage input from the second data line to a second pixel electrode connected through the second contact hole; And A second storage capacitor including a terminal electrode connected to the second pixel electrode through a third contact hole and accumulating the second data signal voltage; Liquid crystal display comprising a. According to claim 1, The first data signal voltage and the second data signal voltage are generated by different gray voltage curves. Liquid crystal display. The method of claim 2, wherein the first thin film transistor, A source electrode connected to the first data line and a drain electrode directly connected to the terminal electrode of the first storage capacitor. Liquid crystal display. The method of claim 3, wherein the second thin film transistor, A source electrode connected to the second data line and a drain electrode connected to the second pixel electrode; Liquid crystal display. The method of claim 4, wherein the first storage capacity, Greater than the second storage capacity Liquid crystal display. The method of claim 5, wherein the first thin film transistor, The first data signal voltage is applied to the first pixel electrode for a predetermined period of one horizontal period, and the second thin film transistor is configured to apply the second data signal voltage to the second pixel electrode for the remaining period of a certain period of one horizontal period. Authorized by Liquid crystal display. A data driver applying a first data signal voltage to the first data line and a second data signal voltage to the second data line; A gate driver for applying a gate driving signal to the gate line; A first thin film transistor configured to apply the first data signal voltage to a first pixel electrode in response to the gate driving signal; A first storage capacitor connected to the first pixel electrode through a first contact hole and directly connected to the first thin film transistor to accumulate the first data signal voltage; A second thin film transistor configured to apply the second data signal voltage to a second pixel electrode connected through a second contact hole in response to the gate driving signal; And A second storage capacitor connected to the second pixel electrode through a third contact hole to accumulate the second data signal voltage; Liquid crystal display comprising a. The method of claim 7, wherein The first data signal voltage and the second data signal voltage are generated by different gray voltage curves. Liquid crystal display. The method of claim 8, A gamma voltage unit configured to supply a first gray gamma voltage for generating the first data signal voltage and a second gray gamma voltage for generating the second data signal voltage to the data driver Liquid crystal display further comprising. The method of claim 9, wherein the data driver, Applying the first data signal voltage to the first thin film transistor for a predetermined period of one horizontal period, and applying the second data signal voltage to the second thin film transistor for the remaining period of a predetermined period of one horizontal period, The gate driver applies the gate driving signal to the first thin film transistor and the second thin film transistor for one horizontal period. Liquid crystal display. A plurality of pixels defined by a plurality of first data lines transferring a first data signal voltage, a plurality of second data lines transferring a second data signal voltage, and a plurality of gate lines transmitting a gate driving signal; As a liquid crystal display device, The pixel, A first pixel electrode displaying the first data signal voltage; A first thin film transistor configured to apply the first data signal voltage to the first pixel electrode; A first storage capacitor connected to the first pixel electrode through a first contact hole and directly connected to the first thin film transistor, and configured to accumulate the first data signal voltage; A second pixel electrode displaying the second data signal voltage; A second thin film transistor connected to the second pixel electrode through a second contact hole and configured to apply the second data signal voltage to the second pixel electrode; And A second storage capacitor connected to the second pixel electrode through a third contact hole and accumulating the second data signal voltage;  Liquid crystal display. The method of claim 11, The first data signal voltage and the second data signal voltage are generated by different gray voltage curves. Liquid crystal display. The method of claim 12, wherein the first storage capacity, And a first terminal electrode, a second terminal electrode connected to the first thin film transistor and the first pixel electrode, and an insulating film between the first terminal electrode and the second terminal electrode. Liquid crystal display. The method of claim 13, wherein the second storage capacity, A third terminal electrode connected to a first terminal electrode, a fourth terminal electrode connected to the second pixel electrode, and an insulating film between the third terminal electrode and the fourth terminal electrode; Liquid crystal display. The method of claim 14, wherein the first storage capacity, A first terminal electrode and a second terminal electrode each having a larger area than the third terminal electrode and the fourth terminal electrode of the second storage capacitor; Liquid crystal display. The method of claim 11, wherein the second pixel electrode, It is formed separately from the first pixel electrode, and is formed surrounding the first pixel electrode Liquid crystal display. Forming a gate line including a first gate electrode and a storage capacitor line including a first terminal electrode on a glass substrate; An active layer forming step of forming an active layer on the glass substrate on which the gate line and the storage capacitor line are formed, the active layer being overlapped with the first gate electrode; A first data line transferring a first data signal voltage, a first source electrode and a first drain electrode of a first transistor connected to the first data line, a second terminal electrode facing the first terminal electrode, and the first terminal A source / drain forming step of forming a source / drain pattern including a first drain line connecting a first drain electrode and the second terminal electrode; And Forming a first contact hole exposing the second terminal electrode by forming an organic insulating film on the glass substrate on which the source / drain pattern is formed, and removing the formed organic interfacial film; Liquid crystal display manufacturing method. The method of claim 14, The gate line forming step includes forming a gate line including a second gate electrode and a storage capacitor line including a third terminal electrode on a glass substrate; The forming of the active layer may include forming an active layer on the glass substrate on which the gate line and the storage capacitor line are formed to overlap the second gate electrode with a gate insulating layer interposed therebetween. The source / drain forming step may include a second data line for transmitting a second data signal voltage, a second source electrode, a second drain electrode, and a third terminal electrode of a second transistor connected to the second data line. Forming a source / drain pattern comprising a fourth terminal electrode and a second drain line connected to the second drain electrode, The forming of the contact hole may include removing a portion of the formed organic insulating layer to form a second contact hole exposing a second drain line connected to the second drain electrode and a third contact hole exposing the fourth terminal electrode. Containing Liquid crystal display manufacturing method. The method of claim 18, A pixel electrode forming step of forming a first pixel electrode displaying a first data signal voltage and a second pixel electrode displaying the low gradation data signal by transparent conductive patterning on the glass substrate on which the contact hole is formed Liquid crystal display device manufacturing method further comprising. 175. The method of claim 169, wherein forming the pixel electrode Forming the first pixel electrode by connecting the first pixel electrode to the first contact hole, and connecting the second pixel electrode to the second contact hole and the third contact hole. Liquid crystal display manufacturing method. The method of claim 20, In the gate line forming step, the storage capacitor line is formed such that the first terminal electrode has a larger area than the third terminal electrode. The source / drain forming step may include forming the source / drain pattern such that the second terminal electrode has a larger area than the fourth terminal electrode. Liquid crystal display manufacturing method. A gate line forming step of forming a gate line including first and second gate electrodes and a storage capacitor line including first and second terminal electrodes on a glass substrate; An active layer forming step of forming an active layer on the glass substrate on which the gate line and the storage capacitor line are formed so as to overlap the first and second gate electrodes, respectively; First and second data lines transferring first and second data signal voltages, respectively, and a first source electrode and a first drain electrode of a first transistor connected to the first data line, and connected to the second data line, respectively. A second source electrode and a second drain electrode of the second transistor, third and fourth terminal electrodes facing the first and second terminal electrodes, and a drain line connecting the first drain electrode and the third terminal electrode; A source / drain formation step of forming a source / drain pattern comprising; An organic insulating layer is formed on the glass substrate on which the source / drain pattern is formed, and a portion of the organic interfacial layer is removed to expose the first contact hole exposing the third terminal electrode and the drain line connected to the second drain electrode. Forming a contact hole for exposing the second contact hole and the third contact hole to expose the fourth terminal electrode; And A first data signal voltage is displayed on the glass substrate on which the contact hole is formed, and a first pixel electrode and the second data signal voltage connected to the first contact hole are displayed, and the second contact hole and the third contact hole are respectively displayed. A pixel electrode forming step of forming a second pixel electrode to be connected by transparent conductive patterning Liquid crystal display device manufacturing method comprising a. A first thin film transistor configured to apply a first data signal voltage input from the data line to the first pixel electrode in response to the first gate driving signal; A first storage capacitor including a terminal electrode connected to the first pixel electrode through a first contact hole and directly connected to the first thin film transistor, and accumulating the first data signal voltage; A second thin film transistor configured to apply a second data signal voltage input from the data line to a second pixel electrode connected through a second contact hole in response to a second gate driving signal; And A second storage capacitor including a terminal electrode connected to the second pixel electrode through a third contact hole and accumulating the second data signal voltage; Liquid crystal display comprising a. The method of claim 23, The first data signal voltage and the second data signal voltage are generated by different gray voltage curves. Liquid crystal display. The method of claim 24, The first gate driving signal and the second gate driving signal are sequentially applied to the first and second thin film transistors during one horizontal period time. Liquid crystal display.

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