KR20080048244A - Single transistor memory cell with auxiliary gate electrode and method for manufacturing same - Google Patents

Abstract

A single transistor memory cell having an auxiliary gate electrode and a method for fabricating the same are provided to improve a sustaining characteristic of data "0" by suppressing a band to band tunneling effect. A bulk region(55c) and an impurity region are formed on a semiconductor substrate(51). An active semiconductor pattern(55a) is isolated from the semiconductor substrate. A main gate electrode(73g) penetrates the impurity region in order to divide the impurity region into a source region(61s) and a drain region(61d). A first auxiliary gate electrode(73d) penetrates the drain region. A second auxiliary gate electrode(73s) penetrates the source region. A main gate insulating layer is inserted between the active semiconductor pattern and the main gate electrode. An auxiliary gate insulating layer is inserted between the active semiconductor pattern and the auxiliary gate electrode.

Description

Single transistor memory cell having an auxiliary gate electrode and method of fabricating the same

1 is a cross-sectional view of a conventional single transistor memory cell.

2 is a plan view illustrating a single transistor memory cell according to an embodiment of the present invention.

3 is a cross-sectional view taken along the line II ′ of FIG. 2.

4 is a cross-sectional view illustrating a method of programming a single transistor memory cell according to an embodiment of the present invention.

5 is a cross-sectional view illustrating a method of erasing a single transistor memory cell according to an embodiment of the present invention.

6 to 12 are cross-sectional views illustrating a method of manufacturing a single transistor memory cell according to an embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a single transistor memory cell having an auxiliary gate electrode and a method for manufacturing the same.

In general, the unit cell of the DRAM device includes one cell capacitor and one access transistor. The cell capacitor has a storage electrode electrically connected to any one of the source / drain regions of the access transistor, and the storage electrode is used as an electrode in which charges corresponding to data are stored. As the integration degree of the DRAM device increases, an area occupied by the storage electrode may decrease. Therefore, in order to implement a high performance and highly integrated DRAM device, the storage electrode must be formed in a three-dimensional form to increase the surface area of the storage electrode within a given plane. However, complex and difficult processes may be required to form a three-dimensional storage electrode.

Recently, a capacitor-less single transistor DRAM cell has been proposed. The single transistor DRAM cell was described in IEEE's 2005 Symposium on VLSI Technology Digest of Technical Papers, pp. 38-39 (2005). It is disclosed in an article by R. Ranica entitled "Scaled 1T-bulk devices built with CMOS 90nm technology for low-cost eDRAM applications." . 1 is a cross-sectional view of a single transistor DRAM cell disclosed in Ranica's paper.

Referring to FIG. 1, a deep n well 3 is provided in a semiconductor substrate 1, and a pocket p well 5 is provided in the deep n well 3. An isolation layer 7 is provided in a predetermined region of the pocket p well 5 to define an active region 5a formed of a portion of the pocket p well 5. The device isolation film 7 is provided to penetrate the pocket p well 5 to contact the deep n well 3. As a result, the active region 5a is surrounded by the device isolation layer 7 and the deep n well 3 to serve as an electrically floating bulk region.

Source regions 16s and drain regions 16d are respectively provided at both ends of the bulk region 5a, and a gate pattern 10 is disposed on the bulk region 5a between the source / drain regions 16s and 16d. ) Is placed. The gate pattern 10 includes a gate insulating layer 8 and a gate electrode 9 which are sequentially stacked. Spacers 13 may be provided on sidewalls of the gate pattern 10. The source region 16s may include a high concentration source region 15s spaced apart from the gate pattern 10, and a low concentration source region 11s extending from the high concentration source region 15s, and the drain region 16d. ) May include a high concentration drain region 15d spaced apart from the gate pattern 10, and a low concentration drain region 11d extending from the high concentration drain region 15d. The low concentration source / drain regions 11s and 11d may be located under the spacer 13.

According to Ranica, the source / drain regions 16s and 16d have a depth smaller than the thickness of the active region 5a, ie, the bulk region, as shown in FIG. Thus, the bulk region 5a may also exist under the source / drain regions 16s and 16d to have a maximized volume. As a result, the number of holes stored in the bulk region 5a during the program operation can be maximized to stabilize the data " 1 " state. However, if the source / drain regions 16s and 16d have large junction areas, the holes stored in the bulk region 5a may be lost after the program operation. Recombination with the electrons in the) can be extinguished in a short time. That is, the single transistor DRAM cell shown in FIG. 1 may exhibit poor data retention characteristics.

Furthermore, if the source / drain regions 16s and 16d have large junction areas, the junction capacitances Cs and Cd of the source / drain regions 16s and 16d also increase. In this case, the loading capacitance of the bit line electrically connected to the drain region 16d may be increased to decrease the operating speed of the single transistor DRAM cell and to reduce the data sensing margin.

The technical problem to be achieved by the present invention is to maximize the volume of the bulk region with the reduction of the junction area of the source / drain regions and to improve the data retention characteristics and to increase the data sensing margin and the method of fabricating a single transistor memory cell. To provide.

According to one aspect of the present invention, a single transistor memory cell having an auxiliary gate electrode is provided. The single transistor memory cell includes an active semiconductor pattern having a bulk region and an impurity region, which are sequentially stacked on a semiconductor substrate. The active semiconductor pattern is insulated from the semiconductor substrate. A main gate electrode is provided that penetrates the impurity region and divides the impurity region into source and drain regions spaced apart from each other. In addition, a first auxiliary gate electrode is provided to penetrate the drain region, and a second auxiliary gate electrode is provided to penetrate the source region.

According to another aspect of the present invention, a method of manufacturing a single transistor memory cell having an auxiliary gate electrode is provided. The method includes forming an active semiconductor pattern on a semiconductor substrate. The active semiconductor pattern is formed to have a bulk region and an impurity region stacked in turn, and the bulk region is insulated from the semiconductor substrate. A main recess region, a first auxiliary recess region, and a second auxiliary recess region penetrating the impurity region are formed. The main recess region is formed to divide the impurity region into a source region and a drain region spaced apart from each other, and the first and second auxiliary recess regions are formed to penetrate the drain region and the source region, respectively. A main gate electrode, a first auxiliary gate electrode, and a second auxiliary gate electrode are formed in the main recess region, the first auxiliary recess region, and the second auxiliary recess region, respectively.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the scope of the invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout.

2 is a plan view illustrating a single transistor memory cell according to an embodiment of the present invention, and FIG. 3 is a cross-sectional view taken along the line II ′ of FIG. 2.

2 and 3, a buried insulating film 53 is stacked on a semiconductor substrate 51, and an active semiconductor pattern 55a is provided on a portion of the buried insulating film 53. The semiconductor substrate 51 may correspond to a supporting substrate of a silicon on insulator (SOI) substrate. The active semiconductor pattern 55a may include a bulk region 55c and an impurity region, which are sequentially stacked, and sidewalls of the active semiconductor pattern 55a may be surrounded by the device isolation layer 57. The impurity region may have a different conductivity type from that of the bulk region 55c. For example, when the bulk region 55c is a p-type semiconductor, the impurity region may be an n-type semiconductor.

The main recess region 70b, the first auxiliary recess region 70c, and the second auxiliary recess region 70a are provided to penetrate the impurity region and extend into the bulk region 55c. The main recess region 70b divides the impurity region into source regions 61s and drain regions 61d spaced apart from each other, and the first and second auxiliary recess regions 70c and 70a are respectively It passes through the drain region 61d and the source region 61s. The inner wall of the main recess region 70b corresponds to the recess channel region.

The main recess region 70b may include a lower region 69b having a first width and an upper region VR2 having a second width smaller than the first width. Similarly, the first auxiliary recess region 70c may include a lower region 69c having the first width and an upper region VR3 having the second width, and the second auxiliary recess region 70a may include a lower region 69a having the first width and an upper region VR1 having the second width. In one embodiment of the present invention, the lower regions 69a, 69b, 69c may have a spherical sidewall as seen from the cross-sectional view of FIG. 3, and the upper regions VR1, VR2, VR3 are shown in FIG. 3. It can have vertical sidewalls as seen from the cross-sectional view of. As a result, the lower width of the drain region 61d between the main recess region 70b and the first auxiliary recess region 70c may be smaller than its upper width, and the main recess region 70b And the lower width of the source region 61s between the second auxiliary recess region 70a may be smaller than its upper width.

The main recess region 70b, the first auxiliary recess region 70c, and the second auxiliary recess region 70a may be a main gate electrode 73g, a first auxiliary gate electrode 73d, and a second auxiliary recess region 70a, respectively. The auxiliary gate electrode 73s may be filled. The gate electrodes 73g, 73d, and 73s are insulated from the active semiconductor pattern 55a by a gate insulating layer 71. That is, the gate insulating layer 71 may be interposed between the gate electrodes 73g, 73d and 73s and the inner walls of the recess regions 70b, 70c and 70a. The active semiconductor pattern 55a, the gate electrodes 73g, 73d, and 73s and the device isolation layer 57 may be covered with an insulating layer 75.

The bulk region 55c may include a lower bulk region 59 and an upper bulk region, and the lower bulk region 59 may have a higher impurity concentration than the upper bulk region. When the recess regions 70b, 70c, and 70a extend through the upper bulk region into the lower bulk region 59, the main recess region 70b and the first auxiliary recess region ( The upper bulk region between 70c may correspond to the first bulk region 55b ″, ie, the drain side bulk region, which is in contact with the bottom surface of the drain region 61d, and the main recess region 70b and the The upper bulk region between the second auxiliary recess regions 70a may correspond to a second bulk region 55b ', ie, a source side bulk region, which contacts the bottom surface of the source region 61s. The widths of the first and second bulk regions 55b 'and 55b "may be smaller than the top surface widths of the source / drain regions 61s and 61d.

A back gate interconnection 79b may be disposed on the insulating layer 75. The back gate wiring 79b fills the back gate contact hole 75b that penetrates the insulating layer 75, the device isolation layer 57, and the buried insulating layer 53. The semiconductor substrate 51 may be electrically connected to the semiconductor substrate 51 through a gate contact plug 77b.

4 is a cross-sectional view for describing a program operation of storing data “1” in a single transistor memory cell described with reference to FIGS. 2 and 3. It is assumed that the single transistor memory cell of FIGS. 2 and 3 is an n-channel MOS transistor cell for convenience of description.

4, a single transistor memory cell in accordance with an embodiment of the present invention can be programmed using a variety of methods. For example, the single transistor memory cell shown in FIGS. 2 and 3 applies a source voltage (V _SS ) of 0 volts to the source region 61s and a positive pulse waveform to the drain region 61d. It can be programmed by applying a first drain voltage (V _DD1 ) having a). While the first drain voltage V _DD1 is applied, a first main gate voltage V _GG1 may be applied to the main gate electrode 73g and a back gate having a negative voltage on the semiconductor substrate 51. A back gate voltage V _BB may be applied.

The first main gate voltage V _GG1 may be a voltage corresponding to about 1/2 of the first drain voltage V _DD1 . In this case, an ionization collision may occur at the junction between the drain region 61d and the first bulk region 55b ″ to generate a large amount of holes and electrons. It is injected into the bulk region 55c by an electric field between the drain region 61d and the bulk region 55c, and the electrons move toward the drain power source (not shown) connected to the drain region 61d. Since the bulk region 55c has an electrically isolated state, the holes are stored in the bulk region 55c, as a result, the threshold voltage of the single transistor memory cell of Fig. 4 is lower than the initial threshold voltage. This is because the holes (ie, excess holes) stored in the bulk region 55c lower the potential barrier between the bulk region 55c and the source region 61s.

In particular, when the back gate voltage V _BB is applied to the semiconductor substrate 51, most of the excess holes stored in the bulk region 55c are caused by an electric field due to the back gate voltage V _BB . It is stored in the lower region (ie, the lower bulk region 59) of the bulk region 55c. In addition, the junction areas AS and AD of the source / drain regions 61s and 61d may be formed by the wide lower regions (69a and 69b of FIG. 3) of the recess regions (70a, 70b and 70c of FIG. 3). And 69c) can be significantly reduced compared to the junction areas of the source / drain regions 16s and 16d of the conventional single transistor memory cell shown in FIG. Thus, even after the first drain voltage V _{DD1 changes} to 0 volts after the program operation, recombination between excess holes in the bulk region 55c and electrons in the source / drain regions 61s and 61d is achieved. Recombination paths can be significantly reduced to increase the holding time, i.e., retention time, of the excess holes in the bulk region 55c. That is, according to the present invention, that is, the retention characteristic of the data "1" can be improved.

In another embodiment, a negative voltage may be applied to at least one of the main gate electrode 73g and the first auxiliary gate electrode 73d during the program operation. That is, at least one of the first main gate voltage V _GG1 applied to the main gate electrode 73g and the first auxiliary gate voltage V _DG1 applied to the first auxiliary gate electrode 73d is negative. Voltage. In this case, holes may be induced in the drain side bulk region 55b ″ to cause band-to-band tunneling BTBT between the drain region 61d and the drain side bulk region 55b ″. Even when the band-to-band tunneling (BTBT) occurs, a large amount of excess holes are stored in the bulk region 55c. Accordingly, the program operation as described above can be achieved.

Furthermore, in the case where the bulk region 55c includes the lower bulk region 59 and the upper bulk region which are sequentially stacked as described above, the retention characteristic of the data "1" may be further improved. This is because most of the excess holes stored in the bulk region 55c can be stably stored in the lower bulk region 59 having a relatively higher impurity concentration than the upper bulk region without applying the back gate voltage. to be.

5 is a cross-sectional view for describing an erase operation of storing data “0” in a single transistor memory cell according to an embodiment of the present invention. Here, it is assumed that the single transistor memory cell is also an n-channel MOS transistor cell for convenience of description.

Referring to FIG. 5, a single transistor memory cell according to an embodiment of the present invention applies a source voltage (V _SS ) of 0 volt to the source region 61s and has a negative pulse waveform in the drain region 61d. It can be erased by applying the second drain voltage V _DD2 . The second drain voltage V _DD2 has a negative voltage (-V) during the erase time T, and the initial state before the erase time T and the holding state of the data "0" after the erase time T. Can have a voltage of zero volts. In addition, a specific voltage, for example, a voltage of 0 volt may be applied to at least one of the main gate electrode 73g and the first auxiliary gate electrode 73d during the erase operation. That is, at least one of a second main gate voltage V _GG2 applied to the main gate electrode 73g and a second auxiliary gate voltage V _DG2 applied to the first auxiliary gate electrode 73d during the erase operation. One can be zero volts and a specific voltage.

During the erase time T, holes in the bulk region 55c are injected into the drain region 61d to increase the threshold voltage of the single transistor memory cell of FIG. 5. Accordingly, the single transistor memory cell may have data corresponding to logic "0".

Subsequently, when the second drain voltage V _DD2 changes to a voltage of 0 volts after the erase time T, the surface potential of the bulk region 55c, that is, the channel region may change. . In other words, if the channel region has a first surface potential during the erase time T, after the erase time T, the channel region may have a second surface potential different from the first surface potential. In this case, the difference between the first and second surface potentials may vary depending on the size of the junction capacitances Cs 'and Cd' of the source / drain regions 61s and 61d. Specifically, as the source / drain junction capacitances Cs 'and Cd' decrease, the difference between the first and second surface potentials also decreases.

The source / drain junction capacitances Cs ', Cd' of a single MOS transistor according to the present invention are defined by the wide bottom regions (69a, 69b and 3b) of the recess regions (70a, 70b and 70c of FIG. 3). Due to the presence of 69c) it can be significantly smaller than the source / drain junction capacitances Cs and Cd of the conventional single transistor memory cell shown in FIG. Accordingly, after the conventional single transistor memory cell shown in FIG. 1 is erased using the same method as described with reference to FIG. 5, the channel region of the conventional single transistor memory cell is higher than the second surface potential. It can have three surface potentials. Here, it may be understood that the lower the surface potential of the channel region after the erasing operation is, the more the threshold voltage difference between the before and after the erasing operation increases. As a result, the threshold voltage difference between before and after the erase of the single transistor memory cell according to the present invention may be higher than the threshold voltage difference between before and after the erase of the conventional single transistor memory cell shown in FIG. 1. Thus, a single transistor memory cell according to the present invention may exhibit a larger sensing margin than the conventional single transistor memory cell shown in FIG.

Furthermore, after the erase operation, a specific voltage, for example, a voltage of 0 volts may be continuously applied to at least one of the main gate electrode 73g and the first auxiliary gate electrode 73d. In this case, the drain side bulk region 55b "may be fully depeleted or partially depeleted. Thus, even if a positive voltage is applied to the drain region 61d, The band-to-band tunneling phenomenon between the drain side bulk region 55b ″ and the drain region 61d can be significantly suppressed.

When band-to-band tunneling occurs at the junction of the drain region 61d after the erase operation, excess holes may be injected into the bulk region 55c to reprogram the single transistor memory cell of FIG. 5. However, according to this embodiment, the tunneling phenomenon of the erased single transistor memory cell can be suppressed as described above to improve the data retention characteristics of the erased single transistor memory cell. In particular, when the width of the drain side bulk region 55b ″ is reduced, the drain side bulk region 55b ″ may be completely depleted. In this case, band-to-band tunneling at the junction of the drain region 61d can be further suppressed.

Now, a method of manufacturing a single transistor memory cell according to an embodiment of the present invention will be described.

6 through 12 are cross-sectional views taken along line II ′ of FIG. 2 to explain a method of manufacturing a single transistor memory cell according to an embodiment of the present invention.

2 and 6, the SOH eye substrate 56 is prepared. The S-OI substrate 56 may include a support substrate 51, a buried insulating film 53 on the support substrate 51, and a semiconductor body layer 55 on the buried insulating film 53. The support substrate 51 may be a semiconductor substrate, and the semiconductor body layer 55 may be a p-type silicon layer.

2 and 7, an isolation region 57 is formed in a predetermined region of the semiconductor body layer 55 to form an active region 55r. The device isolation layer 57 may be formed to contact the buried insulation layer 53. As a result, the active region 55r may be surrounded by the device isolation layer 57 and the buried insulating layer 53 to be electrically insulated from the support substrate 51.

2 and 8, the impurity region 61 is formed by implanting first impurity ions onto the surface of the active region 55r. The impurity region 61 may be formed to have a different conductivity type from the active region 55r. For example, when the active region 55r is p-type, the impurity region 61 may be n-type. In addition, the lower bulk region 59 may be formed by implanting second impurity ions into the lower region of the active region 55r. The lower bulk region 59 defines an upper bulk region 55b between the lower bulk region 59 and the impurity region 61. The lower bulk region 59 may be formed to have the same conductivity type as the active region 55r. In this case, the lower bulk region 59 may have a higher impurity concentration than the upper bulk region 55b. The lower bulk region 59 and the upper bulk region 55b constitute a bulk region 55c. In addition, the bulk region 55c and the impurity region 61 constitute an active semiconductor pattern 55a. The process of forming the lower bulk region 59 may be omitted.

The active semiconductor pattern 55a may be formed using a method different from that described above. For example, before forming the device isolation layer 57, an impurity layer and a lower bulk layer are formed in the surface and the lower region of the semiconductor body layer 55, respectively, to form an upper bulk layer between the impurity layer and the lower bulk layer. It can be defined. Subsequently, the device isolation layer 57 may be formed in the impurity layer, the upper bulk layer, and the lower bulk layer to define the active semiconductor pattern 55a.

2 and 9, a mask pattern 66 is formed on a substrate having the active semiconductor pattern 55a. The mask pattern 66 may be formed to have a main opening 66b, a first auxiliary opening 66c, and a second auxiliary opening 66a crossing the upper portion of the active semiconductor pattern 55a. In this case, the main opening 66b may be located between the first and second auxiliary openings 66c and 66a. In addition, the mask pattern 66 may be formed to include at least two insulating layers. For example, the mask pattern 66 may be formed to include a pad oxide layer pattern 63 and a pad nitride layer pattern 65 that are sequentially stacked.

Using the mask pattern 66 as an etch mask, the active semiconductor pattern 55a is etched to penetrate the impurity region 61 and the main vertical recess region VR2 and the main vertical recess region VR2. First and second auxiliary vertical recessed regions VR3 and VR1 respectively positioned at both sides thereof are formed. Accordingly, the vertical recess regions VR1, VR2, and VR3 may be formed to have a depth greater than the thickness of the impurity region 61 and smaller than the overall thickness of the active semiconductor pattern 55a. As a result, the vertical recess regions VR1, VR2, and VR3 divide the impurity region 61 into a source region 61s and a drain region 61d spaced apart from each other. That is, the drain region 61d may be located between the main vertical recess region VR2 and the first auxiliary vertical recess region VR3, and the source region 61s is the main vertical recess region. It may be located between VR2 and the second auxiliary vertical recess area VR1.

2 and 10, spacers 67 are formed on sidewalls of the vertical recess regions VR1, VR2, VR3 using methods well known in the art. The spacers 67 may be formed of a material layer having an etch selectivity with respect to the active semiconductor pattern 55a of FIG. 8. For example, the spacers 67 may be formed of a silicon oxide film or a silicon nitride film. Isotropic etching of the bulk region 55c using the spacers 67 as etch masks results in the main vertical recess region VR2, the first auxiliary vertical recess region VR3, and the second auxiliary vertical. A main lower region 69b, a first auxiliary lower region 69c, and a second auxiliary lower region 69a are formed below the recess region VR1, respectively. Accordingly, a first bulk region 55b ″ consisting of a portion of the upper bulk region 55b may be defined between the main lower region 69b and the first auxiliary lower region 69c, and the main A second bulk region 55b ′ formed of another part of the upper bulk region 55b may be defined between the lower region 69b and the second auxiliary lower region 69a.

The source / drain regions 61s and 61d may also be partially isotropically etched while forming the lower regions 69a, 69b and 69c. In this case, the width BD of the first bulk region 55b ″ may be smaller than the upper surface width WD of the drain region 61d, and the width BS of the second bulk region 55b ′. ) May be smaller than the top surface width WS of the source region 61s, that is, the junction areas of the source / drain regions 61s and 61d may define the lower regions 69a, 69b, and 69c. By forming.

2 and 11, the spacers 67 are removed and gates are formed on inner walls of the lower regions 69a, 69b and 69c and the vertical recess regions VR1, VR2 and VR3. The insulating film 71 is formed. The lower regions (69a, 69b and 69c in FIG. 10), the vertical recess regions (VR1, VR2 and VR3 in FIG. 10) and the openings (in FIG. 10) are formed on a substrate having the gate insulating layer 67. A gate conductive film filling the 66a, 66b, and 66c is formed, and the gate conductive film is planarized to expose the top surface of the mask pattern 66. As a result, a main gate electrode 73g filling the main lower region 69b, the main vertical recess region VR2, and the main opening 66b is formed, and the first auxiliary lower region 69c and the A first auxiliary gate electrode 73d is formed to fill the first auxiliary vertical recess region VR3 and the first auxiliary opening 66c. In addition, a second auxiliary gate electrode 73s is formed to fill the second auxiliary lower region 69a, the second auxiliary vertical recess region VR1, and the second auxiliary opening 66a. The gate conductive film may be formed of a conductive film such as a doped polysilicon film.

2 and 12, the mask pattern 66 is removed. Next, an insulating layer 75 is formed on the substrate from which the mask pattern 66 is removed. The insulating layer 75, the device isolation layer 57, and the buried insulating layer 53 are patterned to form a rear gate contact hole 75b exposing a predetermined region of the support substrate 51. A back gate contact plug 77b is formed in the back gate contact hole 75b and a back gate wiring 79b covering the back gate contact plug 77b is formed.

As described above, according to the present invention, there is provided an active semiconductor pattern having a bulk region and an impurity region, which are sequentially stacked, and are disposed on both sides of the main gate electrode together with the main gate electrode adjacent to each other while penetrating the impurity region. First and second auxiliary gate electrodes are provided. Therefore, a drain region including the impurity region is defined between the main gate electrode and the first auxiliary gate electrode, and a source region including the impurity region is defined between the main gate electrode and the second auxiliary gate electrode. In addition, each of the main gate electrode and the auxiliary gate electrodes includes a lower region having a first width and an upper region smaller than the first width. Accordingly, the junction areas of the source / drain regions can be reduced to improve the retention characteristic of the excess charges (eg, excess holes) stored in the bulk region (ie, the retention characteristic of the data "1"). have.

Furthermore, if a constant voltage is continuously applied to at least one of the main gate electrode and the first auxiliary gate electrode after the erase operation is completed, even if a positive voltage due to noise or the like is applied to the drain region, The bulk region of may be fully depleted or partially depleted. As a result, band-to-band tunneling at the junction of the drain region is significantly suppressed, so that the retention characteristic of data "0" can be improved.

Claims (10)

An active semiconductor pattern comprising a bulk region and an impurity region, which are sequentially stacked on the semiconductor substrate, insulated from the semiconductor substrate; A main gate electrode penetrating the impurity region to divide the impurity region into source and drain regions spaced apart from each other; A first auxiliary gate electrode penetrating the drain region; And And a second auxiliary gate electrode penetrating the source region. The method of claim 1, A main gate insulating layer interposed between the active semiconductor pattern and the main gate electrode; And And a second gate insulating layer interposed between the active semiconductor pattern and the auxiliary gate electrodes. The method of claim 1, And a bottom surface width of the drain region is smaller than a width of the top surface of the drain region when viewed from a vertical cross sectional view parallel to a direction from the source region to the drain region. The method of claim 1, And the bottom surface width of the source region is smaller than the top surface width of the source region when viewed from a vertical cross sectional view parallel to the direction from the source region to the drain region. The method of claim 1, An insulating layer covering the semiconductor substrate, the active semiconductor pattern and the gate electrodes; And And a back gate interconnection disposed on the insulating film and electrically connected to the semiconductor substrate through a back gate contact hole penetrating through the insulating film. The method of claim 1, And the impurity region has a different conductivity type from the bulk region. An active semiconductor pattern is formed on the semiconductor substrate, the active semiconductor pattern is formed to have a bulk region and an impurity region stacked in turn, the bulk region is insulated from the semiconductor substrate, A main recess region, a first auxiliary recess region, and a second auxiliary recess region penetrating the impurity region, wherein the main recess region divides the impurity region into source and drain regions spaced apart from each other; The first and second auxiliary recess regions are formed to penetrate the drain region and the source region, respectively, Forming a main gate electrode, a first auxiliary gate electrode, and a second auxiliary gate electrode in the main recess region, the first auxiliary recess region, and the second auxiliary recess region, respectively. . The method of claim 7, wherein When viewed from a vertical cross sectional view parallel to the direction from the source region toward the drain region, each of the recess regions has a lower region having a first width and an upper region having a second width smaller than the first width; A method of manufacturing a single transistor memory cell formed. The method of claim 7, wherein And the impurity region is formed to have a different conductivity type from that of the bulk region. The method of claim 1, Forming an insulating film on a substrate having the main gate electrode, the first auxiliary gate electrode, and the second auxiliary gate electrode; Forming a back gate wiring on the insulating film, wherein the back gate wiring is electrically connected to the semiconductor substrate through a back gate contact hole penetrating the insulating film.

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