KR20080038535A - Manufacturing Method of Stacked Semiconductor Device - Google Patents

Abstract

In the method for manufacturing a stacked semiconductor device in which the thickness uniformity of the surface layer used as the channel silicon layer can be improved, a first substrate having a surface layer and a second substrate having a semiconductor structure are provided. An abrasive barrier layer comprising an oxide or nitride is formed under the surface layer, and a separation layer is formed under hydrogen polishing by using hydrogen ion implantation. After bonding the first substrate and the second substrate, the bulk layer of the first substrate is separated from the second substrate with the separation layer as the cut surface. The abrasive stop layer is exposed by chemical mechanical polishing to the bonded first substrate, and the surface stop layer is exposed by removing the abrasive stop layer. After the polishing stop layer is formed as described above, the polishing sacrificial layer may be completely removed using slurries having different polishing rates, thereby improving thickness uniformity of the surface layer subsequently used as the channel silicon layer.

Description

Method of manufacturing a stack type semiconductor device

1 to 6 are schematic cross-sectional views illustrating a method of manufacturing a stacked semiconductor device according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

10: first substrate 12: polishing stop layer

14 separation layer 16 surface layer

18: silicon layer 19: bulk layer

20: second substrate 22: gate pattern

22a: gate insulating film 22b: gate conductive film

24 source / drain 25 semiconductor structure

26 insulating film 30 opening

32: contact 34: oxide film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a stacked semiconductor device, and more particularly, a silicon on insulator manufactured by an ion-cut technique in which ions are imported and two substrates are bonded and separated. The manufacturing method of a stacked semiconductor device including manufacture of a board | substrate is called.

As semiconductor devices become highly integrated, leakage current in the junction region due to parasitic capacitance increases the power consumption of the device, which is an obstacle to manufacturing a semiconductor device requiring high-speed operation and low power.

In particular, as the channel length of the transistor, which occupies the largest portion of the semiconductor device, becomes smaller than 0.5 μm, the density of the substrate is increased, thereby increasing the junction capacitance and leakage current of the source / drain electrodes of the MOS transistor, thereby increasing the parasitic capacitance and leakage current. The use of SOI substrates has emerged to minimize the cost and to realize high-speed operation and low power of semiconductor devices.

The SOI substrate is formed by forming a silicon oxide film that functions as an insulating layer on a silicon substrate, forming a single crystal silicon layer thereon, and manufacturing a semiconductor device on the single crystal silicon layer. At this time, the SOI substrate is excellent in electrical characteristics, such as low voltage (<1V), low power and acceleration characteristics of the device, manufacturing a high-speed ULSI circuit (Ultra Large Scale Interated Circuit), manufacturing Gb-DRAM, radiation and high temperature It is used in circuits, MEMS, and solar cells.

Generally, the SOI substrate is manufactured by a Separation by IMplanted OXygen (hereinafter referred to as 'SIMOX') method and an ion-cut method. First, the SIMOX method implants oxygen atoms into a predetermined depth of a silicon substrate to allow oxygen atoms to penetrate into a predetermined depth of the substrate, and then performs an annealing process to form an SOI substrate.

When the SOI substrate is formed in the above manner, the trench is formed in the SOI substrate to fill the insulator to form the field region, and the base electrode of the MOS transistor is formed on the SOI substrate in the active region. In contact with the insulating film formed under the silicon film in the active region, there is almost no junction capacitance and leakage current under the junction. As a result, low power and high speed operation of the device can be realized, and insulation between the device and the device can also be achieved by using an insulating film disposed below.

The ion cutting method is a method of bonding and etching back substrates on which an insulating film is formed, and injecting hydrogen ions into a substrate on which a silicon oxide film is formed, adhering the substrate to another substrate at high temperature, and then separating the substrate using an ion implantation layer. Next, a technique for relieving surface roughness through high temperature heat treatment and chemical mechanical polishing is used. In the production of the SOI substrate, the ion cutting method has better wafer characteristics such as thickness uniformity and crystallinity than the SIMOX method, is compatible with existing semiconductor processes, and reuses donor substrates into which ions are implanted. The advantage is that you can.

However, when the SOI substrate is manufactured by using the ion cutting technique according to the prior art as described above, there is a difficulty in processing one of the bonded substrates to have a uniform surface layer. In detail, a method of directly polishing one side to a desired thickness in order to alleviate surface roughness may be applied at a thin film thickness of about 10 to 100 μm, but uniformity decreases rapidly when the thickness is reduced.

SUMMARY OF THE INVENTION An object of the present invention for solving the above problems is to provide a method for manufacturing a stacked semiconductor device including an SOI substrate capable of reducing the decrease in thickness uniformity of the surface layer exposed after direct chemical mechanical polishing of the interface of the bonded substrate. To provide.

In the method of manufacturing a stacked semiconductor device according to an embodiment of the present invention for achieving the above object, a first substrate having a surface layer and a second substrate having a semiconductor structure are provided. An abrasive stop layer comprising an oxide or nitride is formed under the surface layer. Under the polishing barrier layer, a separation layer is formed using hydrogen ion implantation. The first substrate and the second substrate are bonded to each other such that the surface layer contacts the semiconductor structure. The bulk layer of the first substrate is separated from the second substrate using the separation layer as a cut surface. The chemical mechanical polishing process is performed until the polishing stop layer of the bonded first substrate is exposed. The polishing stop layer is removed to expose the surface layer of the bonded first substrate.

Preferably, the polishing barrier layer is formed by injecting oxygen ions or nitrogen ions into the first substrate and then heat treating the first substrate. At this time, the heat treatment of the polishing stop layer is carried out at a temperature of 900 to 1300 ℃.

In addition, an oxide layer may be further formed on the second substrate before the bonding.

Here, the polishing stop layer is formed to a thickness of 50 to 5000 kPa. In addition, the separation layer is formed at an interval of 500 to 10000 kPa from the polishing barrier layer, and the surface layer has a thickness of 200 to 5000 kPa.

The chemical mechanical polishing process includes an amine compound to polish silicon and stop polishing on silicon oxide, includes silica, has a solid content of 0.01 to 20 wt%, and a basic pH of 8 to 12. A slurry having

In addition, the polishing stop layer is removed by etching or chemical mechanical polishing. In this case, when the polishing stop layer is removed through a chemical mechanical polishing process, a nonionic polymer compound is used to polish silicon oxide and stop polishing in silicon. And a slurry containing silica or ceria and having a solid content of 0.01 to 20 wt%.

As mentioned, according to the manufacturing method of the stacked semiconductor device of the present invention, by forming an abrasive stop layer containing an oxide or nitride under the surface layer of the first substrate used as the silicon donor before bonding the two substrates, After formation of the SOI substrate, the thickness of the surface layer to be used as the channel silicon layer can be easily adjusted through the polishing stop layer. In addition, after bonding the first substrate to the second substrate on which the semiconductor structure is formed, a step of exposing the polishing barrier layer step by step using slurry having different polishing rates and then completely removing the thickness of the exposed surface layer is performed. Uniformity can be improved.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be implemented in other forms. Rather, the embodiments introduced herein are provided to make the disclosure more complete and to fully convey the spirit and features of the invention to those skilled in the art. In the drawings, the thicknesses of the layers and regions are exaggerated for clarity. If it is also mentioned that the thin film is on another thin film or substrate, it may be formed directly on the other thin film or substrate or a third thin film may be interposed therebetween. In addition, in the preferred embodiment of the present invention as a stack-type semiconductor device will be described limited to the structure similar to SRAM, but is not limited to such as SOC (SiC On Silicon), SiC on glass, GaAs (or InP, GaN, It will be apparent to those skilled in the art that the present invention can be variously applied to SiC) on silicon and the like.

1 to 6 are schematic cross-sectional views illustrating a method of manufacturing a stacked semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1, a first substrate 10 having a surface layer 16 (FIG. 2) and a second substrate 20 on which a semiconductor structure 25 is formed are prepared. Here, examples of the first substrate 10 and the second substrate 20 include a silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, and the like. In addition, since the first substrate 10 may be formed as a channel layer formed on the stacked semiconductor device, the first substrate 10 may be obtained by performing selective epitaxial growth (SEG). It may include a thin film of a single crystal structure.

In addition, since the second substrate 20 is positioned below the structure of the stacked semiconductor device, it is preferable to use a single crystal silicon substrate as the second substrate 20.

Next, although not shown, a trench device isolation film is formed on the second substrate 20 as the device isolation film to define an active region and a field region. The reason why the trench isolation layer is formed as the isolation layer is that the integration degree is taken into consideration.

In addition, a semiconductor structure 25 such as a transistor including a gate pattern 22 and a source / drain 24 may be formed in an active region of the second substrate 20. In addition, the gate pattern 22 mainly includes a gate insulating layer 22a and a gate conductive layer 22b.

The gate pattern 22 may be formed in the following manner to form a semiconductor structure 25 such as a transistor including a source / drain 24.

An insulating film and a conductive film are formed on the second substrate 20. The gate pattern 22 is formed by patterning, such as a photolithography process. Specifically, after forming a photoresist pattern to partially expose the conductive film on the conductive film, etching is performed using the photoresist pattern as an etching mask. As a result, the conductive film exposed by the photoresist pattern and the insulating film positioned below it are removed. Then, the photoresist pattern is completely removed. Then, the gate pattern 22 including the gate insulating layer 22a and the gate conductive layer 22b is formed on the second substrate 20.

Then, ion implantation using the gate pattern 22 as a mask is performed. Then, an impurity doped source / drain 24 is formed under the surface of the second substrate 20 adjacent to the gate pattern 22. Here, examples of the impurities for forming the source / drain 24 include boron (B), phosphorus (P), arsenic (As), and the like. In the case of forming a double stack type SRAM as the stacked semiconductor device, phosphorus (P) and arsenic (As) are used as the impurities because an NMOS transistor is formed on a lower semiconductor substrate.

In addition, in another embodiment of the present invention, the source / drain may be formed in a lightly doped drain (LDD) structure. The source / drain of the LDD structure may be obtained by forming a spacer on the sidewall of the gate pattern and then further performing ion implantation to have a deep junction region.

In the embodiment of the present invention, the semiconductor structure 25 is limited to a transistor including the gate pattern 22 and the source / drain 24, but the semiconductor structure is based on a circuit design. It may further include.

Subsequently, an insulating film 26 is formed on the second substrate 20 having the semiconductor structure 25 including the gate pattern 22 and the transistors of the source / drain 24. It is preferable that the insulating film 26 contains an oxide. Therefore, examples of the insulating film include a borophosphor silicate glass (BPSG) thin film, a phosphor silicate glass (PSG) thin film, an undoped silicate glass thin film (USG), and a spin on glass thin film (SOG). Etc. can be mentioned.

In the exemplary embodiment of the present invention, the insulating film is patterned to form an insulating film pattern 28 having openings 30 exposing the surface of the substrate 10.

Selective epitaxial growth is then performed on each of the openings 30 to form a contact 32 that is sufficiently buried. The contact 32 preferably has a crystal structure substantially the same as that of the second substrate 20. Therefore, the contact 32 is preferably a single crystal silicon contact obtained by performing the selective epitaxial growth when the second substrate 20 is a single crystal silicon substrate.

An oxide film 34 is formed on the second substrate 20 on which the contact 32 and the insulating film 26 are formed. The oxide layer 34 is formed through a deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, or the like. The oxide film 34 becomes a buried oxide layer in the final SOI structure.

Referring to FIG. 2, an abrasive stop layer 12 including an oxide or nitride is formed under the surface layer 16 of the first substrate 10. First, oxygen ions or nitrogen ions are implanted into the first substrate 10. Then, the first substrate 10 is heat-treated to complete the polishing stop layer 12. Here, in the embodiment of the present invention, the heat treatment of the polishing stop layer 12 is performed at a temperature of 900 to 1300 ℃.

Accordingly, the polishing stop layer 12 including silicon oxide or silicon nitride is formed under the surface layer 16. At this time, the polishing stop layer 12 is formed to a thickness of 50 to 5000Å. As an example, the polishing stop layer 12 may be formed of silicon oxide having a thickness of about 1300 GPa.

Here, the polishing stop layer 12 is used as a primary polishing stop when performing a chemical mechanical polishing process for removing only the surface layer 16 of the first substrate 10 thereafter. Furthermore, the abrasive barrier layer 12 can be completely removed while minimizing damage to the underlying surface layer 16. Thus, the polishing stop layer 12 may be formed on the surface layer 16 to greatly reduce the surface roughness due to direct polishing to expose the surface layer.

In addition, the polishing stop layer 12 may be formed under the ion implantation depth from an upper surface of the first substrate 10 to limit the thickness of the surface layer 16 to be used as a channel layer below. At this time, in the embodiment of the present invention, the surface layer 16 is defined to have a thickness of 200 to 5000 kPa by the formation of the polishing barrier layer 12.

Here, the thickness of the polishing barrier layer 12 should be kept constant in order to improve the thickness uniformity of the surface layer 16. Therefore, when implanting the oxygen ions or nitrogen ions into the first substrate 10, the implantation depth is adjusted to be uniform.

In addition, hydrogen ions are implanted under the polishing barrier layer 12 to form a separation layer 14. In this case, the dose of hydrogen ions for forming the separation layer 14 is preferably 1 × 10 ¹⁶ to 1 × 10 ¹⁷ H particles / cm 2. In addition, the implantation depth of the hydrogen ions is preferably deeper than the implantation depth of the oxygen or nitrogen ions for forming the polishing stop layer 12.

In an embodiment of the present invention, the separation layer 14 is formed to have a distance of 500 to 10000 mm from the polishing stop layer 12. In addition, the separation layer 14 is formed to have a very thin thickness, and separation is performed to have a surface that becomes a hydrogen ion during a separation process performed after the bonding of the first substrate 10 and the second substrate 20. do.

Subsequently, the first substrate 10 and the second substrate 20 may perform a cleaning process for removing foreign matter adhered to the surface before bonding.

Referring to FIG. 3, the first substrate 10 and the second substrate 20 are bonded to each other so that the surface layer 16 of the first substrate 10 is positioned on the semiconductor structure 25. The bonding process is carried out through an alignment-direct bonding process.

Referring to FIG. 4, a bulk layer 19 of the first substrate 10 is formed by heat-treating the bonded first substrate 10 and the second substrate 20 to make the separation layer 14 a cut surface. ) Is separated from the second substrate 20. At this time, the heat treatment is preferably carried out at a temperature of 300 to 700 ℃. When the heat treatment temperature is less than 300 ° C., the separation process is difficult to perform, and when the heat treatment temperature exceeds 700 ° C., thermal burden may be applied to the devices formed on the second substrate 20. Because there is. As a result, the surface layer 16, the polishing barrier layer 12, and the silicon layer 18 are formed on the oxide film 34 of the second substrate 20. While the bulk layer 19 of the first substrate 10 is separated through the heat treatment process, the bond strength at the bonding interface between the surface layer 16 of the first substrate 10 and the second substrate 20 is increased. And defects due to the implantation of residual hydrogen ions and ions implanted into the first substrate 10 are removed.

However, after the separation process, the cut surfaces of the first substrate 10 and the second substrate 20 have surface roughness. Therefore, the process of subsequently flattening the cut surface can be performed.

In this case, the bulk layer 19 of the separated first substrate 10 may be reused by polishing the surface roughness of the cut surface.

Referring to FIG. 5, the silicon layer 18 of the bonded first substrate 10 is removed by chemical mechanical polishing until the polishing stop layer 12 is exposed.

At this time, in the embodiment of the present invention, in the chemical mechanical polishing process, it is preferable to use a first slurry including an amine compound to polish the silicon and stop polishing the silicon oxide. In addition, the first slurry includes silica, and the solid content is preferably 0.01 to 20 wt%, pH has a basicity of 8 to 12.

When the surface layer on the conventional bonded substrate is directly CMP, the surface unevenness of the cut surface is measured by a thickness of about 290 mm 3, which causes a problem that the surface uniformity at the cut surface is greatly reduced. However, when the polishing barrier layer 12 including the oxide or nitride of the present invention is used, the surface layer 16 under the polishing barrier layer 12 may be maintained at a constant thickness. In addition, the surface uniformity of the surface layer 16 may be maintained after the removal of the abrasive barrier layer 12.

Referring to FIG. 6, the polishing barrier layer 12 is removed to expose the surface layer 16 of the bonded first substrate 10. At this time, the polishing stop layer 12 is removed by dry etching, wet etching or chemical mechanical polishing. In this case, the removal process of the polishing barrier layer 12 is performed by a process capable of stopping the etching on the surface layer 16 made of silicon. A portion of the upper surface of the surface layer 16 may be removed by the removal process, as a result of which the surface layer 16 is formed to have a desired thickness and a flat top surface. Since the surface layer 16 has a thickness of 200 to 5000Å, the channel layer is formed to have a thickness equal to or smaller than the thickness of the surface layer 16.

Here, as an embodiment of the present invention, when the polishing stop layer 12 is removed through a chemical mechanical polishing process, a second slurry containing a nonionic polymer compound may be used to polish silicon oxide and stop polishing in silicon. It is preferable. The second slurry includes silica or ceria, and the solid content is preferably 0.01 to 20 wt%.

As such, the method of forming the abrasive barrier layer 12 on the surface layer 16 and removing the abrasive barrier layer 12 using slurries having different polishing selectivity may remove the existing surface layer 16. Compared with the case of direct chemical mechanical polishing so that the desired thickness remains, the surface roughness can be reduced and improved in terms of thickness uniformity.

In addition, since the thickness of the surface layer 16 is determined by the polishing stop layer 12, it is easy to control the thickness and thickness uniformity by adjusting the implantation depth of oxygen ions or nitrogen ions for forming the polishing stop layer 12. can do. Therefore, it is possible to manufacture a stacked semiconductor device including an SOI substrate having channel layers of various thicknesses up to several tens of micrometers.

According to the method of manufacturing a stacked semiconductor device of the present invention as described above, an SOI substrate is formed by forming an abrasive stop layer containing an oxide or nitride under the surface layer of a first substrate used as a silicon donor before bonding two substrates. After formation of the thickness of the surface layer to be used as the channel silicon layer can be easily adjusted through the polishing stop layer. In addition, after bonding the first substrate to the second substrate on which the semiconductor structure is formed, a step of exposing and completely removing the polishing stop layer by using slurry having different polishing selectivities may be performed. Thickness uniformity can be improved.

Therefore, the method of the present invention can be actively utilized in the manufacture of stacked semiconductor devices that require recent high integration.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (10)

Providing a first substrate having a surface layer and a second substrate having a semiconductor structure formed thereon; Forming an abrasive stop layer comprising an oxide or nitride under said surface layer; Forming a separation layer under the polishing stop layer by using hydrogen ion implantation; Bonding the first substrate and the second substrate such that the surface layer is in contact with the semiconductor structure; Separating the bulk layer of the first substrate from the second substrate using the separation layer as a cut surface; Performing a chemical mechanical polishing process until the polishing stop layer of the bonded first substrate is exposed; And Removing the polishing stop layer to expose the surface layer of the bonded first substrate. The method of claim 1, wherein the forming of the abrasive blocking layer comprises: Implanting oxygen ions or nitrogen ions into the first substrate; And And heat-treating the first substrate.  The method of claim 2, wherein the polishing stop layer is heat-treated at a temperature of 900 to 1300 ° C. The method of claim 1, further comprising forming an oxide film on the second substrate before the bonding. The method of manufacturing a stacked semiconductor device according to claim 1, wherein the polishing stop layer is formed to a thickness of 50 to 5000 GPa. The method of manufacturing a stacked semiconductor device according to claim 1, wherein the separation layer is formed at an interval of 500 to 10000 GPa from the polishing stop layer. The method of manufacturing a stacked semiconductor device according to claim 1, wherein the surface layer has a thickness of 200 to 5000 GPa. The chemical mechanical polishing process of claim 1, wherein the chemical mechanical polishing process comprises an amine compound, includes silica, polishes silicon and stops polishing on silicon oxide, and has a solid content of 0.01 to 20 wt%, a pH of A slurry having a basicity of 8 to 12 is used. The method of claim 1, wherein the polishing barrier layer is removed by etching or chemical mechanical polishing. 10. The method of claim 9, wherein the removal of the polishing barrier layer through a chemical mechanical polishing process comprises a nonionic polymer compound to polish the silicon oxide and stop polishing in silicon, and includes silica or ceria. And a slurry having a solid content of 0.01 to 20 wt%.

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