KR20080027158A - Semiconductor devices - Google Patents

Abstract

An object of the present invention is to improve the reliability of a semiconductor device having a structure in which a plurality of semiconductor chips having different planar dimensions are stored in the same sealing body in a state of being laminated with an adhesive insulating film.

In the semiconductor device 1A having a configuration in which a plurality of semiconductor chips 2M1, 2M2, and 2C having different plane dimensions are stored in the same sealing body 4 in a state of being laminated via the DAFs 5a to 5c, the control is performed. The thickness of the DAF 5c on the back of the top semiconductor chip 2C on which the circuit was formed was made thicker than that on each of the DAFs 5a, 5b on the back of the lower semiconductor chips 2M1, 2M2 on which the memory circuit was formed. Thereby, the defect which the bonding wire which connects the best semiconductor chip 2C and the wiring board 3 in contact with the main surface corner part of the lower semiconductor chip 2M2 can be reduced.

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device technology, and more particularly, to a technology effective for applying to a semiconductor device having a configuration in which a plurality of semiconductor chips having different plane dimensions are stacked in the same sealing body.

There exists a semiconductor device which accommodates a memory chip semiconductor chip and a control circuit semiconductor chip which controls the operation in one sealing body, and builds a desired system.

In the semiconductor device of this configuration, the semiconductor device can be miniaturized by being mounted on the wiring board in a state in which the semiconductor chip for the memory circuit and the semiconductor chip for the control circuit are stacked. In this case, in general, the semiconductor chip for the memory circuit has a larger plane dimension than the semiconductor chip for the control circuit from the viewpoint of increasing the storage capacity, and thus the semiconductor chip for the control circuit is laminated on the memory chip.

The semiconductor chip for a lower memory circuit is mounted on a wiring board via a die attach film (hereinafter abbreviated as DAF). The electrode of this semiconductor chip for memory circuits is electrically connected to the electrode of a wiring board via a bonding wire. The upper semiconductor chip for control circuit is mounted on the semiconductor chip for memory circuit via DAF. The electrode of this semiconductor chip for control circuits is electrically connected to the electrode of a wiring board via a bonding wire.

About this kind of semiconductor device, it is described in Unexamined-Japanese-Patent No. 2004-146645 (patent document 1), for example. 21 and 22 of Patent Document 1 disclose a technique of stacking a plurality of semiconductor chips via DAF.

[Patent Document 1] Japanese Unexamined Patent Application Publication No. 2004-146645 (Figures 21 and 22, etc.)

However, the present inventors found that there are the following problems in the semiconductor device.

Since the planar dimension of the upper control circuit semiconductor chip is smaller than the planar dimension of the lower memory circuit semiconductor chip, the electrode of the control circuit semiconductor chip and the electrode of the wiring board are positively bonded. When the electrical bonding is performed via the bonding wire by the method of using the first bonding point and the wiring board side as the second bonding point, the bonding wire may come into contact with the upper peripheral edge of the lower surface semiconductor chip for memory circuit. . Also in the semiconductor device disclosed in Patent Document 1, it is not possible to avoid the problem that a part of the bonding wire is in contact with a part of the lower semiconductor chip by simply stacking the semiconductor chip through the DAF.

Here, if the semiconductor chip for control circuits is arrange | positioned as close as possible to the outer periphery of the semiconductor chip for memory circuits, the problem that the said bonding wire contacts the semiconductor chip for memory circuits can be avoided. However, the bonding itself of a bonding wire becomes difficult for the following reasons. The first reason is that, for example, when the semiconductor chip for the control circuit is close to the outer circumference of the semiconductor chip for the memory circuit, the loop of the bonding wire becomes high. The reason for this is as shown in Figs. 19 to 21, and the formation of the bonding wire 50 is determined by the distance DA between the electrode 52 of the semiconductor chip 51C and the electrode 54 of the wiring board 53. After the bonding wire 50 of length DB corresponding to) is taken out from the capillary 55 on the electrode 52 of the semiconductor chip 51C, the capillary 55 is moved to draw a locus. It moves toward the electrode 54 of the wiring board 53. Thereafter, the capillary 55 slides on the surface of the electrode 54 of the wiring board 53, and the bonding wire 50 is connected to the electrode 54 of the wiring board 53. That is, as shown in Fig. 21, when the control circuit semiconductor chip 51C is close to the outer circumference of the memory circuit semiconductor chip 51M, the electrode 52 of the semiconductor chip 51C and the wiring board 53 are separated. Since the distance from the electrode 54 is close, the bonding wire 50 drawn out at the first bonding point is shortened to the second bonding point in a state where the length of the bonding wire 50 is short. The possibility of contacting not only the memory chip semiconductor chip 51M disposed at the lower end but also the upper peripheral portion of the control circuit semiconductor chip 51C is increased. Therefore, in order to avoid contact with the periphery of each semiconductor chip 51C, 51M, what is necessary is just to pull out the bonding wire 50 in a 1st bonding point, but with this, a loop becomes high. Then, a part of the loop is visible or exposed through the seal. The second reason is that, for example, when the semiconductor chip for the control circuit is too close to the outer circumference of the semiconductor chip for the memory circuit, the falling trajectory from the first junction portion to the second junction portion of the bonding wire becomes excessively steep. Since joining becomes difficult, the loop shape of a wire becomes difficult to stabilize. The third reason is that, for example, the closer the control circuit semiconductor chip is to the outer periphery of the memory circuit semiconductor chip, the sharper the incidence angle of the bonding wire when viewed in plan view. That is, since the bonding wires are formed in a direction substantially parallel to one side where the electrode of the semiconductor chip as the target is provided, the distance between adjacent bonding wires becomes narrow, and short circuit defects between bonding wires easily occur.

On the other hand, when the bonding method of the said bonding wire is made into the reverse bonding method (the method of making the electrode of a wiring board the 1st bonding point, and the electrode of the semiconductor chip the 2nd bonding point) opposite to the said positive bond, a bonding wire Since a margin can be earned between the semiconductor chip and the lower layer semiconductor chip, the problem that the bonding wire contacts the semiconductor chip for the memory circuit can be avoided. However, before the wire bonding step, a gold bump must be formed on the second bonding portion side (electrode of the semiconductor chip for control circuit), which lowers the assembly time and the assembly efficiency of the semiconductor device and increases the manufacturing cost of the semiconductor device. Occurs.

Accordingly, an object of the present invention is to provide a technique capable of improving the reliability of a semiconductor device having a structure in which a plurality of semiconductor chips having different planar dimensions are stacked in the same sealing body in a state of being laminated with an adhesive insulating film. It is to offer.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

Among the inventions disclosed in the present application, an outline of typical ones will be briefly described as follows.

That is, this invention is a 1st semiconductor chip mounted on the wiring board through the 1st insulating film which has adhesiveness, and a semiconductor chip whose planar dimension is smaller than the said 1st semiconductor chip, and adhere | attaches on the said 1st semiconductor chip. It has a 2nd semiconductor chip laminated | stacked through the 2nd insulating film which has the property, and the thickness of the said 2nd insulating film is formed thicker than the said 1st insulating film.

Among the inventions disclosed in the present application, the effects obtained by the representative ones are briefly described as follows.

That is, since the thickness of the said 2nd insulating film is formed thicker than the thickness of the said 1st insulating film, the reliability of a semiconductor device can be improved.

In the following embodiments, when necessary for the sake of convenience, the description is divided into a plurality of sections or embodiments, but unless otherwise specified, they are not related to each other, and one side is a part or all modification of the other side. , Details, supplementary explanations, and so on. In addition, in the following embodiment, when referring to the number of elements (including number, numerical value, quantity, range, etc.), except for the case where it is specifically specified, and in principle it is clearly limited to a specific number, etc. It is not limited to a specific number, More than a specific number may be sufficient. In addition, in the following embodiment, it cannot be overemphasized that the component (including the element step etc.) is not necessarily except a case where it specifically stated and when it thinks that it is indispensably essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of a component, it is substantially approximating or similar to the shape etc. except in the case where it is specifically stated and when it thinks that it is not obviously in principle. It shall be included. This also applies to the above numerical values and ranges. In addition, in the whole figure for demonstrating this embodiment, the thing which has the same function is attached | subjected with the same code | symbol, and the repeated description is abbreviate | omitted as much as possible. EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described in detail based on drawing.

(1st embodiment)

1 is a plan view of the semiconductor device according to the first embodiment, FIG. 2 is a sectional view taken along the line X1-X1 of FIG. 1, and FIG. 3 is a sectional view taken along the line X1-X1 of FIG. 1 and viewed from the direction opposite to the arrow of the line X1-X1. 4 is an enlarged cross-sectional view of the region A of FIG. 2, FIG. 5A is a cross-sectional view of an essential part of the semiconductor device examined by the present inventor, and FIG. 5B is a semiconductor device of the first embodiment. The main part of the cross section.

1, the sealing member is removed in order to make the internal structure of a semiconductor device easy to see. 3 also shows a bonding wire that does not intersect the X1-X1 line for easy understanding of the structure of the semiconductor device.

In the semiconductor device 1A of the first embodiment, the semiconductor chips 2M1 and 2M2 for memory circuits and the semiconductor chip 2C for control circuits for controlling the operation are laminated on the main surface of the wiring board 3. It is a semiconductor device of CSP (Chip Size Package) structure which accommodated in the same sealing body 4 in the state, and built up the memory system as a whole. The semiconductor device 1A of the present embodiment is used for, for example, a mobile device, a control device for a hard disk, or a memory card with a controller, which is required to be thinner or smaller.

As the adhesive member of each of the semiconductor chips 2M1, 2M2, and 2C, DAF (Die Attach Film) 5a to 5c are used. Although the paste material may be used as this adhesive member, in this 1st Embodiment, DAF is used for the following reasons.

The first reason is that the situation is good in securing the strength of the semiconductor chip. In recent years, since semiconductor chips have become thinner, how to secure the strength of the semiconductor chips has become an important problem. In the case of the DAF, it is possible to attach to the back surface of the thin semiconductor wafer in order to protect the thin semiconductor chip in the transfer process, the dicing process, and the transfer process (pickup) of the individual semiconductor chip. This is good.

The second reason is that since the DAF can be made thinner than the insulating paste material, it is better to make the total thickness of the semiconductor device 1A thinner. In recent years, since a miniaturization and thinning of a semiconductor device are requested | required, it is preferable that the thickness of an adhesive member is thinner in the structure which laminated | stacks several sheets of semiconductor chips.

The third is because the DAF is higher in thickness uniformity than the insulating paste material, and therefore can cope with an increase in the area of the semiconductor chip. In the case of a paste material, when the area of a semiconductor chip increases, it is difficult to ensure thickness uniformly in the surface, and the semiconductor chip may incline. On the other hand, in the case of DAF, since the uniformity of thickness is high, even if the area of a semiconductor chip increases, the flatness of a semiconductor chip can be ensured.

The fourth is because the DAF can be bonded at a lower temperature than the paste material. In the case of the paste material, in order to harden the paste material, after the semiconductor chip is mounted on the wiring board 3, a certain amount of heat treatment is required, so that the wiring board 3 is bent by the heat, and the wiring board 3 is well conveyed. There may be problems such as impossible. On the other hand, in the case of DAF, since it can adhere | attach at low temperature and the curvature of the wiring board 3 can be suppressed or prevented, the problem that the wiring board 3 cannot be conveyed can be avoided.

The fifth is because the planar positional accuracy of the semiconductor chip is high. In the case of a paste material, the planar position of a semiconductor chip may shift slightly at the time of adhesion | attachment of a semiconductor chip. On the other hand, in the case of DAF, the shift | offset | difference to the planar position of a semiconductor chip does not arise at the time of adhesion | attachment of a semiconductor chip.

Each semiconductor chip 2M1, 2M2, and 2C are electrically connected to the wiring of the wiring board 3 via the bonding wires (hereinafter simply called wires) 6a to 6c of the positive bond method, respectively. In the positive bonding method, the first bonding (first bond) of a wire is performed to a bonding pad (hereinafter simply referred to as a pad) of a semiconductor chip, and the bonding (second bond) that is performed after the first bond of a wire is performed on a wiring board. It is the method to perform with respect to the electrode. In the reverse bond method, which is the reverse of the positive bond method, gold bumps need to be formed on the pads of the semiconductor chip on the second bond part side, so that an increase in manufacturing process and cost is concerned. In contrast, in the first embodiment, the step of forming the gold bumps on the pads of the semiconductor chip can be omitted by employing the positive bonding method, so that the manufacturing process of the semiconductor device 1A can be reduced. The cost of the semiconductor device 1A can be reduced.

Such semiconductor chips 2M1, 2M2, and 2C, DAFs 5a to 5c, and wires 6a to 6c are covered and sealed by the sealing member 4. The sealing body 4 is formed of epoxy resin, for example.

The said wiring board (chip mounting member) 3 consists of a flat rectangular thin plate formed by the printed wiring board which made glass epoxy resin an insulation base material, for example, and has the main surface located in the opposite side along the thickness direction ( It has a main surface (second main surface) and a back surface (first main surface).

Solder resist SR is formed in the main surface and the back surface of this wiring board 3. The solder resist SR has a function of preventing solder from contacting a conductor pattern (wiring or an electrode) that does not require soldering, and a deterioration prevention function such as a conductor pattern due to moisture or contamination, as well as the main and rear surfaces of the wiring board 3. It has a function to make even more. As a method of flattening the main surface and the back surface of the wiring board 3, for example, a method of flattening the surface of the solder resist SR by applying pressure before the heat curing treatment of the solder resist SR or the solder resist SR Is applied twice to planarize the surface of the solder resist SR.

The main surface of the wiring board 3 is a surface on which the semiconductor chips 2M1, 2M2, and 2C are mounted. A plurality of electrodes 7a and 7b are disposed on the main surface of the wiring board 3. The electrode 7a is arrange | positioned in multiple numbers along the short side in the vicinity of the short side on one side of the wiring board 3, and is arrange | positioned. The electrode 7b is arrange | positioned in multiple numbers along the long side in the vicinity of the long side of one side of the wiring board 3, and is arrange | positioned.

On the other hand, the back surface of the wiring board 3 is a surface facing the wiring board on which the semiconductor device 1A is mounted. On the back surface of this wiring board 3, the some bump electrode 8 is arrange | positioned in matrix form in the state exposed from the said solder resist SR. Each bump electrode 8 has the electrode 8a formed in the back surface of the wiring board 3, and the bump part 8b joined to this. The electrode 8a is formed of copper, for example. The bump portion 8b is formed of lead-free solder such as tin (Sn) -silver (Ag) -copper, tin-silver-copper-antimony (Sb), tin-copper or the like. This bump electrode 8 (electrode 8a) is electrically connected to the electrodes 7a and 7b through the internal wiring of the wiring board 3.

The lowermost semiconductor chip (first semiconductor chip) 2M1 is formed of a planar rectangular semiconductor thin plate made of, for example, silicon (Si) single crystal, and is formed on the main surface of the wiring board 3 by the DAF 5a. It is adhere | attached and fixed on the (2nd main surface).

In the vicinity of one side short side of the semiconductor chip 2M1, a plurality of pads 9a are arranged side by side along the short side of the semiconductor chip 2M1. The pad 9a is made of aluminum (Al) or an aluminum alloy, for example. The plurality of pads 9a of the semiconductor chip 2M1 are electrically connected to the electrodes 7a of the wiring board 3 through the plurality of wires (first bonding wires) 6a of the positive bonding method. The wire 6a is formed of gold (Au), for example.

On the main surface of the semiconductor chip 2M1, the semiconductor chip (first semiconductor chip) 2M2 is bonded and fixed by the DAF 5b. The semiconductor chip 2M2 is formed of, for example, a flat rectangular semiconductor thin plate made of a silicon single crystal, and in the state in which the semiconductor chip 2M1 of the lower layer is aligned with the longitudinal direction and the width direction, the lower semiconductor chip is further formed. It is arrange | positioned so that it may be covered on the main surface of the lower semiconductor chip 2M1 in the state shift | deviated in the longitudinal direction of the semiconductor chip 2M1 so that the some pad 9a of 2M1 may be exposed.

In the vicinity of one side short side of the semiconductor chip 2M2, a plurality of pads 9b are arranged side by side along the short side of the semiconductor chip 2M2. This pad 9b is also formed of aluminum or an aluminum alloy, for example. The plurality of pads 9b of the semiconductor chip 2M2 are electrically connected to the electrodes 7a of the wiring board 3 through the plurality of wires (first bonding wires) 6b of the positive bonding method. The wire 6b is also formed of gold, for example.

The two semiconductor chips 2M1 and 2M2 are formed with the same dimensions (vertical, horizontal and thickness dm1 and dm2), and each of the main surfaces has a flash memory (for example, 4 GB) having the same storage capacity. An assist gate AND flash memory) is formed. The thicknesses dm1 and dm2 of each of the semiconductor chips 2M1 and 2M2 are, for example, about 80 to 90 μm. By adopting the AND type memory, the operation speed of the circuit can be improved.

Here, in general, as the adhesive member for fixing the semiconductor chip 2M1 to the wiring board 3, the paste material is used in consideration of the wiring of the main surface of the wiring board 3 and the unevenness of the electrode, while the semiconductor chip 2M2 is used. DAF is used as an adhesive member for fixing). However, in the same semiconductor chips 2M1 and 2M2, there is a problem that assembly is complicated when the adhesive members are different.

On the other hand, in this 1st Embodiment, since flatness of the main surface of the wiring board 3 can be ensured by the soldering resist SR as mentioned above, DAF (as an adhesive member of the lowermost semiconductor chip 2M1) 5a) may be used. That is, since the same DAFs 5a and 5b can be used as the adhesive members of the same semiconductor chips 2M1 and 2M2, the assembling process of the semiconductor device 1A can be simplified. The thicknesses df1 and df2 of these DAFs 5a and 5b are equivalent, for example, about 10 m.

On the main surface of the semiconductor chip 2M2, the semiconductor chip (second semiconductor chip) 2C is bonded and fixed by the DAF 5c. This semiconductor chip 2C is formed of, for example, a flat rectangular semiconductor thin plate made of silicon single crystal, and a control circuit for controlling the operation of the memory circuits of the semiconductor chips 2M1 and 2M2 is formed on the main surface thereof. It is.

This semiconductor chip 2C is arrange | positioned in the main surface of the semiconductor chip 2M2 in the state which matched the lower direction semiconductor chip 2M2 with the longitudinal direction and the width direction. In the vicinity of the long side on one side of the semiconductor chip 2C, a plurality of pads 9c are arranged side by side along the long side of the semiconductor chip 2C. This pad 9c is also formed of aluminum or an aluminum alloy, for example. The plurality of pads 9c of the semiconductor chip 2C are electrically connected to the electrodes 7b of the wiring board 3 through the plurality of wires (second bonding wires) 6c of the positive bonding method. The wire 6c is formed of gold, for example.

The planar dimensions (vertical, horizontal and area) of the uppermost semiconductor chip 2C are smaller than the planar dimensions (vertical, horizontal and area) of the semiconductor chips 2M1 and 2M2 described above. For this reason, if no means is devised at all, as shown by the broken line in Fig. 5A, the problem that the wire 6c comes in close contact with the corner of the main surface of the semiconductor chip 2M2 is a problem. Occurs. In FIG. 5A, when the thicknesses of the semiconductor chips 2M1, 2M2, and 2C are equal, and the same DAF 5a is used as the adhesive member of each of the semiconductor chips 2M1, 2M2, and 2C, FIG. To illustrate.

As a countermeasure for such a problem, what is necessary is just to make height of the 1st bond of the wire 6c (distance separated along the direction orthogonal to the main surface from the main surface of the wiring board 3) high. Therefore, in the first embodiment, it is preferable to make the thicknesses of the DAFs 5a to 5c the same in consideration of the procurement and standardization of the members regardless of the memory circuit and the control circuit. The thickness df3 of the DAF 5c on the back of 2C) was made thicker than the thicknesses df1 and df2 of the DAFs 5a and 5b on the back of the semiconductor chips 2M1 and 2M2. The thickness df3 of the DAF 5c is, for example, about 25 μm.

Thus, since the height of the 1st bond of the wire 6c can be made high by thickening DAF 5c, as shown by the broken line of FIG. 5 (b) by that, The wire 6c can be spaced apart from the main surface corner portion of the semiconductor chip 2M2. For this reason, since the defective potential which the wire 6c contacts the corner part of the main surface of the semiconductor chip 2M2 can be reduced, the assemblability and reliability of the semiconductor device 1A can be improved.

In addition, since the loop of the wire 6c does not increase by this structure, neither the permeation nor exposure of the wire 6c arises. Therefore, the yield of the semiconductor device 1A can be improved. 5B illustrates a case where the thicknesses of the semiconductor chips 2M1, 2M2, and 2C are equal.

Here, the thinning of the DAFs 5a and 5b on the back surfaces of the semiconductor chips 2M1 and 2M2 is, for example, for the following reasons.

That is, from the viewpoint of increasing the height of the first bond of the wire 6c, it is conceivable that the DAFs 5a and 5b on the back surface of the semiconductor chips 2M1 and 2M2 may be thickened. However, when the DAFs 5a and 5b are thickened, the main surface of the semiconductor chip 2M2 also increases, so that the defective potential of the wire 6c in contact with the corner of the main surface of the semiconductor chip 2M2 increases. For this reason, DAF 5a, 5b of the back surface of semiconductor chip 2M1, 2M2 is made relatively thin.

In addition, with the increase in the versatility of electronic devices such as mobile devices and digital home appliances, the memory is gradually increasing in capacity. In order to cope with this, in particular, it is necessary to stack semiconductor chips for memory circuits in multiple layers. Here, in the present state, among the determined thicknesses (thickness of the sealing body 4) of the semiconductor device 1A, in order to realize the multilayering of the semiconductor chip, basically all the DAFs 5a to 5c are in the direction of thinning. . In contrast to this, in the first embodiment, the DAF 5c on the rear surface of the semiconductor chip 2C is removed from the viewpoint of reducing the defect in which the wire 6c contacts the main surface corner portion of the semiconductor chip 2M2 as described above. Thickening. Therefore, the DAFs 5a and 5b on the back surface of the semiconductor chips 2M1 and 2M2 for memory circuits are made thinner by that amount.

In addition, thinning the semiconductor chip for the memory circuit can further stack the semiconductor chip in the semiconductor device 1A, leading to a large capacity. However, the thicknesses of the semiconductor chips 2M1 and 2M2 for memory circuits have reached their limits in consideration of securing pickup performance (assembly yield) in the semiconductor chip mounting process. Therefore, it is better to thin the DAFs 5a and 5b on the back surface of the semiconductor chips 2M1 and 2M2 for memory circuits.

2 C of uppermost semiconductor chips are arrange | positioned in the state in which the main surface center shifted from the main surface center of the lower semiconductor chip 2M2 to the one side long side vicinity of the semiconductor chip 2M2. However, it is considered that the semiconductor chip 2C will not be too close to the long side of one side of the lower semiconductor chip 2M2. The reason is explained with reference to FIG. 6 and FIG. FIG. 6 is a sectional view of an essential part of the semiconductor device examined by the present inventor, and FIGS. 7A and 7B are a plan view of an essential part of the semiconductor device, showing the arrangement of the semiconductor chip 2C in the uppermost layer.

As shown in Fig. 6, by arranging the semiconductor chip 2C as close as possible to the outer circumference of the semiconductor chip 2M2, the problem that the wire 6c contacts the semiconductor chip 2M2 can be avoided. . In this case, however, there is a problem that the loop of the wire 6c becomes high, and the loop portion is visible or exposed through the sealing member 4. In addition, the falling trajectory from the first bond to the second bond of the wire 6c becomes too steep, making joining at the second bond difficult. As shown in Figs. 7A and 7B, the closer the semiconductor chip 2C is to the outer periphery of the semiconductor chip 2M2, the wires at both ends of the array direction in the plurality of wires 6c. 6c is to be obliquely wire-bonded when viewed in a plan view, but the incidence angle θ of the wire 6c becomes an acute angle, so that an interval between adjacent wires 6c becomes narrow and adjacent wires ( 6c) The short circuit defect between each other easily occurs.

Therefore, in this 1st Embodiment, the semiconductor chip 2C is arrange | positioned so that it may not be too close to the one side long side of the lower semiconductor chip 2M2. As a result, the distance between the first bond and the second bond of the wire 6c can be set at an appropriate distance, so that the loop height of the wire 6c does not become too high and the trajectory of the wire 6c is too steep. There is no loss. In addition, the incidence angle θ of the wire 6c does not become too sharp. Therefore, the stability of the wire 6c can be improved.

Moreover, arrange | positioning the electrode 7b with which the semiconductor chip 2C is electrically connected through the wire 6c in the long side of the wiring board 3 makes it easy to arrange the wiring in the wiring board 3. To do that. Moreover, when the electrode 7b to which the wire 6c is connected is arrange | positioned at the short side of the wiring board 3, the dimension of the longitudinal direction of the semiconductor device 1A will become longer, and the planar dimension of the semiconductor device 1A will become As it grows, it is to avoid it.

In the first embodiment, the thickness dc of the semiconductor chip 2C is formed to be thicker than the thicknesses dm1 and dm2 of the semiconductor chips 2M1 and 2M2, respectively. The thickness dc of the semiconductor chip 2C is, for example, about 120 to 150 µm.

The main reason for making the semiconductor chip 2C thick is for curvature suppression of the semiconductor device 1A. That is, when there is much quantity of the sealing body (resin) 4 in the semiconductor device 1A, the semiconductor device 1A will bend by hardening shrinkage of the sealing body 4, and the semiconductor device 1A is mounted. It may become difficult. Therefore, in the first embodiment, the semiconductor chip 2C is made thick. Thereby, since the volume of the semiconductor chip in the sealing body 4 can be increased, and the quantity of the sealing body (resin) 4 of the semiconductor device 1A can be reduced, the bending of the semiconductor device 1A is prevented. It can suppress, and the mounting failure of the semiconductor device 1A can be reduced or prevented.

When only curvature suppression is taken into consideration, it is conceivable to thicken the lower semiconductor chips 2M1 and 2M2. However, when the lower semiconductor chips 2M1 and 2M2 are thickened, the height of the main surface of the semiconductor chip 2M2 is increased. Poor contact between the one wire 6c and the main surface corner portion of the semiconductor chip 2M2 is likely to occur. In addition, when the loop of the wire 6c is made high in order to avoid the poor contact of the wire 6c, the sealing body 4 must be thickened from the viewpoint of preventing the permeation or exposure of the wire 6c. 1A) thickens. In addition, among the determined thicknesses (thickness of the sealing body 4) of the semiconductor device 1A as described above, in order to realize the multilayering of the semiconductor chip, the semiconductor chips for memory circuits 2M1 and 2M2 for which the multilayering is essential are made thin. One is preferable in realizing the thinning of the semiconductor device 1A.

Therefore, in this 1st Embodiment, the thickness of the uppermost semiconductor chip 2C is made thicker than the lower semiconductor chips 2M1 and 2M2. Thereby, the curvature of the semiconductor device 1A can be suppressed, without thickening the semiconductor device 1A. In addition, since the first bond point of the semiconductor chip 2C is increased by making the semiconductor chip 2C thicker than the lower semiconductor chips 2M1 and 2M2, the wire 6c is the main surface corner portion of the semiconductor chip 2M2. Poor potential in contact with can be further reduced.

Here, the present inventors found for the first time that when the semiconductor chip 2C was thickened, the following new problem became remarkable.

The first problem is that chipping on the back surface of the semiconductor chip 2C is likely to occur.

When dicing a semiconductor wafer with a DAF, the hard and flexible ones are cut at the same time, so that chipping is likely to occur at the boundary between the semiconductor chip and the DAF (the corner on the back side of the semiconductor chip). In particular, this chipping defect tends to increase as the semiconductor wafer becomes thicker. According to the analysis result of the present inventors, chipping does not occur very much when the thickness of a semiconductor wafer is about 90 micrometers, but chipping increases when the thickness of a semiconductor wafer becomes 150 micrometers or more. When the silicon chip by such chipping is laminated | stacked on the back surface of the DAF 5c from the back surface of the semiconductor chip 2C, and affixed, the semiconductor chip 2C will be laminated | stacked on the main surface of the semiconductor chip 2M2, There is a problem that silicon debris on the back surface of the DAF 5c damages the main surface of the semiconductor chip 2M2.

In contrast to this, according to the first embodiment of the present invention, even if chipping occurs on the back surface of the semiconductor chip 2C by thickening the DAF 5c, silicon debris due to the chipping returns to the back surface of the DAF 5c. Since it can reduce or prevent that, the damage defect of the main surface of the semiconductor chip 2M2 resulting from the chipping of silicon by chipping can be reduced or prevented. According to the examination of the present inventors, it can be seen that by setting the thickness of the DAF 5c to 20 µm or more, it is possible to reduce the return of the chipping debris to the back of the DAF 5c.

The second problem is a problem due to the inability to absorb the warpage of the semiconductor chip 2C. This problem is explained with reference to Figs. 8 and 9, and the solution result is explained with reference to Fig. 10. 8 shows a sectional view of the thin semiconductor chip 100A and the mounting substrate 101 on which the thin semiconductor chip 100A is mounted. 9 shows a sectional view of the semiconductor chip 100B thicker than the semiconductor chip 100A and the mounting substrate 101 on which the semiconductor chip 100B is mounted. Both thin DAFs 5a are used for the bonding members of the semiconductor chips 100A and 100B. FIG. 10 shows a cross-sectional view of the semiconductor chip 2C and the mounting substrate 101 on which it is mounted.

As shown in Fig. 8A, when the semiconductor chip 100A is thin, even if warpage has occurred in the semiconductor chip 100A before mounting, the rigidity thereof is low, and therefore, it is shown in Fig. 8B. As described above, the semiconductor chip 100A after mounting is mounted in a substantially flat state along the mounting surface by the adhesive force of the DAF 5a.

However, as shown in Fig. 9A, when the semiconductor chip 100B becomes thick, the stiffness is increased so that it is superior to the adhesive force of the DAF 5a. As shown in Fig. 9B, The semiconductor chip 100B is mounted in a closed state, and a gap is formed in which the semiconductor chip 100B is not adhered to the outer peripheral portion (area surrounded by the broken line) of the semiconductor chip 100B. As a result, in the assembling process of the semiconductor device 1A, the semiconductor chip 100B is peeled off from the gap as a starting point, or a mold resin is drawn into the back surface side of the semiconductor chip 100B from the gap in the mold process. The semiconductor chip 100B is cracked.

In contrast to this, according to the first embodiment, by thickening the DAF 5c, the warpage of the semiconductor chip 2C can be absorbed by the DAF 5c as shown in FIG. 10. Thereby, the contact area between the semiconductor chip 2C and the mounting substrate 101 (corresponding to the semiconductor chip 2M2 in the first embodiment) can be widened, and the outer peripheral portion of the semiconductor chip 2C (with a broken line) Since the clearance gap of the surrounding region can be reduced, peeling and a crack of the semiconductor chip 2C can be reduced or prevented.

According to the experiments and evaluation results of the present inventors, the thickness of a semiconductor chip to which a DAF having a thickness of 10 μm is applied is preferably up to 10 times the thickness of the DAF, and when it exceeds the thickness, the thickness of the DAF is greater than 10 μm. It is desirable to apply. The reason for using a single DAF having a thickness of 10 μm as a reference is due to the flatness of the main surface of the wiring board 3. The flatness of the main surface of the wiring board 3 is 5 micrometers as a present state, 3 micrometers, and a guaranteed range. In addition, the manufacturing deviation of DAF thickness is set to +/- 2micrometer. From this, the semiconductor chip is fixed to the wiring board 3, and the DAF thickness considered as a level with no problem in terms of reliability is considered to be the thinnest specification of about 10 m.

Next, an example of the manufacturing method of the semiconductor device 1A of the first embodiment will be described with reference to FIGS. 11 and 12.

First, as shown in FIG. 11, the back surface of the semiconductor wafer 2W after the wafer process is finished is ground by the grindstone 15, and the semiconductor wafer 2W is made into a desired thickness (back grinding process of FIG. 11). 200). Although one semiconductor wafer 2W is shown here, the semiconductor chips 2M1 and 2M2 and the semiconductor chip 2C are each formed of separate semiconductor wafers. Moreover, you may perform a grinding | polishing process or an etching process with respect to the back surface of the semiconductor wafer 2W after the back surface grinding process of the semiconductor wafer 2W.

Subsequently, the back surface of the semiconductor wafer 2W is bonded to the DAF bonding surface of the wafer sheet 16 (wafer mounting step 201 in Fig. 11). This wafer sheet 16 is a DAF / dicing film integrated sheet | seat in which DAF adhere | attached on the main surface of a dicing film. The semiconductor wafer 2W is mounted on the wafer sheet 16 with its main surface facing upward and the back surface of the semiconductor wafer 2W directly bonded to the DAF of the main surface of the wafer sheet 16.

Subsequently, after attaching the wafer ring 17 surrounding the outer circumference of the semiconductor wafer 2W to the main surface of the wafer sheet 16, the semiconductor wafer 2W is conveyed to a dicing apparatus to perform a dicing process. (Dicing Step 202 in Fig. 11). The dicing process cuts the semiconductor wafer 2W by applying the dicing blade 18 which rotates at high speed along the cutting line (circumference of the semiconductor chip) of the semiconductor wafer 2W, and cuts each semiconductor chip 2M1, 2M2. Alternatively, the process is divided into semiconductor chips 2C.

Subsequently, the semiconductor chip 2M1 is picked up from the semiconductor wafer 2W after the dicing step and mounted on the main surface of the wiring board 3. At this time, the semiconductor chip 2M1 is adhesively fixed to the wiring board 3 by the Daf 5a on its back surface. The wiring board 3 in this step has a structure in which the formation regions of the plurality of semiconductor devices are integrally formed. Then, the semiconductor chip 2M2 is picked up from the same semiconductor wafer 2W, and the semiconductor chip 2M2 is mounted on the main surface of the semiconductor chip 2M1. At this time, the semiconductor chip 2M2 is adhesively fixed to the semiconductor chip 2M1 by the DAF 5b on its rear surface (chip mounting step 203 in FIG. 11).

Here, since the semiconductor chips 2M1 and 2M2 are the same memory, the semiconductor chips 2M1 and 2M2 are picked up from the same semiconductor wafer 2W. Thereby, the manufacturing process of a semiconductor device can be simplified. In addition, since memory having similar characteristics can be mounted, the performance of the semiconductor device 1A can be improved. In addition, the semiconductor chips 2M1 and 2M2 may be picked up from separate semiconductor wafers.

Subsequently, the semiconductor chip 2C is picked up from the semiconductor wafer 2W after the dicing step and mounted on the main surface of the semiconductor chip 2M2. At this time, the semiconductor chip 2C is adhesively fixed to the semiconductor chip 2M2 by the DAF 5c on its back surface (chip mounting step 204 in Fig. 11).

12, the semiconductor chips 2M1, 2M2 and 2C on the wiring board 3 and the electrodes of the wiring board 3 are connected by wires 6a, 6b and 6c (FIG. 12). Wire bonding process 205).

Subsequently, the sealing body 4 in which the semiconductor chips 2M1, 2M2, 2C, the wires 6a, 6b, 6c, etc. of the several semiconductor device area | region of the main surface of the wiring board 3 after a wire bonding process were formed by mold resin. ) And the package is collectively sealed (mold process step 206 in FIG. 12).

Subsequently, the wiring board 3 is turned upside down, and the solder balls 8b1 formed by lead-free solder are placed on the plurality of electrodes 8a disposed on the back surface of each of the semiconductor device formation regions on the back surface of the wiring board 3. Then, the bump part 8b is formed in the electrode 8a by performing heat processing (reflow heating process) (ball mounting process 207 of FIG. 12).

Subsequently, the dicing blade 19 which rotates at high speed is cut from the back surface of the wiring board 3 along the cutting line (boundary line of the semiconductor device 1A) of the wiring board 3, and each semiconductor device 1A is cut. ) Into pieces (reorganization cutting process 208 in Fig. 12).

Thereafter, the semiconductor device 1A is manufactured by screening and visual inspection (step 209 in FIG. 12).

(2nd embodiment)

In the first embodiment, it is assumed that the semiconductor device 1A is applied to an electronic device requiring high-speed operation, but the case where the flash memories of the semiconductor chips 2M1 and 2M2 are AND type has been described. For example, a flash memory of NAND type may be used.

13 is a sectional view of principal parts of the semiconductor device 1A of the second embodiment. The broken line shows the semiconductor chips 2M1 and 2M2 in which the AND-type flash memory in the first embodiment is formed. The distance L1 represents the distance from the corner of the main surface of the semiconductor chip 2M2 on which the AND-type flash memory is formed to the wire 6c.

In the case of the NAND type, since the planar dimensions of the semiconductor chips 2M1 and 2M2 can be made smaller than in the case of the AND type (broken line), the distance L2 from the main surface corner of the semiconductor chip 2M2 to the wire 6c is distanced. It can be made longer than L1. For this reason, since the defective potential which the wire 6c contacts the corner part of the main surface of the semiconductor chip 2M2 can be reduced, the assemblability and reliability of the semiconductor device 1A can be improved.

(Third embodiment)

In the first and second embodiments, the case where two semiconductor chips for a memory circuit are stacked is described. However, the present invention is not limited thereto, and may be stacked three or more, for example, or only one.

14 (a) and 14 (b) are cross-sectional views of principal parts of a semiconductor device examined by the present inventors. Fig. 14A shows the case where two semiconductor chips 2M1 and 2M2 for memory circuits are shown, and Fig. 14B shows the case where one semiconductor chip 2M1 for memory circuits is one. As for DAF 5a of the back surface of semiconductor chip 2C, 2M1, 2M2, the thing of the same thickness is used for all.

In the configuration shown in Fig. 14A, when the memory circuit semiconductor chip is one, the height of the main surface of the memory circuit semiconductor chip below the control circuit semiconductor chip 2C is lowered, so that the wire 6c It is considered that a defect in contact with the corner of the main surface of the semiconductor chip for a memory circuit below the semiconductor chip 2C does not occur.

In reality, however, there is a demand not to change the total thickness of the semiconductor device, and if only one semiconductor chip for a memory circuit is used, the amount of the semiconductor chip in the semiconductor device 1A is reduced and the sealing body 4 ( Since the amount of the resin) increases, the semiconductor device 1A tends to bend due to the cure shrinkage of the resin due to the heat treatment during the manufacturing process and the difference in thermal expansion coefficient between the semiconductor chip and the resin. Therefore, in the present state, as shown in Fig. 14B, the thickness of the wiring board 3 is made thicker than in the case of Fig. 14A to reduce the amount of the sealing member 4 (resin). The bending of the semiconductor device 1A is suppressed or prevented.

However, in this case, since the wire 6c must be formed in the range (range of the thickness direction) of the thin sealing body 4, as shown in FIG.14 (b), if no means are taken at all, the wire 6c ), The potential of contact with the corner of the main surface corner of the semiconductor chip 2M1 for the memory circuit increases. Therefore, it is preferable to make it the same as the structure demonstrated in the said 1st Embodiment also when one semiconductor chip for memory circuits is used.

15 and 16 show sectional views of principal parts of the semiconductor device 1A of the third embodiment. There is only one semiconductor chip 2M1 for a memory circuit. In addition, the thickness of the wiring board 3 is thicker than that described in the first embodiment. Thereby, since the quantity of the sealing body 4 (resin) can be reduced, the curvature of the semiconductor device 1A can be suppressed or prevented.

The DAF 5c on the back side of the upper control circuit semiconductor chip 2C is formed thicker than the DAF 5a on the back side of the lower memory circuit semiconductor chip 2M1. Thereby, like the said 1st Embodiment, the defect potential which the wire 6c contacts the main surface corner part of the semiconductor chip 2M1 can be reduced.

In addition, the thickness of the upper control circuit semiconductor chip 2C is formed thicker than the lower memory circuit semiconductor chip 2M1. Thereby, like the said 1st Embodiment, the defect potential which the wire 6c contacts the main surface corner part of the semiconductor chip 2M1 can further be reduced. In addition, since the amount of the sealing member 4 (resin) can be reduced by thickening the semiconductor chip 2C, the warpage of the semiconductor device 1A can be further suppressed or prevented.

(4th embodiment)

17 is a plan view of the semiconductor device of the fourth embodiment, and FIG. 18 is a sectional view taken along the line Y1-Y1 in FIG. 17 shows the internal structure of the semiconductor device.

In the semiconductor device 1B of the fourth embodiment, the logic chip semiconductor chip 2P and the memory circuit semiconductor chip 2M3 are laminated on the main surface of the tab (die pad) 25a of the lead frame. Is a semiconductor device having a quad flat package (QFP) structure, which is housed in the same sealing body 4 and constructed as a microprocessor system as a whole.

In the fourth embodiment, the lead frame 25 is used as the chip mounting member. The lead frame 25 is made of, for example, a metal thin plate such as copper or 42 alloy, and is outer side from the four corners of the tab 25a, the plurality of leads 25b disposed on the outer circumference thereof, and the tab 25a. It has the tab suspension lead 25c extended toward it.

Moreover, the lead 25b has the inner lead 25bi and the outer lead 25bo integrally. The inner lead 25bi is a part inside the sealing body 4 in the lid 25b, and the outer lead 25bo is a part outside the sealing body 4 in the lid 25b.

On the main surface of the tab 25a, the semiconductor chip (first semiconductor chip) 2P is bonded and fixed by the DAF 5a. The semiconductor chip 2P is formed of, for example, a planar square semiconductor thin plate made of a silicon single crystal, and a logic circuit such as a microprocessor or an application specific integrated circuit (ASIC) is formed on the main surface thereof. It is.

In the vicinity of the outer circumference of the semiconductor chip 2P, a plurality of pads are arranged along the outer circumference. This pad is formed of aluminum or an aluminum alloy, for example. The plurality of pads of the semiconductor chip 2P are electrically connected to the inner lead 25bi via the plurality of wires (first bonding wires) 6d of the positive bonding method. The wire 6d is formed of gold, for example.

On the main surface of the semiconductor chip 2P, the semiconductor chip (second semiconductor chip) 2M3 is bonded and fixed by the DAF 5c. The semiconductor chip 2M3 is formed of, for example, a flat rectangular semiconductor thin plate made of silicon single crystal, and on the main surface thereof, for example, 16 MG (megabyte) of SDRAM (Synchronous Dynamic Random Access Memory) is formed. It is.

This semiconductor chip 2M3 is disposed near one side of the lower semiconductor chip 2P. In the vicinity of the long side (side along one side of the semiconductor chip 2P) on one side of the semiconductor chip 2M3, a plurality of pads are arranged side by side along the long side of the semiconductor chip 2M3. This pad is also formed of aluminum or an aluminum alloy, for example. The plurality of pads of the semiconductor chip 2M3 are electrically connected to the inner lead 25bi via a plurality of wires (second bonding wires) 6e of the positive bonding method. The wire 6e is formed of gold, for example.

Also in the fourth embodiment, the planar dimensions (vertical, horizontal and area) of the upper semiconductor chip 2M3 are smaller than the planar dimensions (vertical, horizontal and area) of the lower semiconductor chip 2P. In the case of the fourth embodiment, the wire 6e connected to the upper semiconductor chip 2M3 does not contact the main surface corner portion of the lower semiconductor chip 2P. However, the wire 6e may come in contact with the wire 6d connected to the lower semiconductor chip 2P.

Therefore, also in this 4th Embodiment, the thickness of the DAF 5c of the back surface of the upper semiconductor chip 2M3 is made thicker than the DAF 5a of the back surface of the lower semiconductor chip 2P. Since the height of the 1st bond of the wire 6e can be made high by this, the upper wire 6e can be spaced apart from the lower wire 6d by that much. For this reason, since the potential of the upper wire 6e contacting the lower wire 6d can be reduced, the assemblability and reliability of the semiconductor device 1B can be improved.

In addition, since the loop of the wire 6e does not increase by this structure, neither permeation nor exposure of the wire 6e occurs. Therefore, the yield of the semiconductor device 1B can be improved.

Moreover, also in this 4th Embodiment, the thickness of the upper semiconductor chip 2M3 is thicker than the lower semiconductor chip 2P. Thereby, like the said 1st Embodiment, the curvature of the semiconductor device 1B can be suppressed without thickening the semiconductor device 1B.

In addition, also in this 4th Embodiment, even if chipping generate | occur | produced on the back surface of the semiconductor chip 2M3 by thickening DAF 5c similarly to the said 1st Embodiment, the silicon waste by the chipping is DAF ( Since it can reduce or prevent returning to the back surface of 5c), the damage defect of the main surface of the semiconductor chip 2P resulting from a silicon chip | tip can be reduced or prevented.

In addition, by thickening the DAF 5c, the warpage of the semiconductor chip 2M3 can be absorbed by the DAF 5c as in the first embodiment. As a result, even if the semiconductor chip 2M3 is thickened, the adhesion area between the semiconductor chip 2M3 and the semiconductor chip 2P can be widened, and the gap between the outer peripheral portions of the semiconductor chip 2M3 can be reduced. Peeling and cracking of the semiconductor chip 2M3 can be reduced or prevented.

As mentioned above, although the invention made by this inventor was concretely demonstrated based on embodiment, it is a matter of course that this invention is not limited to the said embodiment and can be variously changed in the range which does not deviate from the summary.

For example, in the said embodiment, although the case where it applied to the semiconductor device of the package structure in which the some bump electrode was arrange | positioned on the back surface of the semiconductor device was demonstrated, it is not limited to this, For example, it is flat on the back surface of a semiconductor device. The present invention can also be applied to a semiconductor device having a land grid array (LGA) package structure in which the rear electrodes are arranged in an array shape.

The present invention can be applied to the manufacturing industry of semiconductor devices.

1 is a plan view of a semiconductor device according to one embodiment of the present invention.

FIG. 2 is a sectional view taken along the line X1-X1 of FIG.

Fig. 3 is a cross sectional view taken along the line X1-X1 in Fig. 1, and is seen in the direction opposite to the arrow of the line X1-X1.

4 is an enlarged cross-sectional view of the region A of FIG.

Fig. 5A is a sectional view of principal parts of a semiconductor device examined by the present inventor, and Fig. 5B is a sectional view of principal parts of a semiconductor device according to an embodiment of the present invention.

Fig. 6 is a sectional view of principal parts of a semiconductor device, which has been examined by the present inventors.

7 (a) and 7 (b) are plan views of the main parts of the semiconductor device, showing the arrangement of the uppermost semiconductor chips.

8 (a) and 8 (b) are cross-sectional views of a thin semiconductor chip and a mounting substrate on which it is mounted.

9 (a) and 9 (b) are cross-sectional views of a thick semiconductor chip and a mounting substrate on which it is mounted.

Fig. 10 is a sectional view of a semiconductor chip 2C and a mounting substrate on which the chip is mounted.

11 is an explanatory diagram of an example of a process of manufacturing a semiconductor device of one embodiment of the present invention.

12 is an explanatory diagram of an example of a process of manufacturing the semiconductor device subsequent to FIG. 11;

13 is an essential part cross sectional view of a semiconductor device according to another embodiment (second embodiment) of the present invention.

Fig. 14A is a sectional view of principal parts of a semiconductor device in the case of two semiconductor chips for memory circuits, and Fig. 14B is a sectional view of principal parts of a semiconductor device in the case of one semiconductor chip for memory circuits.

Fig. 15 is a sectional view of principal parts of a semiconductor device, according to another embodiment (third embodiment) of the present invention.

Fig. 16 is a sectional view of principal parts of a semiconductor device, according to another embodiment (third embodiment) of the present invention.

Fig. 17 is a plan view of a semiconductor device of another embodiment (fourth embodiment) of the present invention.

FIG. 18 is a sectional view taken along the line Y1-Y1 in FIG.

Fig. 19 is an explanatory diagram of bonding wire formation by the positive bonding method.

20 is an explanatory diagram of bonding wire formation by the positive bonding method;

21 is an explanatory diagram of bonding wire formation by the positive bonding method;

<Explanation of symbols for the main parts of the drawings>

1A, 1B: semiconductor device

2W: Semiconductor Wafer

2M1, 2M2, 2P: semiconductor chip (first semiconductor chip)

2M3, 2C: semiconductor chip (second semiconductor chip)

3: wiring board (chip mounting member)

4: sealing body

5a, 5b: DAF (1st insulating film)

5c: DAF (second insulation film)

6a, 6b, 6d: bonding wire (first bonding wire)

6c, 6e: bonding wire (second bonding wire)

7a, 7b: electrode

8: bump electrode

8a: electrode

8b: bump part

9a, 9b, 9c: bonding pads

15: grindstone

16: wafer sheet

17: wafer ring

18, 19: dicing blade

25: lead frame

25a: tab

25b: lead

25bi: inner lead

25bo: outer lead

25c: Tap Suspension Leads

100A, 100B: Semiconductor Chip

101: mounting substrate

SR: Solder Resist

Claims (13)

A wiring board having a first main surface and a second main surface positioned opposite to each other along the thickness direction, a first semiconductor chip mounted on the second main surface of the wiring board via an adhesive first insulating film; A first bonding wire of a positive bonding method for electrically connecting an electrode of the first semiconductor chip to an electrode of the wiring board, and a second insulating film having adhesiveness on the first semiconductor chip. And a second bonding wire of a positive bonding method for electrically connecting an electrode of the second semiconductor chip to an electrode of the wiring board, wherein the planar dimension of the first semiconductor chip is the second semiconductor chip. It is larger than the plane dimension of, and the thickness of a said 2nd insulating film is thicker than the thickness of a said 1st insulating film, The semiconductor device characterized by the above-mentioned. The semiconductor device according to claim 1, wherein a memory circuit is formed on said first semiconductor chip, and a logic circuit is formed on said second semiconductor chip. The semiconductor device according to claim 1, wherein the second semiconductor chip is thicker than the first semiconductor chip. The semiconductor device according to claim 1, wherein the first semiconductor chip is formed by stacking a plurality of same types of semiconductor chips in a direction crossing the second main surface of the wiring board. A wiring board having a first main surface and a second main surface positioned opposite to each other along the thickness direction, and a semiconductor chip for a memory circuit mounted on the second main surface of the wiring board through an adhesive first insulating film; And a first bonding wire having a positive bonding method for electrically connecting the electrode of the semiconductor chip for the memory circuit to the electrode of the wiring board, and a second insulating film having adhesiveness on the semiconductor chip for the memory circuit. And a second bonding wire of a positive bonding method for electrically connecting an electrode of the logic circuit semiconductor chip to an electrode of the wiring board, wherein the planar dimension of the semiconductor chip for memory circuit is the logic. It is larger than the plane dimension of the circuit semiconductor chip, and the thickness of the said 2nd insulating film is thicker than the said 1st insulating film, The semiconductor device characterized by the above-mentioned. The semiconductor device according to claim 5, wherein the semiconductor chip for logic circuit is thicker than the semiconductor chip for memory circuit. 6. The semiconductor device according to claim 5, wherein a plurality of semiconductor chips for the memory circuit are stacked on a second main surface of the wiring board. 8. The semiconductor device according to claim 7, wherein the plurality of semiconductor chips for memory circuits stacked on the second main surface of the wiring board are the same type of semiconductor chips for memory circuits. The electrode of the said semiconductor circuit for logic circuits, the electrode of the said wiring board, and the said 2nd bonding wire which electrically connects these electrodes are arrange | positioned at the long side of the said semiconductor circuit for memory circuits. There is a semiconductor device characterized by the above-mentioned. A semiconductor device according to claim 5, wherein an AND type memory circuit is formed on said memory circuit semiconductor chip. The semiconductor device according to claim 5, wherein a NAND type memory circuit is formed on the memory chip. A chip mounting member having a first main surface and a second main surface positioned opposite to each other along the thickness direction, and a first semiconductor chip mounted on the second main surface of the chip mounting member through an adhesive first insulating film. And a first bonding wire of a positive bonding method for electrically connecting an electrode of the first semiconductor chip to an electrode of the chip mounting member, and a second insulating film having adhesiveness on the first semiconductor chip. And a second bonding wire having a positive bonding method for electrically connecting the electrode of the second semiconductor chip to the electrode of the chip mounting member, wherein the planar dimension of the first semiconductor chip is the second. It is larger than the plane dimension of a semiconductor chip, and the thickness of a said 2nd insulating film is thicker than a said 1st insulating film, The semiconductor device characterized by the above-mentioned. The semiconductor device according to claim 12, wherein the chip mounting member is a lead frame, and an electrode of the chip mounting member is a lead.

Images