KR20080001157A - Bit line contact hole formation method using amorphous carbon layer - Google Patents

Abstract

The present invention provides a method for forming a bit line contact hole of a semiconductor device capable of simultaneously preventing photoresist margins and pattern distortion. The method of forming a bit line contact hole of a semiconductor device of the present invention includes a cell region and a peripheral circuit region. Forming an interlayer insulating film over the defined semiconductor substrate; And sequentially forming bit line contact holes in the cell region and the peripheral circuit region by an etching process using an amorphous carbon layer pattern as a hard mask. The above-described present invention provides a photosensitive film by using an amorphous carbon layer and PETEOS. It is possible to prevent margin shortage and pattern distortion of BLC1 and 2 at the same time, thereby improving reliability of the semiconductor device.

Description

Bit line contact hole formation method using an amorphous carbon layer {METHOD FOR FORMING BITLINE CONTACT HOLE USING AMORPHOUS CARBON LAYER}

1 illustrates a method for forming a bit line contact hole in a semiconductor device according to the prior art;

2A to 2G are cross-sectional views illustrating a method of forming a bit line contact hole in a semiconductor device according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

21 semiconductor substrate 22 gate oxide film

23 gate electrode 24 gate hard mask nitride film

25 gate spacer 26 first interlayer insulating film

27: landing plug contact 28: second interlayer insulating film

29: amorphous carbon layer 30: PETEOS

31: BLC2 Mask 32: BLC2

33: PETEOS 34: BLC1 Mask

35: BLC1

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a bit line contact hole in a semiconductor device.

As semiconductor devices are integrated at T60 (less than 60 nm), photoresist margins are an important issue when etching many layers (LPC, BL, SN, BLC, etc.).

In general, the formation of bit line contact holes in a semiconductor device manufacturing process includes bit line contact holes in a cell region (abbreviated as 'BLC1') and bit line contact holes in a peripheral circuit region (abbreviated as 'BLC2'). Divide and form twice.

1 is a view illustrating a method of forming a bit line contact hole in a semiconductor device according to the prior art.

Referring to FIG. 1, a plurality of gate lines are formed on a semiconductor substrate 11 in which a cell region and a peripheral circuit region are defined at predetermined intervals. In this case, the gate lines are formed not only in the cell region but also in the peripheral circuit region, and the gate lines are stacked in the order of the gate oxide layer 12, the gate electrode 13, and the gate hard mask nitride layer 14.

Next, after the gate spacer nitride film is deposited on the entire surface including the gate line, the gate spacer 15 is etched back to form gate spacers 15 in contact with both sidewalls of the gate line.

Next, the first interlayer insulating film 16 is deposited on the entire surface until the space between the gate lines is filled, and then the landing plug contact 17 is formed between the gate lines only in the cell region.

Next, after the second interlayer insulating film 18 is formed on the entire surface, a first bit line contact hole (hereinafter referred to as 'BLC1') for opening the surface of the landing plug contact 17 is formed in the cell region, and the peripheral circuit is formed. A second bit line contact hole (hereinafter referred to as 'BLC2') is formed in the region to open the surface of the gate electrode 13 of the gate line and open the surface of the semiconductor substrate 11.

The prior art as described above uses a photoresist mask (PR Mask) using ArF PR to form BLC1, BLC2.

However, since the prior art implements BLC1 and BLC2 using photoresist masks, there is a problem in that pattern distortion occurs due to insufficient photoresist margins and ArF PR characteristics. That is, since BLC1 and BLC2 have very large aspect ratios, the photoresist film is insufficient when implementing BLC1 and BLC2, and when ArF PR is used as the photoresist film, the ArF PR is etched due to deformation occurring during etching. After pattern distortion occurs. This pattern distortion adversely affects the contact resistance of the bit line contacts.

Such photoresist film deficiency and pattern distortion occur when the high aspect ratio of the semiconductor device including the bit line contact hole is etched.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method for forming a bit line contact hole in a semiconductor device capable of simultaneously preventing photoresist margins and pattern distortion.

A method of forming a bit line contact hole in a semiconductor device of the present invention for achieving the above object comprises the steps of forming an interlayer insulating film on the semiconductor substrate defined cell region and peripheral circuit region; And sequentially forming bit line contact holes in the cell region and the peripheral circuit region by an etching process using an amorphous carbon layer pattern as a hard mask, wherein the forming of the bit line contact holes is performed. Forming a first layer of an amorphous carbon layer pattern and a first hard mask pattern on the interlayer insulating layer; Forming a bit line contact hole in the peripheral circuit region by etching the interlayer insulating layer of the peripheral circuit region using the first layer as an etching barrier; Forming a second hard mask on a front surface of the bit line contact hole formed in the peripheral circuit area; Forming a photoresist mask for forming a bit line contact hole in the cell region by applying a photoresist film on the second hard mask; Patterning the amorphous carbon layer pattern and the second hard mask using the photoresist mask as an etch barrier to form a second layer formed of the amorphous carbon layer pattern and the second hard mask pattern on the cell region; And forming a bit line contact hole in the cell region by etching the interlayer insulating layer of the cell region using the second layer as an etching barrier, wherein the first and second hard mask patterns are formed of PETEOS. It is done.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

2A through 2G are cross-sectional views illustrating a method of forming a bit line contact hole in a semiconductor device according to an embodiment of the present invention.

As shown in FIG. 2A, a plurality of gate lines are formed on the semiconductor substrate 21 in which cell regions and peripheral circuit regions are defined at predetermined intervals. In this case, the gate lines are formed not only in the cell region but also in the peripheral circuit region, and the gate lines are stacked in the order of the gate oxide layer 22, the gate electrode 23, and the gate hard mask nitride layer 24.

Next, the gate spacer nitride film is deposited on the entire surface including the gate line and then etched back to form the gate spacer 25 in contact with both sidewalls of the gate line.

Next, after the first interlayer insulating film 26 is deposited on the entire surface until the space between the gate lines is filled, CMP (Chemical Mechanical Polishing) of the first interlayer insulating film 26 is stopped on the upper surface of the gate line. Proceed with the process. At this time, the first interlayer insulating film 26 is deposited with a thickness of 5000 kPa to 10,000 kPa.

Next, the LPC hard mask deposition, the contact mask, and the etching are sequentially performed to form contact holes (not shown), and then the contact mask strip and cleaning are performed. Subsequently, the polysilicon film is deposited on the entire surface until the contact hole is buried, and then the polysilicon film etch back process and the CMP process are sequentially performed to form the landing plug contact 27 embedded in the contact hole. . In this case, the landing plug contact 27 is formed only in the cell region.

As shown in FIG. 2B, after the BPSG is deposited on the entire surface of the second interlayer insulating film 28, the amorphous carbon layer 29 and the PETEOS 30 are sequentially formed on the second interlayer insulating film 28. Here, the amorphous carbon layer 29 and the PETEOS 30 is a material acting as a hard mask, the PETEOS 30 serves as a hard mask for patterning the amorphous carbon layer 29, and the amorphous carbon layer 29 is It serves as a hard mask for etching the second interlayer insulating film 28 and the first interlayer insulating film 26.

As shown in FIG. 2C, after the BLC2 mask 31 using the photoresist film is formed on the PETEOS 30, the PETEOS 30 and the amorphous carbon layer 29 are etched using the BLC2 mask 31 as an etching barrier. . At this time, the BLC2 mask 31 is consumed when the amorphous carbon layer 29 is etched, and thus the PETEOS 30 is used as a hard mask when the amorphous carbon layer 29 is etched.

After the etching process as described above, the amorphous carbon layer pattern 29a and the PETEOS pattern 30a are formed.

As shown in FIG. 2D, etching (self-aligned contact etching) for forming the BLC2 32 is performed using the amorphous carbon layer pattern 29a as a hard mask. That is, the bit line contact hole BLC2 32 is etched by etching the second interlayer dielectric layer 28 and the first interlayer dielectric layer 26 in the peripheral area using the amorphous carbon layer pattern 29a and the PETEOS pattern 30a as etch barriers. Form. In this case, since the PETEOS pattern 30a is an oxide material, the PETEOS pattern 30a is simultaneously etched when the interlayer insulating layers are etched. Therefore, the amorphous carbon layer pattern 29a serves as a hard mask when the BLC2 32 is formed.

The BLC2 32 is formed to open the surfaces of the semiconductor substrate 21 and the gate electrode 23 of the gate line in the peripheral circuit region. In this case, the second interlayer insulating film 28 and the gate hard mask nitride film 24 are etched to open the surface of the gate electrode 23, and the second interlayer insulating film 28 to open the surface of the semiconductor substrate 21. And the first interlayer insulating film 26 are etched.

In addition, during the etching process for forming the BLC2 32, a recipe having a sufficient selectivity of at least 10: 1 is set for the amorphous carbon layer pattern 29a. For example, as an etching gas, CF gas (eg, CF ₄ ) is used. A chemistry of at least one (combination of two or more) selected from the group consisting of, O ₂ , Ar, CHF-based gas (eg CHF ₃ ), CO and N ₂ is used. The above chemistry is used for self-aligned contact etching.

As shown in FIG. 2E, the PETEOS 33 is again deposited on the entire surface including the remaining amorphous carbon layer pattern 29a. Therefore, the PETEOS 33 is also formed inside the BLC2 32, and in particular, in the cell region, the stacked structure of the amorphous carbon layer pattern 29a and the PETEOS 33 is formed so that it can be used as a hard mask during the subsequent BLC1 etching process. do.

Next, a photoresist film is applied on the PETEOS 33 and patterned by exposure and development to form a BLC1 mask 34 in the cell region. At this time, the photosensitive film used as the BLC1 mask 34 remains in the form of filling the inside of the BLC2 32 in the peripheral circuit region (reference numeral 34a).

Subsequently, as shown in FIG. 2F, the PETLCOS 33 and the amorphous carbon layer pattern 29a are etched using the BLC1 mask 34. At this time, the BLC1 mask 34 is consumed when the amorphous carbon layer pattern 29a is etched, and thus the PETEOS 33 is used as a hard mask when etching the amorphous carbon layer pattern 29a.

After the etching process as described above, the amorphous carbon layer pattern 29b and the PETEOS pattern 33a in which the portion where the BLC1 is to be formed are opened are formed in the cell region. In the peripheral circuit area, all of the photosensitive film 34a used as the BLC1 mask is removed, and the inside of the BLC2 32 is filled with the PETEOS 33. In order to remove all of the photosensitive film 34a, oxygen (O ₂ ) having a high pressure (700 to 900 mTorr) and a high flow rate (200 to 400 sccm) is used during the etching process.

As a result, in the etching process for the subsequent BLC1 formation, the peripheral circuit area causes the PETEOS 33 to protect the substrates below BLC2 and BLC2 from etching.

As shown in FIG. 2G, etching (eg, self-aligned contact etching (SAC)) for forming BLC1 is performed using the amorphous carbon layer pattern 29b as a hard mask. That is, using the amorphous carbon layer pattern 29b and the PETEOS pattern 33a as an etching barrier, the second interlayer insulating film 28 in the cell region is etched to form the BLC1 35 for opening the surface of the landing plug contact 27. do. At this time, since the PETEOS pattern 33a is an oxide material, it is simultaneously etched when the second interlayer insulating film 28 is etched. Therefore, PETEOS does not remain in the cell region and the peripheral circuit region when the BLC1 35 is formed. The step for removing PETEOS may be omitted. In addition, since the PETEOS 33a is present in the BLC2 32 until the BLC1 35 is formed, the loss of the semiconductor substrate 21 under the BLC2 32 is minimized. At this time, when the BLC1 35 is formed, the substrate loss under the BLC2 32 sets a target of less than 200 GPa.

When the BLC1 35 is formed, the amorphous carbon layer pattern 29b serves as a hard mask.

The BLC1 35 is formed to open the surface of the landing plug contact 27 in the cell region. In addition, during the etching process for forming the BLC1 35, a recipe having a sufficient selection ratio of at least 10: 1 or more is set for the amorphous carbon layer pattern 29b. For example, as an etching gas, CF gas (eg, CF ₄ ) is used. A chemistry of at least one (combination of two or more) selected from the group consisting of, O ₂ , Ar, CHF-based gas (eg CHF ₃ ), CO and N ₂ is used.

Next, the remaining amorphous carbon layer pattern 29b is removed. At this time, the amorphous carbon layer pattern 29b is removed by a strip process using oxygen plasma.

According to the embodiment described above, the present invention uses an amorphous carbon layer of a single layer, and forms a BLC1, 2 structure without additional process increase, thereby preventing photoresist margins and pattern distortion generated during patterning using a conventional photosensitive film. In addition, the present invention can first form a BLC2 structure by using an amorphous carbon layer of a single layer, it is possible to minimize the substrate loss under the BLC2 during BLC1 etching.

On the other hand, as a hard mask for etching the amorphous carbon layer, other oxide film materials other than PETEOS may be used.

In addition, the present invention can be applied to all the self-aligned contact etching process in the semiconductor device manufacturing process including the contact etching process for the landing plug contact in addition to the bit line contact hole.

In addition, it can be applied to all processes using an amorphous carbon layer as a hard mask during deep contact hole etching having a high aspect ratio.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention, the amorphous carbon layer and PETEOS are used to prevent photoresist film shortage and pattern distortion of BLC1 and 2, thereby improving reliability of the semiconductor device.

Claims (7)

Forming an interlayer insulating film on the semiconductor substrate, wherein the cell region and the peripheral circuit region are defined; And Sequentially forming bit line contact holes in the cell region and the peripheral circuit region by an etching process using an amorphous carbon layer pattern as a hard mask Bit line contact hole forming method of a semiconductor device comprising a. The method of claim 1, Forming the bit line contact hole, Forming a first layer of an amorphous carbon layer pattern and a first hard mask pattern on the interlayer insulating layer; Forming a bit line contact hole in the peripheral circuit region by etching the interlayer insulating layer of the peripheral circuit region using the first layer as an etching barrier; Forming a second hard mask on a front surface of the bit line contact hole formed in the peripheral circuit area; Forming a photoresist mask for forming a bit line contact hole in the cell region by applying a photoresist film on the second hard mask; Patterning the amorphous carbon layer pattern and the second hard mask using the photoresist mask as an etch barrier to form a second layer of the amorphous carbon layer pattern and the second hard mask pattern on the cell region; And Forming a bit line contact hole in the cell region by etching the interlayer insulating layer of the cell region using the second layer as an etching barrier Bit line contact hole forming method of a semiconductor device comprising a. The method of claim 2, And the first and second hard mask patterns are formed of an oxide film. The method of claim 3, And the first and second hard mask patterns are formed of PETEOS. The method of claim 2, Forming a bit line contact hole in the cell region and the peripheral circuit region, And etching using a recipe having a selectivity of at least 10: 1 with respect to the amorphous carbon layer pattern. The method of claim 5, Etching gas in the recipe, A method of forming a bit line contact hole in a semiconductor device using at least one chemistry selected from the group consisting of CF gas, O ₂ , Ar, CHF gas CO and N ₂ . The method of claim 2, Forming the second layer, When the amorphous carbon layer and a pattern etching method to form the bit line contact hole of a semiconductor device characterized by using an oxygen (O ₂₎ of the high flow rate of the high pressure and at least at least 200~400sccm 700~900mTorr such that remove all the photoresist mask .

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