KR20070089386A - Transaction ID width conversion apparatus and method - Google Patents

Abstract

The present invention relates to a transaction ID width conversion apparatus and method. The transaction ID width converting apparatus according to the present invention transmits the L-bit transaction ID to the converting unit when it is pre-converted according to whether or not the input L-bit transaction ID is converted. An allocator for transmitting the L-bit transaction ID to a designation unit if not; A designation unit for designating an S-bit transaction ID corresponding to the L-bit transaction ID and transmitting the S-bit transaction ID to the transform unit together with the L-bit transaction ID, and transmitting the L-bit transaction ID to an inverse transform unit; A conversion unit converting the L bit transaction ID into the S bit transaction ID and outputting the converted S bit transaction ID; An inverse transform unit which inversely converts the S-bit transaction ID into a corresponding L-bit transaction ID when the pre-converted S-bit transaction ID is input; And a control unit controlling the allocation unit and the designation unit according to the number of inverse transformations of the same transaction ID.

Description

Apparatus and method for transaction ID width conversion}

BRIEF DESCRIPTION OF THE DRAWINGS In order to understand the drawings referred to in the detailed description of the invention, a brief description of each drawing is provided.

1 is a transaction flow diagram inside an SoC including multiple switch nodes.

FIG. 2 is a diagram interconnecting the switch nodes 1,2 shown in FIG.

3 is a diagram illustrating a configuration of a transaction ID width conversion device according to the present invention.

4 is a diagram illustrating tables present in the transaction ID width conversion apparatus according to the present invention.

5 is a view showing that the transaction ID width conversion apparatus according to the present invention is installed outside the switch node.

6 is a view showing that the transaction ID width conversion apparatus according to the present invention is installed inside the switch node.

7A is a flowchart illustrating an embodiment of a transaction ID width conversion method according to the present invention.

7B is a flowchart illustrating another embodiment of a transaction ID width conversion method according to the present invention.

<Description of Reference Number in Drawing>

10: allocation unit 15: allocation table

20: designation part 25: designation table

30: conversion unit 35: conversion table

40: inverse transform unit 45: inverse transform table

50: control unit 100: master

200: switch node 250: switch node 1

260: switch node 2 270: switch node 3

280: switch node 4 300: transaction ID width conversion device

400: Slave

The present invention relates to a device for converting a transaction ID width and a method for converting the same, and particularly, in an architecture supporting multiple outstanding transactions, when transmitting a transaction between cores, a transaction ID is used. The present invention relates to a transaction ID width conversion apparatus and a conversion method thereof for maintaining a constant width.

System on chip (SoC), which combines all functions such as memory and non-memory, analog and digital components, H / W and S / W into one system, is one step further from the existing semiconductor technology. It is recognized as a whole of various IT (Information technology) technology.

These SoCs use a bus to effectively communicate with each module, which can be implemented using a shared medium, and like a cross bar switch, between each master and slave. You can also connect directly.

Cascaded buses can be used to connect numerous cores in complex SoCs, where each bus acts as a switch node. Hereinafter, the bus will be used as a switch node.

Traditionally, switch nodes typically process incoming transactions in-order. Recently, out-of-order processing has emerged (see ARM PL300 TRM, AMBA AXI Definition)

In this new approach, there can be multiple outstanding transactions, so the ID is used to distinguish each transaction. This ID is usually called a transaction ID. The transaction ID is determined by the number of masters. If there are 2 ^L masters, the L bits are used to distinguish the transactions occurring in each master. For example, if there are 8 masters, 3 bits can distinguish the transaction IDs of all masters.

The switch node determines the location of the slave where the incoming transaction is reached and controls the flow of the transaction. Since the transaction input to one switch node depends on the input terminal of the switch node, one switch Each time a node passes, new information is added to each transaction ID to distinguish between input terminals. For example, if a transaction is sent from one of four masters to one switch node, the transaction ID width at the switch node output terminal is increased by two bits.

Therefore, when the switch node is cascaded (cascade), it is obvious that the width of the transaction ID must increase continuously from the master to the slave. In addition, the asymmetric ID width across the switching nodes makes the interconnection between the switch nodes impossible. This means that a more complex process is required when designing a system with multiple switch nodes. In addition, it is difficult to add / remove cores or switch nodes during system design. That makes design changes more difficult.

The present invention has been made to solve the above problems, in the communication between the cores in the SoC, when the transaction ID width is changed due to a plurality of transactions passing through one or more switch nodes, It is an object of the present invention to provide an apparatus and method for translating a transaction ID width, which can prevent a phenomenon in which the transaction ID width is excessively increased by converting it back to the original ID width and making the design change of the system easy.

Another object of the present invention, if there is a response to the transaction, by restoring the previously converted transaction ID width to the ID width before conversion, and outputs a transaction ID that can induce a smooth flow of the transaction It is an object of the present invention to provide a width converting apparatus and method.

Transaction ID width conversion apparatus according to the present invention,

Depending on whether or not the input L-bit transaction ID is pre-converted, the L-bit transaction ID is transmitted to the converting unit when the L-bit transaction ID is pre-converted. An allocation unit for transmitting;

A designation unit for designating an S-bit transaction ID corresponding to the L-bit transaction ID and transmitting the S-bit transaction ID to the transform unit together with the L-bit transaction ID, and transmitting the L-bit transaction ID to an inverse transform unit;

A conversion unit converting the L bit transaction ID into the S bit transaction ID and outputting the converted S bit transaction ID;

An inverse transform unit which inversely converts the S-bit transaction ID into a corresponding L-bit transaction ID when the pre-converted S-bit transaction ID is input; And

And a control unit controlling the allocation unit and the designation unit according to the number of inverse transformations of the same transaction ID.

The allocator may include an allocation table including 2 ^L × N bit entries for recording whether the input L bit transaction ID is converted and the number of conversions.

In addition, when the same previously converted transaction ID is re-entered, an entry value of a transaction ID of the corresponding allocation table may be increased according to the number of inputs.

The designation unit may include a designation table including two ^S entries for designating an S-bit transaction ID corresponding to the L-bit transaction ID.

The designation unit may assign an entry of the designation table according to an input order of the L-bit transaction ID, and designate an index of the entry as an S-bit transaction ID.

The conversion unit may include a conversion table configured with an entry of 2 ^L × S bits for converting the L bit transaction ID into a corresponding S bit transaction ID.

The inverse transform unit may include an inverse transform table composed of 2 ^S × L bit entries for recording an L bit transaction ID corresponding to the S bit transaction ID.

The controller may decrease an entry value of the corresponding transaction ID of the allocation table corresponding to the number of inverse transformations of the same transaction ID.

When the entry value of the corresponding transaction ID of the allocation table becomes 0, the entry value of the designated table that converts the S-bit transaction ID input to the inverse conversion unit into an index is converted to 0. You can.

Preferably, the L bit has a larger value than the S bit.

The transaction ID width conversion device is preferably installed inside the switch node.

Transaction ID width conversion method according to the present invention,

Depending on whether or not the input L-bit transaction ID is pre-converted, the L-bit transaction ID is transmitted to the converting unit when the L-bit transaction ID is pre-converted. Transmitting;

Designating an S-bit transaction ID corresponding to the L-bit transaction ID and transmitting the S-bit transaction ID together with the L-bit transaction ID to the transform unit, and transmitting the L-bit transaction ID to the inverse transform unit;

Converting the L bit transaction ID into the S bit transaction ID and outputting the converted S bit transaction ID;

Inversely converting the S-bit transaction ID into a corresponding L-bit transaction ID and outputting the pre-converted S-bit transaction ID; And

And controlling the allocation unit and the designation unit according to the number of inverse transformations of the same transaction ID.

In the determining of whether or not the pre-transformation is performed, an allocation table including 2 ^L × N bits of entry may be used.

In addition, when the same previously converted transaction ID is re-entered, an entry value of the corresponding transaction ID of the allocation table may be increased according to the number of inputs.

The step of specifying the S-bit transaction ID corresponding to the L-bit transaction ID may use a designation table composed of 2 ^S entries.

In addition, an entry of the designation table may be given according to the input order of the L-bit transaction ID, and an index of the entry may be designated as an S-bit transaction ID.

The conversion of the L-bit transaction ID to the S-bit transaction ID may use a conversion table composed of 2 ^L × S bit entries.

Inverting the S-bit transaction ID into a corresponding L-bit transaction ID may use an inverse transformation table composed of 2 ^S × L bit entries.

And controlling the allocation unit decreases an entry value of a corresponding transaction ID of the allocation table corresponding to the number of inverse transformations of the S-bit transaction ID.

The controlling of the designation unit may include: when the entry value of the corresponding transaction ID of the allocation table becomes 0, the entry number of the designation table using the pre-converted S-bit transaction ID as an index. You can convert the entry value to O.

Preferably, the L bit has a larger value than the S bit.

                                                                                                                                                                                            Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In describing the present invention, if it is determined that the detailed description of the related well-known configuration or function may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

Prior to describing the present invention, a flow of transactions and interconnected switch nodes in a System on Chip (SoC) including a plurality of switch nodes will be described in detail.

1 is a transaction flow diagram inside an SoC including multiple switch nodes.

As shown in FIG. 1, a system on chip (SoC) may include a master 100, a plurality of switch nodes 250, 260, 270, and 280, and a slave 400 therein.

Master (M ₁ ‥‥ M _n ) may exist up to n, and due to a certain communication pattern, the masters (M ₁ , M ₂ ) at the top are mainly slaves (S ₁ ) at the top through the switch node 1 (250) at the top. The masters (M _{n -1} , M _n ) at the bottom mainly transmit the transaction to the slave (S _n ) at the bottom through the switch node 2 (260) at the bottom. These switch nodes 250, 260 may be directly connected to the slave 400, but may be connected to other switch nodes 270, 280 as shown in FIG. 1.

In this case, since two transactions are input to the switch nodes 1 and 2 (250, 260), respectively, the switch nodes 1, 2 (250, 260) need two input terminals for receiving the transaction, and thus, the switch node 1, Transactions passing 2 (250, 260) are charged with the transaction ID, respectively, with one bit of data identifying the input node of the passing switch node. For example, if the transaction ID width input to one switch node is 1 bit, the output transaction ID width is 2 bits.

Similarly, since there are two transactions input to each of the switch nodes 3 and 4 (270, 280), an additional 1 bit is required to identify the input end of each transaction, and eventually 2 input from the switch nodes 1 and 2 (250, 260). The bit transaction ID width is 3 bits at the output. That is, the transaction ID width increases as the transaction passes through the switch nodes 250, 260, 270, and 280.

FIG. 2 is a diagram interconnecting the switch nodes 1,2 shown in FIG.

As described above, when the transaction ID width input to the switch nodes 1 and 2 (250, 260) is 2 bits, since 4 transactions are input to each switch node 200, each switch node 200 ), The transaction ID width is increased to 4 bits.

If a transaction must also be sent to slaves 400 at different locations, one of the outputs of switch node 1 250 is connected to the input of switch node 2 260 and vice versa. However, in this case, since the transaction ID widths of the input and output terminals are different, there is a problem that it is difficult to interconnect them because they cannot be corrected.

Accordingly, in order to solve this problem, each master is connected to each slave using one large switch node, or a plurality of switch nodes are used to connect each other. But this is clearly inefficient.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

3 is a diagram showing the configuration of a transaction ID width conversion apparatus according to the present invention, and FIG. 4 is a diagram showing tables existing within the transaction ID width conversion apparatus according to the present invention.

Referring to FIG. 3, the transaction ID width conversion apparatus 300 according to the present invention includes an assignment unit 10, a designation unit 20, a conversion unit 30, an inverse conversion unit 40, and a control unit 50. have.

Referring to Fig. 4, the allocation table 15, the assignment table 25, the conversion table 35, and the inverse conversion table 45 are disclosed.

When the L-bit transaction ID is input to the input terminal, the allocator 10 determines whether to pre-convert the input L-bit transaction ID. Determination of whether or not pre-conversion can be performed using the allocation table 15 installed in the allocation unit 10. The allocation table 15 may be configured with 2 ^L entries in order to determine whether to pre-convert all L-bit transaction IDs input to one input terminal. This is because the number of transaction IDs that can be implemented in L bits can be up to 2 ^L.

Here, the index of the allocation table 15 is a concept corresponding to the input L-bit transaction ID and has the same number. Each entry of the allocation table 15 has only one value of 1 or 0, and 0 if the corresponding transaction ID has never been converted, and 1 if it has been converted.

In addition, the allocation table 15 may be configured with an entry of 2 ^L × N bits to record the number of conversions of each transaction ID. The N bits are for indicating the number of pre-translations of the same transaction ID. When the same previously converted transaction ID is re-entered, the entry value of the transaction ID of the corresponding allocation table may increase according to the number of inputs.

If the entry value (entry value) of the specific transaction ID entered is 0, it means that a specific transaction ID is entered for the first time and thus new designation is required. Therefore, the allocation unit 10 transmits the transaction ID to the designation unit 40.

However, if the entry number is 1 or more, it means that the same transaction ID is previously input. Therefore, since the transaction ID is transmitted to the conversion unit 30 and converted using the previously stored data, redesignation is not necessary.

The designator 20 is connected to the assigner 10. The designation unit 20 designates an S-bit transaction ID corresponding to the L-bit transaction ID transmitted from the allocation unit 10 and transmits the S-bit transaction ID to the conversion unit 30 together with the L-bit transaction ID. The inverse transformation unit 40 transmits.

The designation unit 20 may perform its function through the designation table 25 installed therein. Designation table 25 is preferably composed of 2 ^S entries (Entry) to specify the S-bit transaction ID corresponding to the L-bit transaction ID. As a result, the 2 ^S entries may represent all S-bit transaction IDs. In this case, it is preferable that the L bit has a larger value than the S bit.

The designator 20 assigns an entry of the designation table 25 according to the input order of the L-bit transaction ID, and designates an index of the entry as an S-bit transaction ID. In this case, the S-bit transaction ID is irrelevant to the actual L-bit transaction ID and merely means an arbitrary transaction ID given according to the input order of the L-bit transaction ID. The index simply means the number of an entry, and this index itself is designated as an S-bit transaction ID.

The designation unit 20 designates an S-bit transaction ID corresponding to the input L-bit transaction ID, and then transmits the S-bit transaction ID to the conversion unit 30 together with the L-bit transaction ID, and the L-bit transaction ID is inversely transformed. Transfer to section 30. After that, the entry value (Entry value) of the corresponding transaction ID in the designation table 25 is increased by 1, indicating that the S-bit transaction ID corresponding to the specific L-bit transaction ID is designated.

The conversion unit 30 is connected to the allocation unit 10 and the designation unit 20, receives the L-bit transaction ID and the corresponding S-bit transaction ID from the designation unit 20, and converts the L-bit transaction ID into the S-bit. Convert to transaction ID.

The conversion unit 30 preferably includes a conversion table 35 composed of 2 ^L × S bit entries for converting the L bit transaction ID into the corresponding S bit transaction ID. For this reason, the conversion unit 30 can convert the L-bit transaction ID into the S-bit transaction ID in the input order using the conversion table 35. Herein, the S-bit transaction ID means an index of the designation table 25.

The inverse transform unit 40 converts the S-bit transaction ID to the original L-bit transaction ID when the transaction ID pre-converted from L bit to S bit is input, that is, when there is a response to the transaction. It converts to and outputs. This can lead to a smooth flow of transactions.

The reason for the inverse transformation as described above is, for example, to cause the slave 400's response to the transaction sent by the master 100 to be returned back to the exact master 100 position where the original transaction was sent. The inverse transform unit 40 contains information about the original L-bit transaction ID received from the designation unit 20.

The inverse transform unit 40 includes an inverse transform table 45 composed of 2 ^S × L bit entries to record the original L bit transaction ID corresponding to the S bit transaction ID transmitted from the designation unit 20. can do. Using this, if an S-bit transaction ID is input, it can be converted into an L-bit transaction corresponding thereto.

The controller 50 is connected to the inverse transform unit 40, the allocation unit 10, and the designation unit 20, and controls the allocation unit 10 and the designation unit 20 according to the number of inverse transformations of the same transaction ID. do.

As described above, when the same pre-converted L-bit transaction ID is input to the allocator 10, the allocator 10 sets the entry value of the L-bit transaction ID to 1. Increment the entry value according to the number of times the same L-bit transaction ID is entered.

However, when the response to the transaction is completed, since there is no need to continue using the S-bit transaction ID corresponding to the L-bit transaction ID, the control unit 50 is responsible for removing the assignment.

The controller 50 may perform two functions.

First, when a specific converted S bit transaction ID is restored to the original L bit transaction ID through the inverse transform unit 40, it is detected and an entry of the specific L bit transaction ID in the allocation table 15 is detected. A function of decreasing the entry value corresponding to the number of restorations is performed. As a result, it is possible to accurately record the number of responses to the same transaction.

Second, when the entry value of the specific L-bit transaction in the allocation table 15 becomes 0, the entry of the designation table 15 which sets the S-bit transaction ID input to the inverse transform unit as an index. Converts an entry value to 0. For this reason, the designation unit 20 may designate an S-bit transaction ID corresponding to the newly input L-bit transaction ID.

5 is a view showing that the transaction ID width conversion apparatus according to the present invention is installed outside the switch node.

Referring to FIG. 5, two 2-bit transaction IDs pass through the switch node, and are converted into 3-bit transaction IDs, respectively. Thereafter, the 3-bit transaction ID is converted into the original bit, 2 bits, as it passes through the transaction ID width conversion apparatus 300. In other words, the transaction ID width before passing through the switch node 200 is maintained.

 Therefore, even if a plurality of switch nodes are interconnected, the transaction ID width is always fixed, making it easy to connect, and since the switch node is configured as a separate component, it is possible to use a conventional switch node as it is, and it is more economical than efficacy. It is easy to adjust the transaction ID width selectively for each master or slave.

6 is a view showing that the transaction ID width conversion apparatus according to the present invention is installed inside the switch node.

Referring to FIG. 6, two 2-bit transaction IDs are inputted to the input terminal of the switch node 200, and are converted into 3-bit transaction IDs, respectively. Thereafter, the 3 bit transaction ID is converted into 2 bits which are original bits and outputted to the output terminal as it passes through the transaction ID width conversion apparatus 300 installed in the switch node 200. That is, the transaction ID width before passing through the switch node 200 is maintained.

Because of this, there is no need to make a transaction ID width conversion device as a separate component. Therefore, the area of the SoC (System on chip) can be prevented and the fixed transaction ID width can be maintained even if the switch node is added / deleted during system design. It is easy to change the design because it can be maintained, and can be integrated with the switch node to improve the implementation characteristics of the circuit.

7 is a flowchart illustrating an embodiment of a transaction ID width conversion method according to the present invention.

When the L-bit transaction ID is inputted to request the conversion to the S-bit transaction ID (S1), the allocator 10 determines whether the L-bit transaction ID is already assigned. This can be done through an allocation table consisting of 2 ^L × N entries.

The initial allocation is determined based on an entry value of the corresponding transaction ID in the allocation table 15 (S2). At this time, if the entry value is 0, it means unassigned. If it is 1 or more, it means default assignment.

If the entry value (Entry value) is 1 or more, since the received L-bit transaction ID is pre-assigned, the allocation unit 10 sends a permission signal (S2-1), and the allocation table entry number of the transaction ID. After increasing the entry value by 1 (S2-2), the L-bit transaction ID is transmitted to the conversion unit 30. Thereafter, the conversion unit 30 converts the input L-bit transaction ID into an S-bit transaction ID (S2-3).

However, if the entry value is 0, it means unassigned, so a new assignment must be made. The allocator 10 transmits the input L-bit transaction ID to the designation unit 20. The assignment may be made through an assignment table 25 composed of 2 ^S entries. In this case, the L bit is preferably larger than the S bit.

The designation unit 20 sequentially searches for empty entries (Entry) of the designation table (S3). If there is no empty entry in the designation table 25, that is, if the entry value is all 1, a new transaction ID cannot be given, and therefore a reject signal is sent (S3). -One).

When there is an empty entry in the designation table 25, the index of the first empty entry is detected (S4), and a permission signal is sent (S5). After that, the value of the first empty entry in the designation table 25 is recorded as 1 (S6). In addition, the entry value (Entry Value) of the allocation table 15 of the transaction ID is recorded as 1 (S7).

Thereafter, the index of the first empty entry is transmitted to the converter 30 along with the original transaction ID (S7). Then, the transaction ID input to the allocator 10 is transmitted to the inverse transform unit 40 (S8). In this case, the conversion unit 30 is an entry of 2 ^L x S bits, and the inverse conversion unit 40 is preferably composed of an entry of 2 ^L x L bits. The L-bit transaction ID input to the allocation unit 10 is converted by the conversion unit 30 into an S-bit transaction ID which is an index of an entry of the designation table (S9).

7B is a flowchart illustrating another embodiment of a transaction ID width conversion method according to the present invention.

When the transaction ID pre-converted from the L bit to the S bit is input and requests a conversion to the L bit transaction ID (S11), the inverse transform unit 40 sends a signal for allowing the conversion (S12) and the inverse transform table Through S45, the S-bit transaction ID is converted into the original L-bit transaction ID (S13).

Thereafter, the controller 50 detects whether the corresponding transaction ID is inversely transformed, and reduces the entry value of the corresponding transaction ID in the allocation table 15 according to the number of inverse transformations.

If the entry value (Entry value) of the allocation table 15 is 0, the control unit 50 detects this, the entry number of the designation table 25 that uses the input S-bit transaction ID as the index (Index) Convert the entry value to 0. This means that all responses have been made to the transaction, and to specify a new S-bit transaction ID when a new L-bit transaction ID is entered.

In the above described the present invention with reference to the specific embodiment shown in the drawings, but this is only an example, those of ordinary skill in the art to which the present invention pertains various modifications and variations therefrom. Therefore, the protection scope of the present invention should be interpreted by the claims to be described later, and all the technical ideas within the equivalent and equivalent ranges should be construed as being included in the protection scope of the present invention.

As described above, the present invention has the following effects.

First, the ID width can be prevented from increasing as the transaction passes through multiple switch nodes, so that even if a core or switch node is added / deleted during the design of the system including the switch node, it is easy to change the design of the system. Can be.

Second, when designing a system by interconnecting multiple switch nodes, each transaction ID width can be kept constant, so that the connection between switch nodes is easy and the ID width can be selectively adjusted for each master or slave. It is easy.

Third, in the case of integrating and implementing a transaction ID width conversion device into a switch node, it is not necessary to make a separate component, and thus does not increase the circuit area and does not require a complicated process in system design.

Claims (21)

Depending on whether or not the input L-bit transaction ID is pre-converted, the L-bit transaction ID is transmitted to the converting unit when the L-bit transaction ID is pre-converted. An allocation unit for transmitting; A designation unit for designating an S-bit transaction ID corresponding to the L-bit transaction ID and transmitting the S-bit transaction ID to the transform unit together with the L-bit transaction ID, and transmitting the L-bit transaction ID to an inverse transform unit; A conversion unit converting the L bit transaction ID into the S bit transaction ID and outputting the converted S bit transaction ID; An inverse transform unit which inversely converts the S-bit transaction ID into a corresponding L-bit transaction ID when the pre-converted S-bit transaction ID is input; And And a control unit for controlling the allocation unit and the designation unit according to the number of inverse transformations of the same transaction ID. The transaction ID width conversion method of claim 1, wherein the allocation unit comprises an allocation table including ^2L × N bit entries for recording whether the input L-bit transaction ID is converted and the number of conversions. Device. The transaction ID width conversion according to claim 2, wherein the entry value of the transaction ID of the corresponding allocation table is increased according to the number of times when the same converted transaction ID is re-entered. Device. The apparatus of claim 1, wherein the designation unit comprises a designation table including 2 ^S entries for designating an S-bit transaction ID corresponding to the L-bit transaction ID. The method of claim 4, wherein the designation unit assigns an entry of the designation table according to an input order of the L-bit transaction ID, and designates an index of the entry as an S-bit transaction ID. A transaction ID width conversion device. The transaction ID width of claim 1, wherein the conversion unit comprises a conversion table configured with an entry of 2 ^L × S bits for converting the L bit transaction ID into a corresponding S bit transaction ID. Converter. The transaction ID width of claim 1, wherein the inverse transform unit comprises an inverse transform table composed of 2 ^S × L bit entries for recording an L bit transaction ID corresponding to the S bit transaction ID. Converter. The apparatus of claim 2, wherein the controller decreases an entry value of the corresponding transaction ID of the allocation table corresponding to the number of inverse transformations of the same transaction ID. The entry value of the specified table according to claim 8, wherein when the entry value of the corresponding transaction ID of the allocation table becomes 0, the entry value of the designation table of which the S-bit transaction ID input to the inverse transform unit is an index. I) to 0. The apparatus of claim 1, wherein the L bit has a larger value than that of the S bit. The apparatus of claim 1, wherein the transaction ID width conversion device is installed inside a switch node. Depending on whether or not the input L-bit transaction ID is pre-converted, the L-bit transaction ID is transmitted to the converting unit when the L-bit transaction ID is pre-converted. Transmitting; Designating an S-bit transaction ID corresponding to the L-bit transaction ID and transmitting the S-bit transaction ID together with the L-bit transaction ID to the transform unit, and transmitting the L-bit transaction ID to the inverse transform unit; Converting the L bit transaction ID into the S bit transaction ID and outputting the converted S bit transaction ID; Inversely converting the S-bit transaction ID into a corresponding L-bit transaction ID and outputting the pre-converted S-bit transaction ID; And And controlling the allocator and the designator according to the number of inverse transforms of the same transaction ID. 13. The method of claim 12, wherein the step of determining whether or not the pre-conversion is performed using an allocation table composed of entries of 2 ^L x N bits. 15. The transaction ID width of claim 13, wherein when the same transaction ID, which has been previously converted, is re-entered, an entry value of the corresponding transaction ID of the allocation table is increased according to the number of inputs. Converter. The method of claim 12, wherein the step of specifying the S-bit transaction ID corresponding to the L-bit transaction ID uses a designation table composed of 2 ^S entries. The method of claim 15, wherein an entry of the designation table is given according to the input order of the L-bit transaction ID, and an index of the entry is designated as an S-bit transaction ID. How to convert transaction ID width. The method of claim 12, wherein the converting the L-bit transaction ID to the S-bit transaction ID uses a conversion table composed of 2 ^L × S bit entries. The method of claim 12, wherein inversely converting the S-bit transaction ID into a corresponding L-bit transaction ID uses an inverse transform table composed of 2 ^S × L bit entries. The method of claim 13, wherein the controlling of the allocation unit decreases an entry value of a corresponding transaction ID of the allocation table corresponding to the number of inverse transformations of the S-bit transaction ID. . 20. The method of claim 19, wherein the controlling of the designation unit comprises: when the entry value of the corresponding transaction ID of the allocation table becomes O, the pre-converted S-bit transaction ID is indexed. A transaction ID width conversion method, comprising: converting an entry value of the specified table into O; 13. The method of claim 12, wherein the L bit has a larger value than the S bit.

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