KR20070061236A - Quality of Service Switched Router System - Google Patents

Abstract

The present invention discloses a quality guaranteed switched router system.

According to the present invention, an Internet Protocol or a Multi-Protocol Label Switch packet selectively received through a line interface of 10 ports of 1 Gigabit Ethernet or 10 ports of m Gigabit Ethernet is applied. Download the boot process and the software load data of the first and second line processing unit and the first and second line processing unit to perform flow-based processing for each, and collect management information from the first and second line processing units to collect alarms, logs, statistics, System management including performance monitoring, including application processing unit that provides external interface for system management, asynchronous transmission method by providing switching and routing of speed in 20 Gbps full-duplex. Is a flow that combines the quality of service and the scalability and universality of Internet protocols. It can provide flow-based packet classification and intelligent congestion control by unit transmission method, so it is possible to construct QoS guaranteed network without changing existing internet access network when constructing broadband convergence network. That provides the benefits.

Description

Switched router system with QoS guaranteed}

1 is a block diagram illustrating a configuration of a quality guaranteed switched router system according to the present invention.

2 is a block diagram showing an example of a detailed configuration of a quality guaranteed switched router system according to the present invention.

* Explanation of symbols for the main parts of the drawings

11: first line processing unit

12: second line processing unit

13: application processing unit

111: Ethernet physical layer processing unit of the first line processing unit

112: Ethernet medium connection control unit of the first line processing unit

113: Ethernet frame processing unit of the first line processing unit

114: flow-based packet processing unit of the first line processing unit

115: Store & forward switch of the first line processing unit

116: control path processing unit of the first line processing unit

121: Ethernet physical layer processing unit of the second line processing unit

122: Ethernet medium access control section of the second line processing section

123: Ethernet frame processing unit of the second line processing unit

124: flow-based packet processing unit of the second line processing unit

125: Store & forward switch of the second line processing unit

126: control path processing unit of the second line processing unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a network system, and more particularly, to a service quality guaranteed switch router system capable of routing in view of quality on a network.

The conventional router of the access internet network is a packet-based transmission method using limited CoS-based DiffServ (Differentiated Service) and TE (Traffic Engineering: Quality Improvement through Load Balancing). There is a problem that the classification of each traffic flow is not sufficient and most traffic is treated the same because it is not flexible enough to apply traffic management to each flow when congestion occurs.

The technical problem to be solved by the present invention is to solve the above problems, by classifying packets received through the access Internet network into flows for each application to determine the flow type and to use a predefined bandwidth based on this By providing a quality of service switched router system that can provide QoS (Quality of Service) of the exchange technology level of the asynchronous transmission method to allow the user only when the quality can be guaranteed.

According to the present invention for solving the above technical problem, the service quality guaranteed switch router system, the Internet protocol (Internet Protocol) selectively received via the line interface of m port n gigabit Ethernet or n port m gigabit Ethernet Or first and second line processing units for flow-based processing the multi-protocol label switch packet for each application; And download boot process and software load data of the first and second line processing units, collect management information from the first and second line processing units, and perform system management including alarms, logs, statistics, and performance monitoring. It includes an application processing unit for providing an external interface that can manage the; 2 xmxn Gbps full-duplex (Full-duplex), characterized in that the output by providing the line switching and routing.

At this time, the first and second line processing unit equally through the reverse process of flow-based processing of the Internet Protocol or Multi-Protocol Label Switch packet by application for the mxn Gbps It is desirable to process and output through the line interface of n port m gigabit Ethernet or m port n gigabit Ethernet respectively.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a configuration of a quality guaranteed switched router system according to the present invention.

The system flows application-specific Internet Protocol or Multi-Protocol Label Switch packets, optionally received through the line interface of m ports of n Gigabit Ethernet or n ports of m Gigabit Ethernet. First and second line processing units 11 and 12 for base processing; And downloading booting process and software load data of the first and second line processing units, collecting management information from the first and second line processing units, and performing system management including alarms, logs, statistics, and performance monitoring. Including an application processing unit 13 that provides an external interface for managing a system, 2xmxn Gbps full-duplex provides the speed switching and routing to output.

At this time, the first and second line processing units 11 and 12 reverse processes of flow-based processing of an Internet Protocol or Multi-Protocol Label Switch packet by application for mxn Gbps. The process is evened out and output through the line interface of m ports of gigabit Ethernet or n ports of gigabit Ethernet, respectively.

The first and second line processing units 11 and 12 may selectively process only one of n port m gigabit Ethernet line interfaces or m port n gigabit line interfaces.

For example, the value of m is 10 and the value of n is preferably 1. In this case, up to 20Gbps of bandwidth can be handled per system of FIG.

The application processing unit 13 may be mounted in any one of the first line processing unit 11 or the second line processing unit 12 in the form of an add-in card or a daughter card. Can be.

2 is a block diagram showing an example of a detailed configuration of a quality guaranteed switched router system according to the present invention. This is the detailed block of FIG. The configuration, function, and operation of FIG. 1 will be described in detail with reference to FIG. 2.

The difference between the first line processor 11 and the second line processor 12 in FIG. 2 is that the application processor 13 is included in the first line processor 11. Therefore, the following description proceeds only with respect to the first line processing unit 11 except where necessary. Although not described otherwise, the functions and operations occurring in the first line processor 11 are the same in the second line processor 12 for the same components.

The first line processor 11 configures 10 optical signals received through the 10-port 1 Gbps Ethernet line interface into a 1-bit differential serializer / deserializer interface (SI) signal group having a speed of 1.25 Gbps or vice versa. Or an Ethernet physical layer processor (111) configured to configure an optical signal received through a 10-Gbps Ethernet line interface of one port into a 4-bit differential 10 Gigabit Attachement Unit Interface (XAUI) signal group having a speed of 10.3125 Gbps or vice versa. ), The Ethernet frame is extracted from each signal group received through SI or XAUI by configuring from the Ethernet physical layer processing unit 111 and collects reception statistics information about 1 Gigabit Ethernet or 10 Gigabit Ethernet based on the frame header information obtained therefrom. And Ethernet frame-to-payload conversion from Ethernet frames to SPI4.2 at 10Gbps. Packet Interface 4 Phase 2) Signals received through SPI4.2 from the Ethernet medium access controller 112 and the Ethernet medium access controller 112 which are configured as a signal group or perform the reverse process to the Ethernet physical layer processor 111. Performs payload-to-Ethernet frame conversion in the military and re-collects receiving statistics information for each Ethernet port, and performs payload conversion based on the IP and MPLS header information, which are the second and third layers in the Ethernet frame, and then converts them to 64 at 10Gbps. SPI4.1 from the Ethernet frame processing unit 113 and the Ethernet frame processing unit 114 configured to transmit a bit SPI4.1 (System Packet Interface 4 Phase 1) signal group or the reverse process to the Ethernet medium access control unit 112. Flow is distinguished from the signal group received through 1, and the forwarding is performed by performing a lookup for each flow based on a predetermined forwarding information base (FIB). After deciding on a port, selecting a packet switching path, segmenting the packet and scheduling transmission according to the priority of each flow, it is composed of 8 port, 2.5-bit 4-bit differential fabric link interface (FLI) signal group, or vice versa. A packet segment header that performs a flow-based ingress packet processing on a signal group received from the flow-based packet processing unit 114 and the flow-based packet processing unit 114 through FLI by performing a process and transmitting the same to the Ethernet frame processing unit 113. The information belongs to the store & forward switch 125 and the application processing unit of the crossbar switch structure which extracts the information, switches to the corresponding destination port, outputs the data, and performs the reverse process and transmits the information to the flow-based packet processing unit. The boot process and the software load data (FPGA) of the first line processing unit 11 are transferred to the packet forwarding path. Information received from the FIB, and forwards packet forwarding path information to the flow-based packet processor, and delivers software load data (FPGA) to the Ethernet frame processor, or a routing protocol packet received from the flow-based packet processor 114; And a control path processor 116 which collects management information including alarms and statistical matters of each processor 111 to 115 and delivers them to the application processor 13.

In this case, the application processor downloads the boot process and software load data of the line processor to the control path processors 116 and 126 of each of the first or second line processors 11 and 12, and controls the control path processors 116 and 126. Analyze the routing protocol packet received from the RPC, construct and manage a routing information base (RIB), update the FIB based on the routing protocol packet, and transfer the FIB back to the respective control path processors 116 and 126, and from the respective control path processors It collects the management information it receives and performs system management functions including alarms, logs, statistics, and performance monitoring, and provides a path to manage it when system stacking, RS-232, 10/100 / 1000Mbps Ethernet, The interface, including the compact flash memory interface, enables external system management.

The Ethernet physical layer processing unit 111 is composed of a 1G Ethernet physical layer processing unit and a 10G Ethernet physical layer processing unit, but two physical layer processing units may not be used at the same time. Optical fiber is used as the transmission medium.

The 1G Ethernet physical layer processor converts 10 optical signals received through the 10-port 1Gbps Ethernet line interface with the external network into 10 electrical signals and converts them into 1-bit serializer / deserializer interface (SI) signals at 1.25Gbps. Each configures a total of 10 SI signal groups to be transmitted to the Ethernet medium connection 112, or performs the reverse process described above.

The reverse process is as follows: A group of 10 1.25Gbps speed 1-bit differential SI signals transmitted from the Ethernet medium connection 112 is converted and output to the 10-port 1Gbps Ethernet line interface.

The reverse processes, which are also referred to below, are processes in which signals are transmitted in a right-to-left direction in the drawing, which is an inverse process of a left-to-right process, which is an original process, and a separate description thereof will be omitted.

10G Ethernet physical layer processing unit converts one optical signal received through one port 10Gbps Ethernet line interface with external network into one electrical signal and then recovers clock data, 1:16 demultiplexing, descrambling, 66B / 64B Decode, 8B / 10B coding, and 10: 1 multiplexing are performed sequentially to form a 4-bit differential 10 Gigabit Attachment Unit Interface (XAUI) signal group with a speed of 3.125 Gbps per bit (3.125 Gbps x 4 = 10.3125 Gbps). 112, 122) or vice versa.

One signal of 10bps and 10 signals of 1Gbps can be selectively processed, and there are two innernet physical layer processing units per system according to the present invention, and each inneret physical layer processing unit can operate independently of each other. Alternatively, the Ethernet physical layer processing units 111 and 121 included in each of the second line processing units 11 and 12 may select and operate only one interface of the gigabit Ethernet line interface and the 10 gigabit Ethernet line interface, respectively. As a result, the system according to the present invention can operate with the following three line interface combinations.

1) 1 Gigabit Ethernet with 1 to 20 ports

2) 1 to 10 port Gigabit Ethernet and 1 port 10 Gigabit Ethernet

3) 2 ports 10 Gigabit Ethernet

The 1G / 10G Ethernet physical layer processing unit 111 may receive operation control or provide status information through some control signals and a serial interface of the Ethernet frame processing unit 113.

The Ethernet medium access control unit 112 extracts the Ethernet frame from the 10 SI signal groups received from the 1G Ethernet physical layer processing unit of the Ethernet physical layer processing unit 111 and based on the frame header information obtained through the 10 Gigabit Ethernet for 10 ports. Collect reception statistics. The Ethernet frame of each port is read in through 1 Gigabit Ethernet port-to-SPI4.2 (System Packet Interface 4 Phase 2) channel mapping (port 0 = channel 0, port 1 = channel 1, port 9 = channel 9). After storage in the specified area of the Ingress FIFO, Ethernet frame-to-payload conversion is performed, for example, composed of SPI4.2 signal groups of 16-bit differential signals up to 390 MHz DDR clock. Transfer to Ethernet frame processing unit 113 or vice versa.

In addition, one XAUI signal group received from the 10G Ethernet physical layer processor of the Ethernet physical layer processor 111 performs 1:10 demultiplexing, 10B / 8B decoding, and then extracts an Ethernet frame. Based on the frame header information obtained, it collects receiving statistics on 10 Gigabit Ethernet on one port, and 10 Gigabit Ethernet port-to-SPI4.2 (System Packet Interface 4 Phase 2) channel mapping (10G port = channel 0) stores Ethernet frames from 10 Gigabit Ethernet ports in a specified area of Ingress FIFO and then performs Ethernet frame-to-payload conversion, e.g., for a 390 MHz DDR clock, Composed of the SPI4.2 signal group of the bit differential signal is transmitted to the Ethernet frame processing unit 113, or vice versa.

The SPI4.2 signal group includes a 2-bit state signal of, for example, an 80 MHz clock, which checks the ingress memory state of the Ethernet frame processing unit 113 and transmits it to the Ethernet connection control unit 112.

The Ethernet frame processing unit 113 performs payload-to-Ethernet frame conversion and reacquiring reception statistics information for each Ethernet line interface port in the signal group received from the Ethernet medium access control unit 112 through SPI4.2. In addition, based on the second and third layer (IP, MPLS) header information in the Ethernet frame, Ethernet frame-to-POS (Packet over SONET) packet conversion is performed, and additionally, a payload is performed by inserting a receiver gasket header (RGH). After performing the conversion, for example, it is configured as a 64-bit SPI4.1 (System Packet Interface 4 Phase 1) signal group with a 200 MHz clock, and then transferred to the flow-based packet processing unit 114 or vice versa.

The SPI4.1 signal group includes a 5-bit state signal that checks the ingress memory state of the flow-based packet processor 114 and delivers it to the Ethernet frame processor 113.

In addition, the Ethernet frame processing unit 113 provides a control and management path between the control path processing unit 116 and the Ethernet medium access control unit 112 through a 16-bit external bus interference (EBI), the line interface port of the system according to the present invention It is possible to control the operation of the light emitting diode to visualize the operating state of.

The Ethernet frame processor 113 may be implemented through a device such as a field programmable gate array for payload generation and additional functions for the operation of the flow-based packet processor 114. It is apparent that the device implemented at this time can be used in various kinds.

The flow-based packet processor 114 performs payload-to-POS packet conversion (including the RGH header) on the signal group received through the SPI4.1 from the Ethernet frame processor 113. And it extracts the 5-tuple (Destination Addrdess, Source Address, Destination IP, Source IP, TCP Port) information for hashing and classifies the flow based on this information, for example, 512 megabytes, The packet is stored in the flow block memory, and the packet is stored in the data block memory, for example, having a capacity of 1 gigabyte.

At this time, the basic operation of the flow-based packet processor 114 is performed through the micro code received from the control path processor 116 through a 36-bit CPU bus interface (CIF) signal group, for example, at a 100 MHz rate.

A packet stored in the data block memory is performed by a lookup for each flow based on a forwarding information base (FIB) received from a control path processor 116 or 126 through a 100-MHz, 36-bit CPU bus interface (CIF) signal group. The egress port for forwarding is then determined. After selecting the packet switching path in consideration of the congestion rate of the Store & Forward switch 115, the packet is segmented into 336 byte payload (maximum value) and 28 byte header to schedule transmission according to the priority of each flow. It consists of a 4-bit differential FLI (Fabric Link Interface) signal group of Gbps speed and transmits it to the switch & forward switch 115 or vice versa. Considering congestion means preventing data from concentrating on specific ports on the store & forward switch. In other words, when data is concentrated in a specific port, data is distributed through other paths.

At this time, four of the eight port FLI store and forward switch 115 of the first line processing unit 11 which is the same line processing unit, and the remaining four ports store and forward of the second line processing unit 12 which is another line processing unit. Used to connect with switch 125.

For example, four of the eight port FLIs of the flow-based packet processing unit 114 of the first line processing unit 11 are connected to the store & forward switch 115 of the corresponding unit card module 11 and the remaining four ports. The port is connected to the store & forward switch 125 of the second line processor 12. This is to provide a switching path between two line card modules because the system according to the present invention is composed of two line processing units (11, 12).

The store & forward switch 115 extracts packet segment header information that has performed flow-based ingress packet processing from the signal group received from the flow-based packet processor 114 through FLI, refers to the corresponding destination port, and outputs it by switching. It's a 25 x 25 port crossbar switch.

At this time, four ports of the FLI of 25 ports are the flow-based packet processor 114 of the first line processor 11, five ports are the flow-based packet processor 124 of the second line processor 12, and the remaining 16 ports. The port is used to connect to other systems' Store & Forward switches when stacking systems.

For example, four of the 25 port FLI switches of the store & forward switch 115 of the first line processing unit 11 are connected to the corresponding unit flow based packet processing unit 114, and five ports are connected to the other line card module. 12 is connected to the flow-based packet processing unit 124-4 ports and the store & forward switch 125-1 port, and the remaining 16 ports are used when stacking the system.

The control path processor 116 receives the boot process and the software load data of each of the line processors 11 and 12 from the application processor 13 through the 5-bit signal group of the BSCAN (Backplane SCAN) interface to perform an initialization process. Information is transmitted to the flow-based packet processing unit 114 through the CIF signal group of 100 MHz and 36 bits, and to the Ethernet frame processing units 113 and 123 through the external bus control interface (EBI) signal group of 25 MHz and 16 bits. Deliver relevant information. In addition, the application processor 13 receives the FIB, which is packet forwarding path information, through a Sytem Control Network (SCN) interface using 10/100/1000 Mbps Ethernet, and delivers the FIB to the flow-based packet processor 114 through the CIF signal group.

The routing protocol packet received from the flow-based packet processing unit 114, 124 and the management information (alarm, statistics, etc.) of each component are collected and transmitted to the application processing unit 13 through the SCN interface.

In the case of FIG. 2, the application processor 13 exists only in the first line processor 11 and downloads the boot process and software load data of each line processor 11 and 12 through the BSCAN interface.

In addition, the application processor 13 analyzes the routing protocol packets received from the control path processors 116 and 126 of each line processor 11 and 12 through the SCN interface, constructs and manages a routing information base (RIB), and based thereon. The FIB is updated and passed back to the control path processors 116 and 126.

In addition, the management information received from the control path processing units 116 and 126 of the line processing units 11 and 12 through the SCN interface is collected to perform system management functions such as alarms, logs, statistics, and performance monitoring.

In addition to the internal SCN interface of the two ports connected to each of the line processing units 11 and 12 in the single system, the application processor 13 may stack the system through four ports of the external SCN interface for connecting the stacked systems. It provides a path to management and enables external system management through RS-232, 10/100 / 1000Mbps Ethernet, and compact flash memory interfaces.

The application processor manages packet forwarding and routing information so that when the systems are physically stacked (up to five stackables), the entire stacked systems can be operated as one logical system. At this time, the application processing part of one of the physically stacked systems becomes a master, and the application processing part of the other systems becomes a slave. The master forwarding and routing received from the slaves through an external SCN interface. After collecting and updating the relevant table information of the entire system based on the information, it delivers the relevant table information to the slave through the external SCN interface so that the entire system can operate as one system. The master and the slave determine the arbitrarily defined priority algorithm.

Conventional routers have a limited CoS (Class of Service) based packet-based transmission method, which is not enough to classify each traffic flow and is not fluid enough to apply traffic management to each flow when congestion occurs. In contrast, the present invention can provide flow-based packet classification and intelligent congestion control in a flow-based transmission method that combines the service quality of the asynchronous transmission method with the scalability and universality of the Internet protocol. Convergence Network can be used to build a Quality Service Guaranteed network without changing the existing Internet access network.

Those skilled in the art will appreciate that the present invention can be implemented in a modified form without departing from the essential features of the present invention. Therefore, the disclosed embodiments should be considered in descriptive sense only and not for purposes of limitation. Examples included in the above description are introduced for the understanding of the present invention, and these examples do not limit the spirit and scope of the present invention. It will be apparent to those skilled in the art that various embodiments in accordance with the present invention in addition to the above examples are possible. The scope of the present invention is shown not in the above description but in the claims, and all differences within the scope will be construed as being included in the present invention.

In addition, it can be easily understood by those skilled in the art that each of the above steps according to the present invention can be variously implemented in software or hardware using a general programming technique.

And some steps of the invention may also be embodied as computer readable code on a computer readable recording medium. The computer-readable recording medium includes all kinds of recording devices in which data that can be read by a computer system is stored. Examples of computer-readable recording media include ROM, RAM, CD-ROM, CD-RW, magnetic tape, floppy disks, HDDs, optical disks, magneto-optical storage devices, and carrier wave (eg, Internet It also includes the implementation in the form of). The computer readable recording medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.

According to the present invention, an Internet Protocol or a Multi-Protocol Label Switch packet selectively received through a line interface of 10 ports of 1 Gigabit Ethernet or 10 ports of m Gigabit Ethernet is applied. Download the boot process and the software load data of the first and second line processing unit and the first and second line processing unit to perform flow-based processing for each, and collect management information from the first and second line processing units to collect alarms, logs, statistics, System management including performance monitoring, including application processing unit that provides external interface for system management, asynchronous transmission method by providing switching and routing of speed in 20 Gbps full-duplex. Is a flow that combines the quality of service and the scalability and universality of Internet protocols. It can provide flow-based packet classification and intelligent congestion control by unit transmission method, so it is possible to construct QoS guaranteed network without changing existing internet access network when constructing broadband convergence network. That provides the benefits.

Claims (16)

Application-based flow-based processing of Internet Protocol or Multi-Protocol Label Switch packets selectively received through the line interface of m ports of n Gigabit Ethernet or n ports of m Gigabit Ethernet First and second line processing units; And Download the boot process and software load data of the first and second line processing unit, and collect management information from the first and second line processing unit to manage the system including alarms, logs, statistics, and performance monitoring. Including; an application processing unit for providing an external interface to manage the 2 x m x n Gbps full-duplex (Full-duplex) is a quality assurance switched router system, characterized in that the output by providing the switching and routing. The method of claim 1, The first and second line processing units equally process an mxn Gbps input through an inverse process of flow-based processing of an Internet Protocol or a Multi-Protocol Label Switch packet for each application. A quality guaranteed switched router system, each of which outputs through a line interface of n ports of m gigabit ethernet or m ports of n gigabit ethernet. The method of claim 1, The first and second line processing unit selectively processes any one of n port m gigabit Ethernet line interface or m port n gigabit line interface. The method according to claim 1 or 2, The value of m is 10, the value of n is 1 characterized in that the switched router system. The method of claim 1, The application processing unit is a quality assurance type switched router system, characterized in that mounted on any one of the first line processing unit or the second line processing unit in the form of an add-in card (add-in card). The method according to any one of claims 1 to 3 or 5, Each of the first and second line processors, The 10 optical signals received through the 10-port 1Gbps Ethernet line interface consist of a group of 1-bit differential serializer / deserializer interface (SI) signals at 1.25Gbps, or vice versa, or 10Gbps on 1 port An Ethernet physical layer processor configured to configure an optical signal received through the Ethernet line interface into a 4-bit differential 10 Gigabit Attachment Unit Interface (XAUI) signal group having a speed of 10.3125 Gbps or vice versa; Configured from the Ethernet physical layer processing unit to extract the Ethernet frame from each signal group received through the SI or XAUI, and collects receiving statistics information for 1 Gigabit Ethernet or 10 Gigabit Ethernet based on the frame header information obtained through this, and Ethernet frame Ethernet to perform Ethernet frame-to-payload conversion from SPI4.2 (System Packet Interface 4 Phase 2) signal group of 10Gbps or perform the reverse process to transfer to Ethernet Ethernet layer processing unit A medium connection control unit; Performs payload-to-Ethernet frame conversion and re-acquisition of receiving statistics information for each Ethernet port in the signal group received through SPI4.2 from the Ethernet medium access controller, and based on IP and MPLS header information, which are the second and third layers in the Ethernet frame An Ethernet frame processing unit configured to perform a payload conversion to a 64-bit System Packet Interface 4 Phase 1 (SPI4.1) signal group of 10 Gbps or perform the reverse process and transfer the same to the Ethernet media access controller; The flow is distinguished from the signal group received through the SPI4.1 from the Ethernet frame processing unit, and an egress port for forwarding is performed by performing a lookup for each flow based on a predetermined forwarding information base (FIB). After selecting the packet switching path, segment the corresponding packet and schedule transmission according to the priority of each flow to configure 8 port, 2.5 Gbps 4-bit differential fabric link interface (FLI) signal group or vice versa. A flow-based packet processor for performing the transmission to the Ethernet frame processor; From the signal group received through the FLI, the flow-based packet processing unit extracts the packet segment header information that has performed the flow-based ingress packet processing, switches to the corresponding destination port, and outputs the reverse process. A store & forward switch having a crossbar switch structure for transmitting to a packet processor; And Receives the boot process and software load data of the first or second line processing unit to which it belongs, receives the FIB, which is packet forwarding path information, transfers the relevant information to the flow-based packet processing unit, and sends the related information to the Ethernet frame processing unit. Or a control path processor configured to collect the routing protocol packet received from the flow-based packet processor and management information including alarms and statistics of each processor and transmit the collected information to the application processor. , The application processor downloads a boot process and software load data of a line processor to a control path processor of each of the first or second line processors, analyzes a routing protocol packet received from the control path processors, and a routing information base. ) A system that includes alarm, log, statistics, and performance monitoring by building and managing and updating the FIB based on this, and forwarding it back to the respective control path processing units, and collecting management information received from each control path processing unit. It provides management paths, provides a path to manage them when the system is stacked, and enables external systems to be managed through interfaces including RS-232, 10/100/1000 Mbps Ethernet, and compact flash memory interfaces. When the quality of service switched switch router Stem. The method of claim 6, The Ethernet physical layer processing unit, It converts 10 optical signals received through 10 port 1Gbps Ethernet line interface into 10 electrical signals and configures each of 1-bit serializer / deserializer interface (SI) signal group of 1.25Gbps and transmits them to Ethernet media connection. Perform the reverse process, Converts one optical signal received via one port's 10 Gbps Ethernet line interface into one electrical signal and then recovers clock data, 1:16 demultiplexing, descrambling, 66B / 64B decoding, 8B / 10B coding, 10 A service quality guaranteed switch router system comprising: 1 multiplexing sequentially and configured as a 4-bit differential XAUI signal group having a speed of 10.3125 Gbps to deliver to the Ethernet media access unit or vice versa. The method of claim 6, The Ethernet medium connection control unit, The Ethernet frame is extracted from each signal group received through the 10 SIs or 1 XAUI from the Ethernet physical layer processing unit and based on the frame header information obtained from the 10 port 1 Gigabit Ethernet or 1 port 10 Gigabit Ethernet Collects received statistics information, stores Ethernet frame in Ingress FIFO, performs Ethernet frame-to-payload conversion, and configures 16-bit differential SPI4.2 signal group of 10Gbps to the Ethernet frame processing unit. Quality of service switched router system characterized in that the forwarding or the reverse process. The method of claim 6, The Ethernet frame processing unit, Payload-to-Ethernet frame conversion and re-acquisition of reception statistics information for each Ethernet port are performed on the signal group received through SPI4.2 from the Ethernet medium access controller, and IP and MPLS header information, which is the second and third layers in the Ethernet frame, is collected. Based on Ethernet frame-to-force packet conversion and receiver gasket header (RGH) insertion, payload conversion is performed and configured as a 10-bit 64-bit SPI4.1 signal group to be transmitted to the flow-based packet processor or vice versa. Quality of service switched router system, characterized in that performing the process of. The method of claim 6, The flow-based packet processing unit, 5-tuple for hashing after performing payload to force packet conversion including RGH header in the signal group received through SPI4.1 from the Ethernet frame processor (Destination Addrdess / IP, Source Address / IP, TCP Port) information is extracted and flow is classified based on this, and this information is stored in the flow block memory, and the packet is stored in the data block memory. Determines the egress port for forwarding by performing a lookup for each flow based on the FIB received from the control path processor through a CPU bus interface (CIF) signal group, and congestion of the store & forward switch After considering packet switching path, segment the packet into maximum 336 byte payload, 28 byte header and schedule transmission according to the priority of each flow to configure 8 port, 4 bit differential FLI signal group of 2.5Gbps. Quality of service switched router system characterized in that the transfer to the switch and forward switch or vice versa. The method of claim 10, 4 ports of 8 ports FLI are to the store & forward switch included in the line processing unit when the transmission schedule is composed of 8 ports and 4 bits differential FLI signal group of 2.5 Gbps, and transmitted to the switch & forward switch. And the remaining four ports are used for connection with a store & forward switch included in another line processing unit not belonging to the service quality guaranteed switch router system. The method of claim 6, The store & forward switch, From the signal group received through the FLI from the flow-based packet processing unit extracts the packet segment header information performing the flow-based ingress packet processing process to switch to the corresponding destination port, and outputs the crossbar switch structure of the 25 x 25 port Four of the 25 ports of FLI are connected to the flow-based packet processor included in the line processor to which they belong, and the other five ports are flow-based packet processors and store and forward switches included in the other line processor to which they do not belong. The remaining 16 ports are used for connection with a store & forward switch between systems when stacking the system. The method of claim 6, The control path processing unit, The boot process and software load data required for each line processor are received from the application processor through the 5-bit signal group of the BSCAN interface, and packet forwarding path information is transmitted through the SCN (System Control Network) interface using 10/100 / 1000Mbps Ethernet. Receives the FIB and delivers the related information to the flow based packet processor through the CIF signal group, and transmits the related information to the Ethernet frame processor through the EBI (External Bus Control Interface) signal group or receives the received information from the flow based packet processor. And a routing protocol packet and management information of each component are collected and delivered to the application processing unit through an SCN interface. The method of claim 6, The application processing unit, Download the boot process and software load data to the control path processing unit of each of the first or second line processing unit through the BSCAN interface, and analyze the routing protocol packet received from the control path processing unit of each line processing unit through the SCN interface to establish RIB. And managing and updating the FIB based on the information and forwarding the FIB to the control path processor again, or collecting management information received from the control path processor of each line processor through the SCN interface to include alarms, logs, statistics, and performance monitoring. Perform system administration functions, Each of the first and second line processors further includes two ports of an SCN interface. The application processing unit is connected to each line processing unit in a single system through the two port SCN interface, and provides a path for connection between stacked systems through an additional SCN interface of four ports. Quality Assured Switched Router System. The method of claim 14, Four port SCN interface for stacking the application processor and 32 ports for stacking the store & forward switch included in each of the first or second line processor (16 ports / line processor x 2) Fabric Link Interface Quality Assured Switched Router system, characterized in that for stacking up to five systems. The method of claim 6, The Ethernet physical layer processing units included in each of the first or second line processing units may select and operate only one interface of a gigabit Ethernet line interface and a 10 gigabit Ethernet line interface, respectively. A quality guaranteed switched router capable of providing three line interface combinations of 20 ports of 1 Gigabit Ethernet or 1 to 10 ports Gigabit Ethernet and 1 port 10 Gigabit Ethernet or 2 ports 10 Gigabit Ethernet system.

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