KR20050122983A - Method for organic light eitting display by appling reverse bias - Google Patents

Abstract

The present invention relates to a method of applying reverse bias to an organic light emitting display device, the method comprising: a plurality of pixels, a plurality of data lines for applying a data signal to the plurality of pixels, a plurality of scanning lines for applying a selection signal to the plurality of pixels, and A first step of manufacturing an organic light emitting display device including first and second power lines for applying first and second power sources to a pixel; And a second for applying a negative potential to the first and second power supply lines, applying a selection signal having a high and low level potential to the scan line, and applying a data signal having a positive potential to the data line. Steps.

 Therefore, the reverse bias voltage application method of the organic light emitting diode display according to the present invention applies the reverse bias voltage to the image display device to perform an aging process, thereby reducing leakage current in the TFT of the image display device. It is possible to reduce the change in the amount of charge charged in the capacitor.

Description

Method of applying reverse bias of organic light emitting display device {METHOD FOR ORGANIC LIGHT EITTING DISPLAY BY APPLING REVERSE BIAS}

The present invention relates to a method of applying reverse bias of an organic light emitting diode display. More particularly, the present invention relates to a method of applying a reverse bias voltage to a pixel portion to minimize image degradation due to leakage current of a switching element. It relates to a reverse bias application method.

Recently, various flat panel displays have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes. As a flat panel display, an organic light emitting diode (LCD) using a liquid crystal display, a field emission display, a plasma display panel, and an organic light emitting device (hereinafter referred to as OLED) is used. And a light emitting display device.

A self-light emitting device that emits a fluorescent material by recombination of OLED electrons and holes among flat panel displays, and has the advantage of having a fast response speed, such as a cathode ray tube, compared to a light emitting device that requires a separate light source such as a liquid crystal display device. .

The anode electrode of the OLED is connected to the pixel circuit and the cathode electrode is connected to the second voltage power supply VSS. The OLED includes an emission layer (EML), an electron transport layer (ETL), and a hole transport layer (HTL) formed between the anode electrode and the cathode electrode. In addition, the OLED may further include an electron injection layer (EIL) and a hole injection layer (HIL).

In the OLED, when a voltage is applied between the anode electrode and the cathode electrode, electrons generated from the cathode electrode move toward the light emitting layer through the electron injection layer and the electron transport layer, and holes generated from the anode electrode are transferred through the hole injection layer and the hole transport layer. Move toward the light emitting layer.

Accordingly, in the light emitting layer, light is generated by collision between electrons and holes supplied from the electron transporting layer and the hole transporting layer and recombination.

1 is a circuit diagram of a pixel of an organic light emitting diode display according to the related art. Referring to FIG. 1, the pixel includes an OLED, a thin film transistor (MD), a storage capacitor (Cst), and a switching TFT (MS). The scanning line S, the data line D, and the power supply line VDD are connected to the pixel. The scanning line S is formed in the row direction, and the data line D and the power supply line VDD are formed in the column direction.

The driving TFT MD supplies a current for emitting light to the OLED. The amount of current in the driving TFT MD is controlled by the data voltage applied through the switching TFT MS.

The storage capacitor Cst is connected between the source electrode and the gate electrode of the driving TFT MD, and maintains the voltage between the source electrode and the gate electrode applied by the data voltage for a predetermined period of time.

Due to this configuration, when the switching TFT MS is turned on by the scan signal applied to the gate electrode of the switching TFT MS, the data voltage is applied to the gate electrode of the driving TFT MD through the data line DL. do.

In addition, in response to the data voltage applied to the gate electrode of the driving TFT MD, a current flows through the driving TFT MD to emit light.

The driving TFT (MD) or the switching TFT (MS) included in the above pixel is a P-type metal oxide semiconductor field effect TFT (MOSFET, Metal-Oxide Semiconductor Field Effect Transistor). The reason for using a P-type TFT is that the manufacturing process is simpler than using an N-type TFT, which is advantageous for mass-producing an organic light emitting display device.

However, the charge charged in the storage capacitor Cst may cause leakage current due to the TFTs included in the pixel, thereby reducing the voltage holding ability of the storage capacitor Cst and causing deterioration in image quality. There is a problem. In particular, the P-type TFT has a problem that the degradation of the image quality is more severe than the N-type TFT due to the larger leakage current.

In addition, a pixel has been devised to compensate for the threshold voltage of the driving TFT (MD) in order to prevent unevenness of luminance, and this method has used more P-type TFTs and capacitors than the pixel shown in FIG.

Therefore, the voltage holding capability of the capacitor is further reduced by the leakage current generated in the P-type TFTs.

Accordingly, the present invention was created to solve the problems of the prior art, and an object of the present invention is to apply a reverse bias to each P-type TFT of an organic light emitting diode display to reduce leakage current of the P-type TFT. The present invention provides a method of applying reverse bias to a display device.

In addition, another object of the present invention is to apply a reverse bias to each P-type TFT to an organic light-emitting display including pixels implemented to have a uniform luminance, thereby reducing leakage current of the P-type TFT and improving image quality. It is to provide a reverse bias application method.

In order to achieve the above object, a reverse bias applying method of an organic light emitting diode display according to the present invention includes applying a selection signal to a plurality of pixels, a plurality of data lines for applying a data signal to the plurality of pixels, and a plurality of pixels. A first step of manufacturing an organic light emitting display device including a plurality of scan lines and first and second power lines for applying first and second power to the pixels; And a second for applying a negative potential to the first and second power supply lines, applying a selection signal having a high and low level potential to the scan line, and applying a data signal having a positive potential to the data line. Steps.

Preferably, the pixel, the light emitting element; A first switching element for applying a data signal applied to the data line to the second node in response to the first selection signal applied to the first scan line; A first capacitor charging a voltage corresponding to the data signal and maintaining the same for a predetermined period of time; A driving element for flowing a current to the first node in response to the voltage charged in the first capacitor; A second capacitor compensating for a voltage difference generated in the driving device; A second switching element configured to charge the voltage corresponding to the data signal to the first capacitor in response to a second selection signal; A third switching device configured to allow the first node and the driving device to function as a diode in response to the second selection signal; And a fourth switching element responsive to a light emission signal and connected to the first node to flow a current through the light emitting element.

In the second step, preferably, a voltage in the range of -5V to -15V is applied to the first power supply line, a voltage in the range of -5V to -8V is applied to the second power supply line, and the scan line A voltage having a high level in the range of 3V to 5V and a low level in the range of -4V to -9V is applied, and a voltage in the range of 2.5V to 5V is applied to the data line.

Further, preferably, the signal applied to the first power line is an AC signal.

Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

2 is a circuit diagram illustrating a pixel of an organic light emitting diode display used in the present invention. Referring to FIG. 2, the pixel 11 of the organic light emitting display is selected when a selection signal is applied to the scan line SL, and generates light corresponding to the data signal supplied to the data line DL. .

To this end, each pixel 11 includes an OLED and a pixel circuit, and is connected to the data line D, the scan lines Sn and Sn-1, and the light emission signal line En.

The pixel circuit 40 includes the driving TFT MD connected between the first voltage power supply VDD and the OLED, the fourth switching TFT MS4 connected to the light emitting signal line EMIn and the OLED and the driving TFT MD, N; The first (where N is a positive integer) first switching TFT MS1, first switching TFT MS1 and first voltage power supply VDD connected to scan line Sn and data line D, and N- The first node N1 and the N-th scan line Sn-1 connected between the second switching TFT MS2, the driving TFT MD, and the fourth switching TFT MS4 connected to the first scan line Sn-1. And between the second node N2 and the first voltage power supply VDD, which are between the third switching TFT MS3 and the first and second switching TFTs MS1 and MS2 connected to the gate electrode of the driving TFT MD. The connected storage capacitor Cst and the compensation capacitor Cvth connected between the second node N2 and the gate electrode of the driving TFT MD are provided.

The gate electrode of the first switching TFT MS1 is connected to the Nth scan line Sn, the source electrode is connected to the data line D, and the drain electrode is connected to the second node N2. The first switching TFT MS1 supplies the data signal from the data line D to the second node N2 in response to the selection signal supplied from the scan driver (not shown) to the Nth scan line Sn. .

The gate electrode of the second switching TFT MS2 is connected to the N-th scan line Sn-1, the source electrode is connected to the first voltage power supply VDD, and the drain electrode is connected to the second node N2. do. The second switching TFT MS2 supplies the voltage from the first voltage power supply VDD to the second node N2 in response to the selection signal supplied to the N-1 scan line Sn-1.

The gate electrode of the third switching TFT MS3 is connected to the N-th scan line Sn-1, the source electrode is connected to the first node N1, and the drain electrode is connected to the gate electrode of the driving TFT MD. Connected. The third switching TFT MS3 connects the gate electrode of the driving TFT MD to the first node N1 in response to the selection signal supplied to the N-1 scan line Sn-1.

The storage capacitor Cst stores a voltage corresponding to the data signal supplied to the second node N2 via the first switching TFT MS1 in a section where the selection signal is supplied to the Nth scan line Sn. When the first switching TFT MS1 is turned off, the on state of the driving TFT MD is maintained for one frame.

The compensating capacitor Cvth stores a voltage corresponding to the threshold voltage Vth of the driving TFT MD from the first voltage power supply VDD in a section in which the selection signal is supplied to the N-1th scan line Sn-1. do. That is, the compensation capacitor Cvth stores the compensation voltage for compensating the threshold voltage Vth of the driving TFT MD according to the switching of the second and third switching TFTs MS2 and MS3.

The gate electrode of the driving TFT MD is connected to the source electrode of the third switching TFT MS3 and the compensation capacitor Cvth, the source electrode is connected to the first voltage power supply VDD, and the drain electrode is connected to the first node. It is connected to (N1). The driving TFT MD adjusts the current between its source electrode and the drain electrode supplied from the first voltage power supply VDD according to the voltage supplied to its gate electrode and supplies it to the fourth switching TFT MS4. .

The gate electrode of the fourth switching TFT MS4 is connected to the light emission signal line En, the source electrode is connected to the first node N1, and the drain electrode is connected to the anode electrode of the OLED. The fourth switching TFT MS4 emits the OLED by supplying the current supplied from the driving TFT MD to the OLED in response to the emission signal supplied from the emission signal line En.

On the other hand, the fourth switching TFT MS4 is switched by the light emitting signal supplied from the light emitting signal line En to block the flow of current to the driving TFT MD while writing the data signal.

3 is a timing diagram illustrating driving of pixels of an ideal organic light emitting diode display. Referring to FIG. 3, a T1 section in which a selection signal in a low state is supplied to the N-th scan line Sn-1 and a selection signal in a high state is supplied to the N-th scan line Sn-1. In this case, the second and third switching TFTs MS2 and MS3 are turned on, and the first switching TFT MS1 is turned off. In addition, the fourth switching TFT MS4 is turned off in the on state according to the light emission signal of the high state supplied to the light emission signal line En.

As a result, the driving TFT MD performs a diode function, and the voltage between the gate electrode and the source electrode of the driving TFT MD changes until its threshold voltage Vth is reached. Accordingly, the compensation capacitor Cvth stores the compensation voltage corresponding to the threshold voltage Vth of the driving TFT MD.

Subsequently, in the T2 section in which the selection signal in the high state is supplied to the N-th scan line Sn-1 and the selection signal in the low state is supplied to the N-th scan line Sn-1, the second and third periods. The switching TFTs MS2 and MS3 are turned off, and the first switching TFT MS1 is turned on. As a result, the data signal supplied from the data driver 30 to the data line DL is supplied to the second node N2 via the first switching TFT MS1. Accordingly, the gate electrode of the driving TFT MD is supplied with the voltage plus the variation value Vdata-VDD of the voltage of the second node N2 and the compensation voltage stored in the compensation capacitor Cvth.

In this case, the storage capacitor Cst stores the voltage change value of the second node N2.

The fourth switching TFT MS4 has a low light emission signal supplied to the light emission signal line En in a portion of a section in which a selection signal in a low state is supplied to the Nth scan line Sn. Is turned on. At this time, the driving TFT MD is turned on by the voltage added with the voltage variation value of the second node N2 and the compensation voltage stored in the compensation capacitor Cvth, and fourth switching current corresponding to the compensated data signal. Supply to TFT MS4. Therefore, the OLED emits light by the current supplied from the driving TFT MD via the fourth switching TFT MS4 to display an image.

Then, after the T2 section in which the selection signal of the high state is supplied to the Nth scan line Sn, the on state of the driving TFT MD is maintained by the data signal stored in the storage capacitor Cst, so that the OLED is held for one frame period. The light is emitted to display an image.

4 is a block diagram showing an aging system for applying a reverse bias according to the reverse bias application method according to the present invention. Referring to FIG. 4, the aging system 100 is connected to a pixel portion 10 including a plurality of pixels illustrated in FIG. 2 through a flexible printed circuit (FPC). The aging system 100 includes an anode voltage power supply unit 20, a circuit voltage power supply unit 40, a cathode voltage power supply unit 30, and a data voltage power supply unit 50.

The anode voltage power supply unit 20 is connected to the power supply line of the pixel unit 10 and applies a voltage having a value between -5V and -15V to the power supply line. In this case, the anode voltage power supply unit 20 may apply a voltage having an arbitrary size between -5V to -15V, and may also apply an AC voltage that varies within a range of -5V to -15V. In particular, applying an alternating voltage is more effective.

The cathode voltage power supply unit 30 is connected to the cathode electrode of the pixel unit 10 and applies a voltage having a value between -5V and -8V to the cathode electrode.

The circuit voltage power supply 40 applies a voltage having a high value between 3V and 5V and a low value between -4V and -9V to the scan driver. At this time, the voltage output from the circuit voltage power supply 40 has a long time of high and a short time of low, so that the second switching TFT MS2 and the third switching TFT MS3 of the pixel are short. Stay on for hours.

Therefore, the switching TFTs MS1, MS2, MS3 repeat the on-off operation as the voltage applied from the circuit voltage power supply 40 repeats the low signal at the high. At this time, even when the switching TFTs MS1, MS2, and MS3 are in an off state, a voltage is applied to the gate electrode of the driving TFT MD by the storage capacitor Cst and the compensation capacitor Cvth, so that the driving TFT MD Current continues to flow. Therefore, even when a high voltage is applied in the reverse bias application process, the time for maintaining the on state of the switching TFTs MS1, MS2, and MS3 is reduced, thereby reducing the voltage stress applied to the TFTs MD, MS1, MS2, and MS3 in the pixel. have.

The data voltage power supply unit 50 is connected to the data line of the pixel unit 10 and applies a voltage having a value between 2.5V and 5V to the data line.

In addition, when the reverse bias application process is described as an example, a voltage of -15 V is applied to the power supply line VDD and a voltage of -5 V is applied to the cathode voltage power supply unit 30 through the anode voltage power supply unit 20. It is assumed that a voltage having a high of 3 V and a low of -4 V is applied through the voltage power supply 40, and a voltage having a magnitude of 3 V is applied through the data voltage power supply 50.

When a potential of −15 V is applied to the power supply line VDD and −5 V is applied to the cathode electrode VSS, the voltage applied to the drain electrode of the driving TFT MD has a value of about −12 V to −15 V. At this time, the voltage applied from the circuit voltage power supply 40 maintains a high state for the most part.

Therefore, a voltage having a value between about -12V and -15V is applied to the source electrode of the third switching TFT MS3 and a voltage of 3V is mainly applied to the gate electrode, so that the source electrode and the gate electrode of the third switching TFT MS3 are applied. The reverse voltage is applied.

In the second switching TFT MS2, a voltage of −15 V is applied to the source electrode by the power supply line VDD, and a voltage of 3 V is mainly applied to the gate electrode by the circuit voltage power supply 40. The reverse voltage is applied between the source electrode and the gate electrode of MS2).

In addition, in the first switching TFT MS1, when the second switching TFT MS2 is in an off state, a voltage of −15 V across the power supply line VDD is applied to the first electrode of the storage capacitor Cst. At this time, the capacity of the storage capacitor Cst is so small that a voltage of -15V cannot be charged in the storage capacitor Cst, and a voltage of about -3V to -5V is charged in the capacitor. When a voltage of −3 V is charged to the storage capacitor Cst, a voltage of about −12 V is applied to the second electrode of the storage capacitor Cst, and a voltage of about −12 V is applied to the drain electrode of the first switching TFT MS1. do. A voltage having a high of 3 V and a low of -4 V is applied to the gate electrode of the first switching TFT MS1, and a voltage of 3 V is applied to the source electrode. Since a high voltage is mainly maintained at the gate electrode of the first switching TFT MS1, a voltage of 3V is applied, and a reverse voltage is applied between the gate electrode and the drain electrode of the first switching TFT MS1.

Therefore, a reverse voltage is applied between the gate electrode and the source electrode or the drain electrode of the first switching TFT MS1, the second switching TFT MS2, and the third switching TFT MS3.

An aging process is performed on the first switching TFT MS1, the second switching TFT MS2, and the third switching TFT MS3 by the applied reverse voltage.

Therefore, the amount of charge stored in the storage capacitor Cst and the compensation capacitor Cvth can be reduced by leakage through the first switching TFT MS1, the second switching TFT MS2, and the third switching TFT MS3. do.

5 is a graph comparing before and after aging of an IV curve of a TFT in an organic light emitting diode display. The dotted line shows the current flowing between the drain electrode and the source electrode of the TFT without performing the aging process, and the solid line shows the current flowing between the drain electrode and the source electrode of the TFT after the aging process with the reverse bias voltage applied. Indicates. Referring to FIG. 5, the voltage between the gate sources is a case in which a reverse bias voltage is applied and a reverse bias voltage is not applied in a normal operation state in which the V _GS voltage between -15V and + 15V is between -15V and 0V. Although there is little difference in the amount of current flowing between the drain electrode and the source electrode, there is a difference in the amount of current flowing between the drain electrode and the source electrode when the reverse bias voltage is applied or not when the OFF state is between 0V and 15V. Therefore, when the aging process of applying the reverse bias voltage is performed, the amount of current flowing in the off state can be reduced.

Accordingly, the amount of charges stored in the storage capacitor Cst and the compensation capacitor Cvth leaks through the first switching TFT MS1 and the second switching TFT MS2 and the third switching TFT MS3. .

While preferred embodiments of the present invention have been described using specific terms, such descriptions are for illustrative purposes only and it is understood that various changes and modifications may be made without departing from the spirit and scope of the following claims. You must lose.

In the reverse bias application method according to the present invention, by applying a reverse bias voltage to the pixel portion to perform the aging process in the TFT of the pixel portion by the reverse bias voltage to reduce the occurrence of leakage current flowing from the capacitor to the transistor, The amount of charge charged in the included storage capacitors and compensation capacitors can be reduced.

Therefore, the voltage holding force of the storage capacitor and the compensation capacitor does not fall, and thus the image quality of the organic light emitting display device does not occur.

1 is a circuit diagram of a pixel of an organic light emitting diode display according to the related art.

2 is a circuit diagram illustrating a pixel of an organic light emitting diode display used in the present invention.

3 is a timing diagram illustrating driving of pixels of an ideal organic light emitting diode display.

4 is a block diagram illustrating an aging system for applying reverse bias in the reverse bias applying method of the organic light emitting diode display according to the present invention.

5 is a view comparing before and after aging an I-V curve of a TFT in an organic light emitting diode display.

*** Explanation of symbols in drawings ***

10: pixel portion 20: anode voltage power supply portion

30: cathode voltage power supply unit 40: circuit voltage power supply unit

50: data voltage power supply 100: aging system

Claims (4)

A plurality of pixels, a plurality of data lines for applying a data signal to the plurality of pixels, a plurality of scanning lines for applying a selection signal to the plurality of pixels, and first and second applying first and second power supplies to the pixels. A first step of manufacturing an organic light emitting display device including a power line; And A second step of applying a negative potential to the first and second power supply lines, a selection signal having a high and low level potential to the scan line, and applying a data signal having a positive potential to the data line Reverse bias application method of an organic light emitting display comprising a. The method of claim 1, The pixel, Light emitting element; A first switching element for applying a data signal applied to the data line to the second node in response to the first selection signal applied to the first scan line; A first capacitor charging a voltage corresponding to the data signal and maintaining the same for a predetermined period of time; A driving element for flowing a current to the first node in response to the voltage charged in the first capacitor; A second capacitor compensating for a voltage difference generated in the driving device; A second switching element configured to charge the voltage corresponding to the data signal to the first capacitor in response to a second selection signal; A third switching device configured to allow the first node and the driving device to function as a diode in response to the second selection signal; And And a fourth switching element in response to a light emission signal, the fourth switching element being connected to the first node to allow a current to flow through the light emitting element. The method of claim 1, In the second step, a voltage in the range of -5V to -15V is applied to the first power supply line, a voltage in the range of -5V to -8V is applied to the second power supply line, and a high level is applied to the scan line. A method of applying reverse bias in an organic light emitting display device which applies a voltage having a potential in a range of 3V to 5V and a low level potential in a range of -4V to -9V, and applies a voltage in a range of 2.5V to 5V to the data line. . The method of claim 3, wherein And a signal applied to the first power line is an alternating current signal.