KR20050066823A - A semiconductor device for forming a via using alcu-plug, and a manufacturing method thereof - Google Patents
A semiconductor device for forming a via using alcu-plug, and a manufacturing method thereof Download PDFInfo
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- KR20050066823A KR20050066823A KR1020030098305A KR20030098305A KR20050066823A KR 20050066823 A KR20050066823 A KR 20050066823A KR 1020030098305 A KR1020030098305 A KR 1020030098305A KR 20030098305 A KR20030098305 A KR 20030098305A KR 20050066823 A KR20050066823 A KR 20050066823A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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Abstract
본 발명은 반도체 소자의 금속 배선 공정에 있어서 낮은 비저항을 갖는 알루미늄구리를 사용하여 비아-플러그를 형성하는 반도체 소자 및 그 제조 방법에 관한 것이다. 본 발명에 따른 알루미늄구리-플러그를 이용하여 비아를 형성한 반도체 소자의 제조 방법은, ⅰ) 게이트 및 소스/드레인이 형성된 반도체 기판 상에 금속전 유전체막(PMD) 및 콘택을 형성하고, 그 상부에 제1 IMD(Inter Metal Dielectric) 산화막과 질화막을 차례로 형성하는 단계; ⅱ) 금속 배선을 패터닝하고, 노출된 전면에 장벽 금속막을 증착하는 단계; ⅲ) 상기 장벽 금속막 상에 알루미늄구리(AlCu)를 증착하고, 그 상부에 비아 패턴을 형성하는 단계; ⅳ) 상기 비아 패턴에 따라 상기 알루미늄구리를 식각하여 알루미늄-구리 플러그를 형성하고, 상기 알루미늄구리-플러그의 표면에 패시베이션막을 형성하는 단계; 및 ⅴ) 노출된 전면에 제2 IMD 산화막을 증착하고, 상기 알루미늄구리-플러그가 노출되도록 평탄화를 진행하는 단계를 포함한다. 본 발명에 따르면, 낮은 비저항을 갖는 알루미늄구리-플러그 비아를 형성하여 비아 저항을 낮춤으로써, 반도체 소자의 속도를 향상시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device for forming a via-plug using aluminum copper having a low specific resistance in a metal wiring process of a semiconductor device, and a manufacturing method thereof. In the method for manufacturing a semiconductor device in which vias are formed by using an aluminum copper-plug according to the present invention, (i) forming a metal dielectric film (PMD) and a contact on a semiconductor substrate having gates and sources / drains formed thereon, and Sequentially forming a first intermetal dielectric (IMD) oxide film and a nitride film on the film; Ii) patterning the metal wiring and depositing a barrier metal film on the exposed front surface; Iii) depositing AlCu on the barrier metal film and forming a via pattern thereon; Iii) etching the aluminum copper according to the via pattern to form an aluminum-copper plug, and forming a passivation film on the surface of the aluminum copper-plug; And iii) depositing a second IMD oxide film on the exposed entire surface, and planarizing the aluminum copper-plug to expose the aluminum I-plug. According to the present invention, by forming the aluminum copper-plug via having a low specific resistance to lower the via resistance, the speed of the semiconductor device can be improved.
Description
본 발명은 알루미늄구리-플러그를 이용하여 비아를 형성한 반도체 소자 및 그 제조 방법에 관한 것으로, 보다 구체적으로, 반도체 소자의 금속 배선 공정에 있어서 낮은 비저항을 갖는 알루미늄구리-플러그를 이용하여 비아를 형성하는 반도체 소자 및 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which vias are formed using aluminum copper plugs, and more particularly to a method of manufacturing the vias. It relates to a semiconductor device and a manufacturing method thereof.
도 1은 종래 기술에 따른 텅스텐-플러그를 이용하여 비아를 형성한 반도체 소자의 단면도이다.1 is a cross-sectional view of a semiconductor device in which vias are formed using a tungsten plug according to the related art.
종래 기술에 따르면, 먼저 소자 분리막(2)이 형성된 반도체 기판 또는 실리콘 웨이퍼(1) 상에 게이트(3)를 형성하고, 저농도 불순물을 주입하여 저농도 도핑 드레인(LDD: 5)을 형성한 후, 상기 게이트(3)의 측벽에 게이트 스페이서(4)를 형성하고, 이후 활성 영역 상에 소스/드레인(6)을 형성하게 된다.According to the prior art, first, the gate 3 is formed on a semiconductor substrate or a silicon wafer 1 on which the device isolation film 2 is formed, and then a low concentration doping drain (LDD) 5 is formed by injecting low concentration impurities, and then A gate spacer 4 is formed on the sidewall of the gate 3, and then a source / drain 6 is formed on the active region.
이후, 노출된 전면에 반사 방지막(7)과 금속전 유전체막(Pre Metal Dielectric: PMD)(8)을 형성한 후에 콘택(9)을 형성하고, 후속적으로 금속 배선 공정을 실시하게 된다.Subsequently, after forming the anti-reflection film 7 and the pre-metal dielectric film (PMD) 8 on the exposed entire surface, the contact 9 is formed and a metal wiring process is subsequently performed.
즉, 금속 스퍼터링(sputtering) 이후 패터닝 및 식각 공정으로 금속 배선(10)을 형성한 후, 이후 반사 방지막(11)과 IMD(Inter Metal Dielectric)(12)를 증착한 후, 화학적 기계 연마법(CMP)으로 평탄화 공정을 실시하며, 이후, 비아홀 패터닝 및 식각 공정을 진행하여 비아홀을 형성한 후, 장벽 금속막 및 텅스텐-플러그를 증착하고, 이후, CMP 평탄화를 통해 비아(13)를 형성한다.That is, after forming the metal wiring 10 by the patterning and etching process after metal sputtering, after the anti-reflection film 11 and the IMD (Inter Metal Dielectric) 12 is deposited, chemical mechanical polishing (CMP) After the planarization process, the via hole patterning and etching process is performed to form the via hole, the barrier metal film and the tungsten-plug are deposited, and then the via 13 is formed through the CMP planarization.
그러나 종래 기술에 따른 텅스텐-플러그의 CMP 평탄화로 인해 텅스텐-잔여물이 남을 수 있고, 또한 텅스텐의 높은 비저항으로 인해 비아 저항이 높아짐으로써 반도체 소자의 동작 속도가 저하될 수 있다는 문제점이 있다.However, there is a problem that the tungsten-residue may remain due to the CMP planarization of the tungsten-plug according to the prior art, and the operation speed of the semiconductor device may be reduced by increasing the via resistance due to the high resistivity of tungsten.
상기 문제점을 해결하기 위한 본 발명의 목적은 기존의 텅스텐-비아의 텅스텐-잔여물(Residue)과 비아 저항 문제를 해결하고, 낮은 저항에 의해 반도체 소자의 속도를 향상시킬 수 있는 알루미늄구리-플러그를 이용하여 비아를 형성한 반도체 소자 및 그 제조 방법을 제공하기 위한 것이다.An object of the present invention to solve the above problems is to solve the problem of the conventional tungsten-residue (residue) and via resistance of the tungsten-via, and the aluminum copper-plug which can improve the speed of the semiconductor device by a low resistance It is to provide a semiconductor device having vias formed thereon and a method of manufacturing the same.
상기 목적을 달성하기 위한 수단으로서, 본 발명에 따른 알루미늄구리-플러그를 이용하여 비아를 형성한 반도체 소자의 제조 방법은, 반도체 소자의 금속 배선 공정에 있어서,As a means for achieving the above object, a method of manufacturing a semiconductor device in which vias are formed using the aluminum copper-plug according to the present invention, in the metal wiring process of the semiconductor device,
ⅰ) 게이트 및 소스/드레인이 형성된 반도체 기판 상에 금속전 유전체막(Pre Metal Dielectric: PMD) 및 콘택을 형성하고, 그 상부에 제1 IMD(Inter Metal Dielectric) 산화막과 질화막을 차례로 형성하는 단계;Iii) forming a Pre Metal Dielectric (PMD) and a contact on the semiconductor substrate on which the gate and the source / drain are formed, and sequentially forming a first IMD (Inter Metal Dielectric) oxide film and a nitride film thereon;
ⅱ) 금속 배선을 패터닝하고, 노출된 전면에 장벽 금속막을 증착하는 단계;Ii) patterning the metal wiring and depositing a barrier metal film on the exposed front surface;
ⅲ) 상기 장벽 금속막 상에 알루미늄구리(AlCu)를 증착하고, 그 상부에 비아 패턴을 형성하는 단계;Iii) depositing AlCu on the barrier metal film and forming a via pattern thereon;
ⅳ) 상기 비아 패턴에 따라 상기 알루미늄구리를 식각하여 알루미늄구리-플러그를 형성하고, 상기 알루미늄구리-플러그의 표면에 패시베이션막을 형성하는 단계; 및Iii) etching the aluminum copper according to the via pattern to form an aluminum copper plug, and forming a passivation film on the surface of the aluminum copper plug; And
ⅴ) 노출된 전면에 제2 IMD 산화막을 증착하고, 상기 알루미늄구리-플러그가 노출되도록 평탄화를 진행하는 단계Iii) depositing a second IMD oxide film on the exposed entire surface and planarizing the aluminum copper-plug to expose the aluminum I-plug;
를 포함한다.It includes.
여기서, 상기 ⅱ) 내지 ⅴ) 단계를 반복하여 다층의 금속 배선을 형성하는 단계를 추가로 포함할 수 있다.Here, the method may further include forming a multilayer metal wiring by repeating steps ii) to iii).
여기서, 상기 알루미늄구리는 스퍼터링(Sputtering) 방식으로 형성되는 것을 특징으로 한다.Here, the aluminum copper is characterized in that it is formed by a sputtering method.
여기서, 상기 패시베이션막을 형성하는 단계는, 상기 제1 IMD 산화막 상의 장벽 금속막이 완전히 제거됨과 아울러, 상기 질화막이 노출될 때까지 상기 비아 패턴에 따라 상기 알루미늄구리를 식각하는 단계; 및 상기 식각에 의해 형성된 알루미늄구리-플러그의 표면에 패시베이션막을 형성하는 단계를 포함할 수 있다.The forming of the passivation layer may include: etching the aluminum copper according to the via pattern until the barrier metal layer on the first IMD oxide layer is completely removed and the nitride layer is exposed; And forming a passivation film on the surface of the aluminum copper-plug formed by the etching.
여기서, 상기 패시베이션막은 산소 분위기(O2)에서 형성되는 산화알루미늄막(Al2O)인 것을 특징으로 한다.Here, the passivation film is characterized in that the aluminum oxide film (Al 2 O) formed in the oxygen atmosphere (O 2 ).
여기서, 상기 평탄화는 화학적 기계 연마법(CMP) 방식을 사용하는 것을 특징으로 한다.Here, the planarization is characterized by using a chemical mechanical polishing (CMP) method.
한편, 상기 목적을 달성하기 위한 다른 수단으로서, 본 발명에 따른 알루미늄구리-플러그를 이용하여 비아를 형성한 반도체 소자는,On the other hand, as another means for achieving the above object, a semiconductor device in which vias are formed using an aluminum copper-plug according to the present invention,
게이트 및 소스/드레인이 형성된 반도체 기판;A semiconductor substrate on which gates and sources / drains are formed;
상기 반도체 기판 상에 차례로 형성된 금속전 유전체막(PMD) 및 콘택;A metal dielectric layer (PMD) and contacts sequentially formed on the semiconductor substrate;
상기 금속전 유전체막 및 콘택 상부에 차례로 형성되며, 금속 배선 연결을 위해 상기 콘택 상부까지 식각된 제1 IMD 산화막과 질화막;A first IMD oxide film and a nitride film which are sequentially formed on the metal dielectric layer and the contact, and etched to the contact upper portion for metal wire connection;
상기 제1 IMD 산화막과 질화막의 식각 부위에 증착된 장벽 금속막;A barrier metal film deposited on an etched portion of the first IMD oxide film and the nitride film;
상기 장벽 금속막 상에 형성되는 알루미늄구리(AlCu)-플러그;An aluminum copper (AlCu) -plug formed on the barrier metal film;
상기 알루미늄구리-플러그 표면에 증착되는 패시베이션막; 및A passivation film deposited on the surface of the aluminum copper-plug; And
노출된 전면에 증착되고, 상기 알루미늄구리-플러그가 노출되도록 평탄화된 제2 IMD 산화막A second IMD oxide deposited on the exposed front surface and planarized to expose the aluminum copper plug;
을 포함한다.It includes.
여기서, 상기 알루미늄구리-플러그는 스퍼터링 방식으로 형성되는 것을 특징으로 한다.Here, the aluminum copper-plug is characterized in that it is formed by a sputtering method.
여기서, 상기 패시베이션막은 산소 분위기(O2)에서 형성되는 산화알루미늄막(Al2O)인 것을 특징으로 한다.Here, the passivation film is characterized in that the aluminum oxide film (Al 2 O) formed in the oxygen atmosphere (O 2 ).
본 발명에 따르면, 기존의 금속 배선 및 비아홀 제조 방법에 따른 높은 비저항을 갖는 텅스텐 대신에 낮은 비저항을 갖는 알루미늄구리-플러그를 형성하여 비아 저항을 낮춤으로써, 반도체 소자의 속도를 향상시킬 수 있고, 또한 종래 기술에 따른 텅스텐-플러그의 CMP 평탄화로 인한 텅스텐-잔여물 문제를 해결할 수 있다.According to the present invention, by lowering the via resistance by forming aluminum copper-plug having a low specific resistance instead of tungsten having a high specific resistance according to the conventional metal wiring and via hole manufacturing method, it is possible to improve the speed of the semiconductor device, and Tungsten-residue problem due to CMP planarization of the tungsten-plug according to the prior art can be solved.
이하, 첨부된 도면을 참조하여, 본 발명의 실시예에 따른 알루미늄구리-플러그를 이용하여 비아를 형성한 반도체 소자 및 그 제조 방법을 상세히 설명한다.Hereinafter, a semiconductor device in which vias are formed using an aluminum copper plug according to an embodiment of the present invention, and a method of manufacturing the same will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e는 본 발명에 따른 알루미늄구리-플러그를 이용하여 비아를 형성한 반도체 소자의 제조 방법을 나타내는 공정 흐름도이다.2A to 2E are process flowcharts illustrating a method of manufacturing a semiconductor device in which vias are formed using an aluminum copper plug according to the present invention.
본 발명에 따른 알루미늄구리-플러그를 이용하여 비아를 형성한 반도체 소자의 제조 방법은, 도 2a를 참조하면, 반도체 기판 또는 실리콘 웨이퍼(21) 상에 게이트(22)를 형성하고, 저농도 불순물을 주입하여 저농도 도핑 드레인(LDD)(도시되지 않음)을 형성한 후, 상기 게이트(22)의 측벽에 게이트 스페이서(23)를 형성하고, 이후 활성 영역 상에 소스/드레인(도시되지 않음)을 형성하게 된다. 이후, 상기 소스/드레인 영역 상에 실리사이드(25)를 형성하고, 금속전 유전체 산화막(PMD: 24)을 형성한 후, 사진 및 식각 공정으로 비아 또는 콘택(26)을 형성하며, 이후 IMD 산화막(27) 및 SiN 질화막(28)을 증착하게 된다.In the method of manufacturing a semiconductor device in which vias are formed using an aluminum copper-plug according to the present invention, referring to FIG. 2A, a gate 22 is formed on a semiconductor substrate or a silicon wafer 21, and low concentration impurities are injected. To form a low concentration doped drain (LDD) (not shown), followed by forming a gate spacer 23 on the sidewall of the gate 22, and then forming a source / drain (not shown) on the active region. do. Subsequently, silicide 25 is formed on the source / drain regions, a dielectric metal oxide layer (PMD) 24 is formed, and vias or contacts 26 are formed by photolithography and etching, and then an IMD oxide layer ( 27) and SiN nitride film 28 is deposited.
다음으로, 금속 배선을 형성하기 위한 금속 라인을 패터닝하여 상기 SiN 질화막(28) 및 IMD 산화막(27)의 소정 부위를 식각하고, 노출된 전면에 TiN 장벽 금속막(29)을 증착한다(도 2b 참조).Next, a metal line for forming a metal wiring is patterned to etch predetermined portions of the SiN nitride film 28 and the IMD oxide film 27 and to deposit a TiN barrier metal film 29 on the exposed entire surface (FIG. 2B). Reference).
다음으로, 상기 장벽 금속막(29) 상부에 알루미늄구리(AlCu)(30)를 스퍼터링 방식으로 증착한 후, 비아 패턴(31)을 형성한다(도 2c 참조).Next, after the aluminum copper (AlCu) 30 is deposited by sputtering on the barrier metal layer 29, a via pattern 31 is formed (see FIG. 2C).
다음으로, 상기 IMD 산화막(27) 상의 장벽 금속(29)이 완전히 제거됨과 아울러, 질화막(28)이 노출될 때까지 상기 비아 패턴(31)을 마스크로 하여 식각을 진행하여 금속 배선 및 비아 역할을 하는 알루미늄구리 플러그(32)를 형성한 후, 산소(O2) 분위기에서 알루미늄구리(AlCu) 표면에 산화알루미늄막(Al2O: 33)을 형성한다(도 2d 참조). 여기서, 상기 산화알루미늄막(33)은 패시베이션막으로 사용될 수 있다.Next, the barrier metal 29 on the IMD oxide layer 27 is completely removed, and etching is performed using the via pattern 31 as a mask until the nitride layer 28 is exposed, thereby serving as a metal wiring and a via. After the aluminum copper plug 32 is formed, an aluminum oxide film (Al 2 O: 33) is formed on the surface of aluminum copper (AlCu) in an oxygen (O 2 ) atmosphere (see FIG. 2D). Here, the aluminum oxide film 33 may be used as a passivation film.
다음으로, 노출된 전면에 제2 IMD 산화막(34)을 증착한 후, CMP 평탄화를 실시하고(도 2e 참조), 이후 전술한 금속 배선 공정을 반복하여 다층의 금속 배선을 형성할 수 있게 된다.Next, after depositing the second IMD oxide film 34 on the exposed entire surface, CMP planarization is performed (see FIG. 2E), and the above-described metal wiring process can be repeated to form a multilayer metal wiring.
본 발명은 높은 비저항을 갖는 텅스텐 대신에 낮은 비저항을 갖는 알루미늄구리-플러그를 형성함으로써, 비아 저항을 낮출 수 있고, 또한 종래 기술에 따른 텅스텐-플러그의 CMP 평탄화로 인한 텅스텐-잔여물 문제를 해결할 수 있다.The present invention can lower the via resistance by forming aluminum copper-plug having a low resistivity instead of tungsten having a high resistivity, and also solve the tungsten-residue problem caused by CMP planarization of the tungsten-plug according to the prior art. have.
위에서 발명을 설명하였지만, 이러한 실시예는 이 발명을 제한하려는 것이 아니라 예시하려는 것이다. 이 발명이 속하는 분야의 숙련자에게는 이 발명의 기술 사항을 벗어남이 없어 위 실시예에 대한 다양한 변화나 변경 또는 조절이 가능함이 자명할 것이다. 그러므로 본 발명의 보호 범위는 첨부된 청구 범위에 의해서만 한정될 것이며, 위와 같은 변화예나 변경예 또는 조절예를 모두 포함하는 것으로 해석되어야 할 것이다.While the invention has been described above, these examples are intended to illustrate rather than limit this invention. It will be apparent to those skilled in the art that various changes, modifications, or adjustments to the above embodiments are possible without departing from the technical details of the present invention. Therefore, the scope of protection of the present invention will be limited only by the appended claims, and should be construed as including all such changes, modifications or adjustments.
본 발명에 따르면, 높은 비저항을 갖는 텅스텐 대신에 낮은 비저항을 갖는 알루미늄구리-플러그를 형성하여 비아 저항을 낮춤으로써, 반도체 소자의 속도를 향상시킬 수 있고, 또한 종래 기술에 따른 텅스텐-플러그의 CMP 평탄화로 인한 텅스텐-잔여물 문제를 해결할 수 있다.According to the present invention, by lowering the via resistance by forming aluminum copper-plug having a low specific resistance instead of tungsten having a high specific resistance, it is possible to improve the speed of the semiconductor device, and also to planarize the CMP of the tungsten-plug according to the prior art. Tungsten-residue problem can be solved.
도 1은 종래 기술에 따른 텅스텐-플러그를 이용하여 비아를 형성한 반도체 소자의 단면도이다.1 is a cross-sectional view of a semiconductor device in which vias are formed using a tungsten plug according to the related art.
도 2a 내지 도 2e는 본 발명에 따른 알루미늄구리-플러그를 이용하여 비아를 형성한 반도체 소자의 제조 방법을 나타내는 공정 흐름도이다.2A to 2E are process flowcharts illustrating a method of manufacturing a semiconductor device in which vias are formed using an aluminum copper plug according to the present invention.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100780245B1 (en) * | 2006-08-28 | 2007-11-27 | 동부일렉트로닉스 주식회사 | Semiconductor device and manufacturing method |
| KR100889547B1 (en) * | 2007-10-25 | 2009-03-23 | 주식회사 동부하이텍 | Metal wiring formation method of semiconductor device |
| US7648904B2 (en) | 2006-09-29 | 2010-01-19 | Hynix Semiconductor Inc. | Metal line in semiconductor device and method for forming the same |
| US8710660B2 (en) | 2012-07-20 | 2014-04-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid interconnect scheme including aluminum metal line in low-k dielectric |
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2003
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100780245B1 (en) * | 2006-08-28 | 2007-11-27 | 동부일렉트로닉스 주식회사 | Semiconductor device and manufacturing method |
| US7648904B2 (en) | 2006-09-29 | 2010-01-19 | Hynix Semiconductor Inc. | Metal line in semiconductor device and method for forming the same |
| US8120113B2 (en) | 2006-09-29 | 2012-02-21 | Hynix Semiconductor Inc. | Metal line in semiconductor device |
| KR100889547B1 (en) * | 2007-10-25 | 2009-03-23 | 주식회사 동부하이텍 | Metal wiring formation method of semiconductor device |
| US7691738B2 (en) | 2007-10-25 | 2010-04-06 | Dongbu Hitek Co., Ltd. | Metal line in semiconductor device and fabricating method thereof |
| US8710660B2 (en) | 2012-07-20 | 2014-04-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid interconnect scheme including aluminum metal line in low-k dielectric |
| KR101411198B1 (en) * | 2012-07-20 | 2014-06-23 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Hybrid Interconnect Scheme and Methods for Forming the Same |
| US9362164B2 (en) | 2012-07-20 | 2016-06-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid interconnect scheme and methods for forming the same |
| US9966336B2 (en) | 2012-07-20 | 2018-05-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid interconnect scheme and methods for forming the same |
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