KR20040083809A - The Driving Circuit of Pseudo SRAM - Google Patents

Abstract

The present invention discloses a drive circuit for a pseudo esram. In particular, a comparator for comparing the external voltage and the core voltage to selectively output a high signal and a low signal to control the switching unit; A switching unit which opens and closes switching according to the control signal output from the comparator and outputs an internal boost voltage and a core voltage; And a driving unit connected to the switching unit and driven according to a first driving voltage and a second driving voltage, wherein a supply voltage is sufficient to maintain data when the power supply voltage is lowered below the operating voltage through the circuit. There is this.

Description

The driving circuit of Pseudo SRAM.

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a drive circuit of a pseudo-sRAM, and more particularly, to a method of preserving data by reinforcing an insufficient voltage when the core voltage is below an external voltage.

Currently, Pseudo SRAM is being developed to supplement the small area of DRAM with fast operation speed and low power consumption of SRAM of semiconductor memory devices.

1 is a circuit diagram for briefly explaining a voltage occupied by an equivalent circuit of a pseudo-sram.

As shown in FIG. 1, the equivalent circuits 100 and 110 of FIG. 1 show a case where one switch is turned on (110) / off (100) a bit line capacitor and a cell capacitor, and the diagram 120 below shows ON / OFF. Represents the charging voltage of the equivalent circuit.

That is, in the off state 100, 2/1 of the core voltage is precharged V _{BL in the} bit line. At this time, when the switch is turned on (110), the voltage is charged between the bit line (BL) and the cell (Charge sharging) (V) in accordance with the data signal.

For example, when the switch of the equivalent circuit is in the on state 110, when the data signal of 1 is stored in the unit memory cell, the voltage of Vs1 in the precharging (V _BL ) state in the bit line and the bit bar line. When this is applied and transferred to the sense amplifier, the sense amplifier recognizes a data signal of 1. In contrast, a data signal of zero has a Vs2 voltage applied to the bit line and the bit bar line. Here, reference numeral Vcore denotes a core voltage as a voltage supplied to a memory of a memory, Cs denotes a cell capacitance, and CBL denotes a capacitance of a bit line.

The Shush SRAM also performs a refresh operation that periodically charges to avoid losing stored data. This operation consumes power, so if the phone is not used, such as a mobile phone, the power supply The recent trend is to keep the power at a lower voltage by lowering the normal operating voltage to minimize power consumption. At this time, a voltage lower than the voltage applied in the normal operation causes a problem of data loss even when the refresh is input.

In other words, when the driving voltage of the mobile phone in normal operation is 1.8V, when the phone is not used, it is 1.8V, and when the phone is not used, the low voltage of 1.8V or less is not maintained, so that sufficient refresh charge is not supplied. In other words, the low voltage causes the ring oscillator to determine the refresh period, resulting in loss of data stored as a fallback failure.

Accordingly, an object of the present invention is to solve the above-mentioned problems, and when the core voltage is lower than the driving voltage, the drive circuit of the pseudo-sram which can preserve the data by supplying insufficient voltage sufficiently To provide.

1 is an equivalent circuit and a block diagram for explaining a general method of driving a drive SRAM.

2 is a voltage curve for explaining the voltage characteristics used in the present invention.

Figure 3 is a circuit diagram for explaining a drive circuit of the shoe SRAM according to the present invention.

The driving circuit of the pseudo SRAM according to the present invention for achieving the above object comprises: a comparator for comparing the external voltage and the core voltage to selectively output a high signal and a low signal to control the switching unit; A switching unit which opens and closes switching according to the control signal output from the comparator and outputs an internal boost voltage and a core voltage; And a driving unit connected to the switching unit and driven according to a first driving voltage and a second driving voltage.

Example 1

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, the voltage curves of the internal voltages used in the driving circuit of the pseudo-sram will be described with reference to the drawings.

2 is a graph showing curves of voltages used as internal power supply voltages in a normal operation mode. As shown, the characteristics of the respective internal power sources are shown based on the external voltage Vext. The horizontal axis represents the external voltage Vext, and the vertical axis represents each internal power source set according to the external voltage Vext value.

Here, the core voltage (Vcore) for supplying power to the unit memory cell is set to maintain 1.8V even if the external voltage (Vext) increases from 1.8V. That is, when the driving voltage of the driving circuit is set to 1.8V, the driving voltage of the circuit is maintained at the core voltage Vcore when the external voltage is higher than 1.8V.

At this time, when the core voltage is less than 1.8V, the core voltage Vcore has a voltage value less than or equal to the driving voltage and thus data cannot be maintained.

Where Vpp denotes an internal boost voltage, Vcore denotes a core voltage, and Vcp / Vblp denotes a voltage flowing in a capacitor and a bit line of a cell, and power-up (Pwrup) starts at 1.5V in the voltage curve.

3 is a circuit diagram illustrating in detail the driving circuit of the pseudo SRAM according to the present invention.

As shown, the driving circuit of the shoe SRAM according to the present invention is composed of a comparator 300, a switching unit 310 and a driving unit 320, the comparator 300 and the switching unit 310 is the first You are connected to control mode (Ctrl 1).

The driving method of the circuit based on the difference between the magnitude of the external voltage Vext and the core voltage Vcore is as follows.

The comparator 300 includes two first and second PMOS transistors P1 and P2 and three first, second and third NMOS transistors N1, N2 and N3.

A gate of the first NMOS transistor N1 is connected to an external voltage Vext, and a drain thereof is simultaneously connected to a source and a node A of the first PMOS transistor P1. The first PMOS transistor P1 has an internal boost voltage Vpp connected to a drain thereof, and a gate thereof connected to a drain of the first NMOS transistor N1 so as to be connected to a signal of the first NMOS transistor N1. Decide to open and close accordingly. In addition, the second PMOS transistor P2 also has an internal boost voltage Vpp connected to the drain, and a gate thereof is connected to the node A signal coming out of the drain of the first NMOS transistor N1, according to the reference of the node A signal. The first NMOS transistor P1 is opened and closed to apply the internal boost voltage Vpp or the external voltage Vext to the first control mode Ctrl 1, respectively. The node B connected to the source of the second PMOS transistor P2 and the first control mode Ctrl 1 is connected to the drain of the second NMOS transistor N2, and the gate is connected to the core voltage Vcore. Connected. In addition, the source of the first and second NMOS transistors N1 and N2 has a structure connected to the drain of the third NMOS transistor N2 connected to the ground voltage Vss.

In the switching unit 310, the gate of the third PMOS transistor P3 is connected to the first control mode Ctrl 1, the core voltage Vcor is applied to the drain and the source at the first driving voltage, respectively, and the second driving is performed. The internal boosting voltage Vpp is connected to the voltage to be configured to transmit one of the first driving voltage and the second driving voltage to the output unit 320 according to the control signal of the comparator 300.

First, the driving method of the second NMOS transistor N2 when the external voltage Vext is greater than the core voltage Vcor, that is, when the core voltage Vcor is constant at 1.8V or more as shown in section A of FIG. 2. The gate is closed by receiving a low signal, and the gate of the first NMOS transistor N1 receives a high signal to open the gate, so that the ground voltage Vss flows to the node A. At this time, since the first and second PMOS transistors P1 and P2 are turned on and the gate is opened, the internal boost voltage Vpp flows in the first control mode Ctrl 1.

On the contrary, when the core voltage Vcore is less than or equal to the external voltage Vext, that is, when the core voltage is 1.8V or less and the driving voltage is smaller than the driving voltage as shown in section B of FIG. The gate of the NMOS transistor N2 receives a high signal and the first NMOS transistor N1 receives a low signal, and the second NMOS transistor N2 opens to allow the ground voltage Vss to flow toward the node B. 1 In control mode (Ctrl 1), the ground voltage (Vss) flows.

At this time, when the internal boost voltage Vpp flows in the first control mode Ctrl 1 according to the signal of the comparator 300, the third PMOS transistor P3 of the switching unit 310 is turned off and the driving unit 320 is turned on. When the core voltage Vcore is applied and the ground voltage Vss flows in the first control mode Ctrl 1, the third PMOS transistor P3 is turned on to boost the internal voltage to the driving unit 320. The voltage Vpp flows.

The driving unit 320 is connected to a sense amplifier and a ring oscillator to perform a sensing operation or to maintain a refresh cycle.

In other words, when the circuit is constructed with the voltage characteristic curve of FIG. 2, when the external voltage Vext becomes 1.8 V or more, the core voltage Vcore is always maintained at 1.8 V, and the comparator 300 then controls the first control. Since the internal boost voltage Vpp is applied in the mode CtrlA to turn off the third PMOS transistor P3, the core voltage Vcore flows through the sense amplifier 320 as it is.

However, when the core voltage Vcore is 1.8 V or less, the external voltage Vext and the core voltage Vcore become equal, and then the comparator 300 applies the ground voltage Vss in the first control mode Ctrl 1 to apply the ground voltage Vss. The 3 MOS transistor P3 is opened, and the internal boost voltage Vpp, which is the highest voltage among the internal power supplies, is applied to the driver 320.

That is, even if a low voltage below the driving voltage is applied, a sufficient voltage can always be charged to the driving unit through the internal boost voltage Vpp.

In this case, the second control mode (ctrl 2) may be set as a high signal when it is fixed and used as an enable signal when used as a control signal.

As described above, according to the driving circuit of the pseudo SRAM according to the present invention, when a battery of a machine requiring a low voltage, such as a mobile phone, or when the power is turned off for a while, when a low voltage below the driving voltage flows, By connecting the sense amplifier to the driving unit so that the internal boost voltage, which is the highest internal voltage, flows as the driving voltage of the unit memory cell, thereby preventing data loss due to low power.

In addition, when the reason for data loss is caused by a long period of refresh, the refresh cycle is maintained by appropriately adjusting the refresh cycle by connecting a ring oscillator to the driving unit of the present invention.

On the other hand, the present invention is not limited to the above-described specific preferred embodiments, anyone of ordinary skill in the art without departing from the gist of the invention claimed in the claims can be variously modified. will be.

Claims (3)

A comparator for comparing the external voltage and the core voltage to selectively output a high signal and a low signal to control the switching unit; A switching unit which opens and closes switching according to the control signal output from the comparator and outputs an internal boost voltage and a core voltage; And a driving unit connected to the switching unit and driven according to a first driving voltage and a second driving voltage. The method of claim 1, In the comparator, when the external voltage is greater than the core voltage, the switching unit outputs the core voltage as the first driving voltage, and in the reverse case, the switching unit outputs the highest internal voltage of the driving circuit as the second driving voltage. The drive circuit of the pseudo-sram, characterized in that configured. The method of claim 1, And a sense amplifier and a ring oscillator connected to the driving unit.