KR20040010931A - Generic Framing Procedure Frame Delineation Detection Circuit in communication system - Google Patents

Abstract

PURPOSE: A circuit for detecting a GFP(Generic Framing Procedure) frame boundary in a communication system is provided to calculate frequency for converting into a synchronous state from a preliminary synchronous state, and to determine a GFP frame boundary by receiving calculated results, thereby processing data at high speed and minimizing wrong operations. CONSTITUTION: A shift register(10) shifts a GFP frame. An error detector and compensator(20) descrambles the GFP frame, detects an HEC(Header Error Check), corrects a single error, and detects multiple errors. A storage(30) extracts a PLI(Payload Length Identifier) from the received GFP frame, and stores the extracted PLI. The first counter(40) calculates boundary length of the GFP frame. The second counter(50) calculates frequency for converting into a synchronous state from a preliminary synchronous state. A state determiner(60) determines a GFP frame boundary by receiving calculated results.

Description

Generic Framing Procedure Frame Delineation Detection Circuit in communication system

The present invention relates to a communication system, and more particularly, to a packet using an optical transport network (OTN) and a synchronous digital layer (SDH) defined in ITU-T G.709 and G.707. The present invention relates to a generic framing procedure (hereinafter referred to as GFP) frame boundary detection circuit that is suitable for processing data at high speed in case of transmission.

The International Telecommunication Union (ITU) develops and publishes standard specifications to promote ITU Recommendations to facilitate the interconnection of global telecommunication systems, regardless of the technology or model used, two of which are the ITU-R Recommendation and the IUT-T Recommendation. It is written and published.

Conventional techniques for packet transmission as indicated in the IUT-T Recommendations include high-level data link control procedures (HDLC / point-to-point protocol (PPP) or link access procedures). The packet was transmitted using an encapsulation technique such as a link access procedure (synchronous digital hierarchy (LAPS)).

Here, HDLC is a typical data communication transmission control procedure used in a packet switched network or an integrated information communication network (ISDN), and means a standardized by the International Organization for Standardization (ISO). In HDLC, information is divided and transmitted in units called frames. Partial transmission of data is the same as the basic mode transmission control procedure, which is an initial technology, but a feature of transmitting a code necessary for transmission control in the first part of the frame is always distinguished from the information and transmitted. The position of the frame is easily detected because the start and end of each frame are wrapped with a flag of 8-bit code (01111110). In HDLC, six consecutive ones are limited to flags, and if six or more consecutive ones are included in the information, zeros are forced to be added after the fifth so that the flag can be clearly distinguished from the flag. The flag is followed by an address code indicating an identification number of a transmitting side and a receiving side, a control code displaying various control information, a data information portion of arbitrary length, and a frame error check sequence. If an error is detected at the receiving end, resend is requested. Therefore, high reliability is ensured. HDLC is a representative protocol of the data link layer (second layer) of the OSI basic reference model, and is also used in an X.25 based packet switching network or a signaling method through an ISDN D channel.

In addition, LAPS is a communication protocol recommended by ITU-T for transmitting a packet in the SDH transmitter, and is a simplified form of HDLC as described above.

In addition, the encapsulation technology is a technology for transmitting the communication protocol information of the upper layer in the lower communication protocol frame user information area in data communication. The encapsulation technology is also referred to as a procedure of combining information in a plurality of protocol layers into a communication network. Same meaning as

However, such a conventional technology has a problem that it is difficult to process a packet to be transmitted at high speed because a flag byte is inserted to encapsulate the packet, or packet data is changed for an escape operation.

In addition, due to an error generated when a packet is transmitted, it affects several frames and is not suitable for a long distance transmission with a relatively large number of transmission errors.

In order to solve this problem, new technologies such as SDL, GFP, etc. are being applied to research and communication systems.

GFP is a method of multiplexing signals such as IP / PPP, gigabit ethernet, and optical channel for effective transmission through a telecommunication network. GFP frames are variable length and can increase bandwidth efficiency by multiplexing different types of signals into one transport frame for SDH / SONET.

SUMMARY OF THE INVENTION The present invention has been made to solve such a conventional problem, and an object thereof is to provide a general framing procedure frame boundary detection circuit in a communication system capable of processing data to be transmitted at high speed.

1 is a general framing procedure frame boundary state diagram in a communication system in accordance with the present invention.

2 is a block diagram of a general framing procedure frame boundary detection circuit in a communication system in accordance with the present invention.

3 is a waveform diagram illustrating the operation of FIG. 2;

* Description of the symbols for the main parts of the drawings *

10: shift register section

11 ~ 14: Shift register

20: error detection and correction unit

30: storage unit

40: first counting unit

50: second counting unit

60: state determination unit

In the communication system according to the present invention for achieving the above object, a general framing procedure frame boundary detection circuit includes: a synchronization state for detecting information for identifying a header abnormality in units of frames; A preliminary synchronizing state which detects information for confirming whether there is an abnormality of the header in a predetermined number of times and transitions to the synchronizing state when detecting; A communication system operating in a synchronization signal tracking state that detects information for checking whether there is an abnormality of the header and transitions to the pre-synchronization state when detected, wherein the payload length identifier is received from a received Generic Framing Procedure (GFP) frame. A storage unit for extracting and storing information; A first counting unit calculating a boundary length of the GFP frame; A second counting unit calculating a number of times for switching from a preliminary synchronization state to a synchronization state; And a state determination unit which determines the GFP frame boundary based on the calculation result of the first counting unit and the second counting unit.

According to the features of the present invention as described above, it is possible to process the data to be transmitted at high speed, this feature has the advantage that is more suitable for transmitting the data to the destination at a long distance.

Hereinafter, a configuration and operation of a general framing procedure frame boundary detection circuit in a communication system according to the present invention will be described with reference to the accompanying drawings.

1 is a general framing procedure frame boundary state diagram in a communication system according to the present invention. Referring to FIG. 1, the synchronization signal tracking state HUNT detects packet error check information (Header Error Check: HEC) for detecting a header abnormality in octet units, and preliminary synchronization when detecting an HEC. Transition to PRESYNC. The pre-sync state PRESYNC detects the HEC on a frame-by-frame basis, and transitions to the sync state SYNC when detecting Delta times. At this time, the system automatically transitions to the synchronization signal tracking state (HUNT) if it does not detect the synchronization signal even once. Delta is also a mathematical constant with the name mentioned in the ITU-T G.7041 GFP specification, generally eight.

The synchronizing state SYNC detects the cHEC on a frame basis, performs error correction when a 1-bit error occurs in the cHEC, and transitions to the synchronizing signal tracking state HUNT when a multi-bit error occurs. In the synchronous state, data is transmitted normally, but not in other states.

2 is a block diagram of a general framing procedure frame boundary detection circuit in a communication system according to the present invention. Referring to FIG. 2, in the communication system of the present invention, a general framing procedure frame boundary detection circuit includes a shift register section 10 having four shift registers and shifting a GFP frame input in units of preset bytes; Error detection and correction unit that descrambles using 4 bytes shifted in the shift register unit 10, detects an HEC, corrects a single error, and detects a multiple error. 20; A storage unit 30 for extracting and storing a payload length identifier (PLI) from the received GFP frame; A first counting unit 40 for calculating a boundary length of the GFP frame; A second counting unit 50 for counting the number of times for switching from a preliminary synchronization state to a synchronization state; The first counting unit 40 and the second counting unit 50 is configured to receive a calculation result of the state determination unit 60 to determine the boundary of the GFP frame.

Hereinafter, an operation of a general framing procedure frame boundary detection circuit in a communication system according to the present invention will be described with reference to the accompanying drawings.

Each shift register 11-14 of the shift register section 10 shifts the input 8 bits data. The error detection and correction unit 20 descrambles 4 bytes every clock and detects an HEC. At this time, when the result value of the HEC is 0, the error detection and correction unit 20 sends an output (hec_det) value. If the current state is a synchronous state (SYNC), if a result value other than 0 is output, it is determined whether it is a 1-bit error or a multi-bit error. If a 1-bit error occurs, a single error message (single_err) is output. If it is a multi-bit error, it outputs a multi-error message (multi_err). In this case, the error detection and correction unit 20 may correct the generated error.

When the current state is the synchronization signal tracking state HUNT, the storage unit 30 first outputs the output hec_det of the error detection and correction unit 20 to '1' or is not the synchronization signal tracking state HUNT. When the output sync_ts of the counting unit 40 becomes '1', the PLI portion, which is the upper two bytes of the shift register 11-14, is stored. That is, the storage unit 30 stores the PLI information based on the detection time of the HEC in the synchronization signal tracking state (HUNT). However, in a state other than the synchronization signal tracking state HUNT, the PLI information is stored based on the output of the first counting unit 40 measuring the GFP frame length.

The first counting unit 40 sets the primary output pli_cnt to X "0001" when the output hec_det of the error detection and correction unit 20 becomes '1' in the selection (HUNT) state. If the primary output (pli_cnt) is equal to the output (pli_val) of the storage unit 30, the primary output is set to X "0000". Otherwise, the primary output (pli_cnt) is increased by +1, and the primary output (pli_cnt) is 0. When the final output (sync_ts) is output as '1'. That is, in the synchronization signal tracking state HUNT, an initial value + 1 is set when the HEC is detected, and when the counting value of the first counting unit 40 is equal to the PLI information, the initial value is set to an initial value, and otherwise, it is increased by +1. When the value of the counter is equal to the initial value, the sync pulse signal is output.

In the second counting unit 50, when the output sync_ts of the first counting unit 40 becomes '1' in the preliminary synchronization state PRESYNC, the output hec_det of the error detection and correction unit 20 becomes '1'. If it is 1 ', it is incremented by +1. If the output (hec_det) of the error detection and correction unit 20 is' 0', it is cleared to 0. That is, it is a preliminary synchronization state (PRESYNC) at the time of synchronization signal input, increases by +1 when HEC is detected, and clears to 0 otherwise.

If the output hec_det of the error detection and correction unit 20 is '1' and the first output unit pli_cnt of the first counting unit 40 is 0 in the synchronization signal tracking state HUNT, The current state becomes the preliminary synchronization state PRESYNC, and when the final output sync_ts of the first counting unit 40 is '1' in the preliminary synchronization state PRESYNC, the output of the error detection and correction unit 20 ( When hec_det is '1' and the second counting unit 50 becomes delta DELTA, the synchronization state SYNC is obtained, and when the error detection and correction unit 20 outputs hec_det 0, the synchronization signal is generated. Return to trace state (HUNT). However, when the final output sync_ts of the first counting unit 40 is '1' in the synchronization state SYNC, if a multi-error multi_err is detected, the synchronization signal tracking state HUNT is entered. Here, the delta DELTA means the number of times to switch from the preliminary synchronization (RESINC) state to the synchronization (SYNC) state.

FIG. 3 is a waveform diagram illustrating the operation of FIG. 2, where waveform a) represents a pulse signal generated when HEC is detected, and an arrow indicates a start point of a next packet designated by PLI. Waveform diagram b) shows that the first counting unit 40 sets it to 1 using the waveform of the waveform diagram b). In the normal state, the polling of the waveform diagram a) and the waveform diagram b) coincide. The waveform diagram c) corresponds to the waveform diagram a) in the normal state at the time when the first counting unit 40 becomes zero, and does not match in the abnormal state.

The waveform diagram d) shows the output pulse signal generated when the waveform diagram a) and the waveform diagram c) coincide, the waveform diagram e) shows the output signal of the second counting unit 50, and the waveform diagram f) shows the state. The output signal of the decision unit 60 is shown.

As described above, although the PLI information may be very short or very long due to an error of HEC detection in the synchronization signal tracking state (HUNT), the primary output (pli_cnt) of the first counting unit 40 by the following HEC detection. Is reset to X "0001", and the output pli_val of the storage unit 30 is also stored as a new value.

When the received data is stable, normal HEC can be detected, and when the first stable GFP is input, the normal PLI is updated in the storage unit 30. In this case, when the next stable GFP is input again, when the output pli_cnt of the first counting unit 40 becomes 0, the error detection and correction unit 20 outputs hec_det. ) Becomes '1' so that continuity of the primary output pli_cnt of the first counting unit 40 is not broken and counting is normally performed. At this time, the current state transitions to the preliminary synchronization state PRESYNC, and the output delta_cnt of the second counting unit 50 increases by 1 from 0 to 1. When the normal GFP frame is continuously input delta DELTA times, the output delta_cnt of the second counting unit 50 becomes DELTA + 1 and becomes a synchronization state SYNC. In the next GFP frame, since the synchronization state SYNC, the second counting unit 50 is cleared to '0' and maintains the synchronization state SYNC until a multi-error multi_err occurs. When the multiple error multi_err becomes '1' in the synchronization state SYNC, the synchronization signal tracking state HUNT is again performed, and the above-described operation is repeated from the beginning.

Although the preferred embodiments of the present invention have been described in detail above, those skilled in the art will appreciate that the present invention may be modified without departing from the spirit and scope of the invention as defined in the appended claims. It will be appreciated that modifications or variations may be made.

According to the general framing procedure frame boundary detection circuit in the communication system according to the present invention as described above, the data to be transmitted can be processed at high speed, and the communication system equipped with the present invention can transmit data to a long distance destination. Malfunctions caused by errors can be minimized. Therefore, there is an advantage that can provide a competitive communication system in the environment of the communication market where a high speed and high capacity communication system is required.

Claims (5)

A synchronization state for detecting information for identifying a header abnormality in units of frames; A preliminary synchronizing state which detects information for confirming whether there is an abnormality of the header in a predetermined number of times and transitions to the synchronizing state when detecting; In a communication system that operates in a synchronization signal tracking state that detects information for confirming whether there is an abnormality of the header and, when detected, transitions to the pre-synchronization state. A storage unit for extracting and storing payload length identifier information from the received Generic Framing Procedure (GFP) frame; A first counting unit calculating a boundary length of the GFP frame; A second counting unit calculating a number of times for switching from the preliminary synchronization state to the synchronization state; And a state determination unit configured to determine the GFP frame boundary based on the calculation results of the first counting unit and the second counting unit. The storage unit of claim 1, wherein the storage unit stores the header error based on the detection time of the error information in the header in the synchronization signal tracking state, and stores the output based on the output of the first counting unit in a state other than the synchronization signal tracking state. And a general framing procedure frame boundary detection circuit in a communication system. The method of claim 1, wherein the first counting unit sets an initial value + 1 when the synchronization signal tracking state detects whether there is an error in the header error check information, and the counting value of the first counting unit is equal to the payload length identifier information. Setting a value, otherwise increasing by +1, and outputting a sync pulse signal when the counting value of the first counting unit is equal to the initial value. The general framing of the communication system according to claim 1, wherein the second counting unit is in a preliminary synchronization state when the synchronization signal is input, and increases by +1 when detecting error information of a header error, and is cleared to 0 otherwise. Procedure Frame Boundary Detection Circuit. The synchronization determiner of claim 1, wherein the state determiner is in a preliminary synchronization state when the detection value of the error error confirmation information of the header in the synchronization signal tracking state and the counting value of the first counting unit are initial values. When a signal is input, when the detection value of the error abnormality confirmation information of the header and the counting value of the first counting unit become a preset constant value, and the synchronization state is not detected, and when the error abnormality confirmation information of the header is not detected And returning to the synchronization signal tracking state and transitioning to the synchronization signal tracking state when a multi-bit error is detected when the synchronization pulse signal is input in the synchronization state.