KR20040004121A - Process for machining a wafer-like workpiece - Google Patents
Process for machining a wafer-like workpiece Download PDFInfo
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- KR20040004121A KR20040004121A KR1020030044331A KR20030044331A KR20040004121A KR 20040004121 A KR20040004121 A KR 20040004121A KR 1020030044331 A KR1020030044331 A KR 1020030044331A KR 20030044331 A KR20030044331 A KR 20030044331A KR 20040004121 A KR20040004121 A KR 20040004121A
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- 238000000034 method Methods 0.000 title claims abstract description 21
- 238000003754 machining Methods 0.000 title description 2
- 239000000463 material Substances 0.000 claims abstract description 6
- 230000007423 decrease Effects 0.000 claims abstract description 4
- 238000005498 polishing Methods 0.000 claims description 19
- 239000004065 semiconductor Substances 0.000 claims description 10
- 230000000694 effects Effects 0.000 claims description 2
- 239000012752 auxiliary agent Substances 0.000 claims 1
- 239000013589 supplement Substances 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 description 14
- 239000003795 chemical substances by application Substances 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 241001093575 Alma Species 0.000 description 1
- 239000002671 adjuvant Substances 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
- B24B37/07—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool
- B24B37/08—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool for double side lapping
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
- B24B37/042—Lapping machines or devices; Accessories designed for working plane surfaces operating processes therefor
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B49/00—Measuring or gauging equipment for controlling the feed movement of the grinding tool or work; Arrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation
- B24B49/16—Measuring or gauging equipment for controlling the feed movement of the grinding tool or work; Arrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation taking regard of the load
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B7/00—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor
- B24B7/10—Single-purpose machines or devices
- B24B7/16—Single-purpose machines or devices for grinding end-faces, e.g. of gauges, rollers, nuts, piston rings
- B24B7/17—Single-purpose machines or devices for grinding end-faces, e.g. of gauges, rollers, nuts, piston rings for simultaneously grinding opposite and parallel end faces, e.g. double disc grinders
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
Landscapes
- Engineering & Computer Science (AREA)
- Mechanical Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
- Grinding-Machine Dressing And Accessory Apparatuses (AREA)
Abstract
본 발명은 공급된 보조제의 영향 및 피가공물에 작용하는 무게의 영향으로 물질이 피가공물에서 마멸되며, 가공공구의 2개의 판사이에서 웨이퍼형상 피가공물을 가공하는 방법에 관한 것이다. 이 방법에 있어서, 피가공물의 가공시 무게에 의한 피가공물의 하중은 최소한 한번 크게 감소되고, 그후 다시 증가되며, 그리고 보조제의 공급은 무게가 증가됨에 따라 감소된다.The present invention relates to a method of processing a wafer-shaped workpiece between two plates of a processing tool, in which the material is abraded out of the workpiece under the influence of the aid supplied and the weight acting on the workpiece. In this way, the weight of the workpiece by weight in the processing of the workpiece is greatly reduced at least once, and then increased again, and the supply of the supplement decreases with increasing weight.
Description
본 발명은 가공공구의 2개 판사이에서 웨이퍼형상 피가공물을 가공하는 방법에 관한 것이며, 특히 본 발명은 연마 또는 래핑머신에 의한 반도체 웨이퍼의 물질제거가공에 관한 것이다.The present invention relates to a method of processing a wafer-shaped workpiece between two plates of a processing tool, and more particularly, to the material removal processing of a semiconductor wafer by polishing or lapping machine.
반도체 웨이퍼를 연마할 때, 양면 연마와 단일면 연마는 차이가 있다. 이를 위해 사용되는 머신은 시판되고 있으며, 특히 단일면 연마에서는 상부를 연마포로 덮는 작업원판 대신에 피가공물을 고정한 캐리어판이 있는 것이 특징이다. 양면 연마 및 래핑에서는 대조적으로 피가공물이 가공되며, 양면 연마의 경우 연마포로만 덮힌 2개의 작업원판이 있으며, 피가공물은 작업원판 사이에 구비된 템플레이트의 컷아웃(cut out)에 유지된다.When polishing a semiconductor wafer, there is a difference between double-side polishing and single-side polishing. Machines used for this purpose are commercially available, and in particular, in the single-side polishing, there is a carrier plate which fixes the workpiece instead of the working plate which covers the upper part with the polishing cloth. In double sided polishing and lapping, the workpiece is machined in contrast, and in the case of double sided polishing there are two working plates covered only with abrasive cloth, and the workpieces are held in the cutout of the template provided between the working plates.
또한, 1개의 피가공물 또는 복수의 피가공물이 동시에 가공되는가에 따라 단일 웨이퍼가공과 복수 웨이퍼가공은 차이가 있다. 높은 스루풋의 달성 때문에 반도체 웨이퍼의 래핑 및 연마가 일반적으로 복수 웨이퍼가공으로 실시된다. 본 발명은 단일 웨이퍼 및 복수 웨이퍼의 양가공에 적합하다.Further, there is a difference between single wafer processing and multiple wafer processing depending on whether one workpiece or a plurality of workpieces are processed simultaneously. Due to the achievement of high throughput, lapping and polishing of semiconductor wafers are generally performed in multiple wafer processing. The present invention is suitable for the machining of single wafers and multiple wafers.
피가공물의 물질제거 및 평면도향상의 소정효과를 달성하기 위해 래핑시 래핑 연마제가 공급되고 연마시 연마용 연마제가 피가공물에 공급되며, 그리고 피가공물은 무게에 의해 작용된다. 무게는 통상적으로 상부 작업원판 또는 캐리어판을 하부 작업원판 및 그 사이에 놓인 피가공물쪽으로 가압하는 공기식, 유압식 또는전기식 힘전달장치를 통하여 전달된다. 피가공물의 래핑 또는 연마시 최소 1개의 작업원판 또는 캐리어판이 피가공물의 중심을 회전한다.In order to achieve the desired effect of removing the workpiece and improving the plan view, the lapping abrasive is supplied upon wrapping, the abrasive abrasive is supplied to the workpiece upon polishing, and the workpiece is operated by weight. The weight is typically transmitted through pneumatic, hydraulic or electrical force transmissions that press the upper working plate or carrier plate toward the lower working plate and the workpiece placed therebetween. At least one working plate or carrier plate rotates around the workpiece when lapping or polishing the workpiece.
특허 문헌(JP-05177534 A)에서, 초기에는 물질제거를 크게 달성하기 위해 비교적 높은 연마압력으로 연마를 실시하며, 연마종료 무렵에는 연마 반도체 웨이퍼의 평면도(flatness)를 향상시키기 위해 연마압력을 크게 감소시킴으로서, 최적의 스루풋을 가지는 반도체 웨이퍼의 연마방법을 제안하였다.In the patent document (JP-05177534 A), polishing is carried out at a relatively high polishing pressure to achieve large material removal at the beginning, and at the end of polishing, the polishing pressure is greatly reduced to improve the flatness of the polishing semiconductor wafer. As a result, a method of polishing a semiconductor wafer having an optimum throughput has been proposed.
본 발명은 특히 높은 스루풋을 얻을 수 있는 평면형상 피가공물의 물질제거방법을 제공한다.The present invention provides a method for removing substances of planar workpieces, in which particularly high throughput can be obtained.
본 발명은 공급된 보조제의 영향 및 피가공물에 작용하는 무게의 영향으로 물질이 피가공물에서 마멸되며, 가공공구의 2개의 판사이에서 웨이퍼형상의 피가공물을 가공하는 방법에 관한 것이다. 여기서 피가공물의 가공시 무게에 의한 피가공물의 하중은 최소 한번 크게 감소되고, 그후 다시 증가되며, 그리고 보조제의 공급은 무게가 증가됨에 따라 감소된다.The present invention relates to a method of processing a workpiece in the form of a wafer between two plates of a processing tool, in which the material is abraded in the workpiece under the influence of the aid supplied and the weight acting on the workpiece. Wherein the weight of the workpiece by weight in the processing of the workpiece is greatly reduced at least once, and then increased again, and the supply of the supplement decreases with increasing weight.
본 방법은 모든 형의 웨이퍼형상 피가공물의 물질제거가공에 적합하며, 특히 예로써 실리콘 또는 화합물 반도체로 이루어진 반도체 웨이퍼의 래핑 또는 연마에 적합하다.The method is suitable for the dematerialization of all types of wafer-like workpieces, in particular for lapping or polishing of semiconductor wafers made of silicon or compound semiconductors, for example.
본 발명을 더욱 상세히 설명한다. 도면은 시간경과를 통한 2개의 처리파라미터의 프로파일, 즉 피가공물에 작용하는 압축력 및 공급된 래핑제의 양을 나타낸다.The present invention is explained in more detail. The figure shows the profile of the two treatment parameters over time, i.e. the compressive force acting on the workpiece and the amount of lapping agent supplied.
도 1은 종래방법의 프로파일을 나타낸다.1 shows a profile of a conventional method.
도 2는 본 발명에 의한 방법의 전형적인 프로파일을 나타낸다.2 shows a typical profile of the method according to the invention.
도 1 및 도 2에 나타난 공정은 개시단계, 주단계(main phase) 및 마무리단계로 분할된다. 본 발명에 의해 피가공물의 가공시 무게는 최소 한번 크게 감소되고, 그후 다시 증가되며, 또 보조제의 공급은 무게의 증가에 따라 감소되기 때문에 각 단계는 서로 차이가 있다.The process shown in FIGS. 1 and 2 is divided into an initiation step, a main phase and a finishing step. According to the present invention, the weights of the workpieces are greatly reduced at least once, and then increased again, and the steps are different from each other because the supply of the adjuvant decreases with increasing weight.
도 1에 나타난 종래방법에 있어서, 주단계 기간에 일정하게 유지된 래핑제의 공급이 마무리단계에서 정지되며, 그리고 주단계 기간에 달성한 레벨에서 시작하여 피가공물에 작용하는 무게는 경사프로파일을 통하여 영(0)에 가까이 감소된다.In the conventional method shown in Fig. 1, the supply of the lapping agent which is kept constant in the main stage period is stopped at the finishing stage, and the weight acting on the workpiece starting at the level achieved in the main stage period is applied through the inclined profile. It is reduced to near zero.
도 2에 나타난 본 발명에 의한 방법에 있어서, 피가공물에 작용하는 무게는 소정시간 바람직하게는 0.5 ~ 1분간 최소 한번 크게 감소되고 그후 마무리단계전에 다시 증가된다. 무게가 주단계 기간에 달성한 레벨의 최소 20%까지 감소된 다음 이전 레벨로 복귀되는 것이 특히 유리하다. 동시에 무게가 증가함에 따라 레핑제의 공급이 주단계 기간에 달성된 레벨의 0 ~ 50%로 특히 바람직하게는 0 ~ 30%로 감소된다.In the method according to the invention shown in FIG. 2, the weight acting on the workpiece is greatly reduced at least once for a predetermined time, preferably 0.5-1 minute, and then increased again before the finishing step. It is particularly advantageous for the weight to be reduced to at least 20% of the level achieved in the main stage period and then returned to the previous level. At the same time, as the weight increases, the supply of the lepping agent is particularly preferably reduced to 0-50% of the level achieved in the main stage period.
[비교실시예 및 실시예]Comparative Examples and Examples
실리콘으로 제조된 반도체 웨이퍼가 종래의 래핑방법을 사용하여 가공되었으며, 동일형의 기타 반도체 웨이퍼도 래핑제의 무게 및 공급이 도 2(EOC 공정)에 나타낸 본 발명에 의한 프로파일에 따라 변경된 것 이외에는 동일한 방법으로 래핑되었다. 다음의 표는 그때에 실시된 평면도(flatness)측정의 결과이며, 그때 극부 평면도치(GBIR) 및 목표두께와의 두께편차가 분석되었다.A semiconductor wafer made of silicon was processed using a conventional lapping method, and other semiconductor wafers of the same type were identical except that the weight and supply of the lapping agent were changed according to the profile according to the present invention shown in Fig. 2 (EOC process). Wrapped in a way. The following table shows the results of the flatness measurement performed at that time, and the thickness deviation between the pole top view value (GBIR) and the target thickness was analyzed at that time.
본 발명에서는 피가공물의 가공시 피가공물에 작용하는 무게가 소정시간(바람직하게는 0.5 ~ 1분간)최소 한번 감소되고, 그후 마무리단꼐전에 다시 증가되며, 동시에 무게가 증가함에 따라 래핑제의 공급이 주단계 기간에 달성된 레벨의 0 ~ 50%, 특히 바람직하게는 0 ~ 30%로 감소된다.In the present invention, when the workpiece is processed, the weight acting on the workpiece is reduced at least once for a predetermined time (preferably 0.5 to 1 minute), and then increased again before finishing, and at the same time, the supply of the lapping agent increases as the weight increases. It is reduced to 0-50%, particularly preferably 0-30% of the level achieved in the main stage period.
Claims (8)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE10230146.8 | 2002-07-04 | ||
| DE10230146A DE10230146B4 (en) | 2002-07-04 | 2002-07-04 | Process for machining a disc-shaped workpiece |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20040004121A true KR20040004121A (en) | 2004-01-13 |
| KR100555049B1 KR100555049B1 (en) | 2006-03-03 |
Family
ID=29761628
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020030044331A Expired - Lifetime KR100555049B1 (en) | 2002-07-04 | 2003-07-01 | Process for machining a wafer-like workpiece |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US6811473B2 (en) |
| JP (1) | JP4012488B2 (en) |
| KR (1) | KR100555049B1 (en) |
| CN (1) | CN1206081C (en) |
| DE (1) | DE10230146B4 (en) |
| TW (1) | TWI224832B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7840300B2 (en) * | 2006-05-31 | 2010-11-23 | Robert Arthur Harker | Full spectrum lapidary 3D image scanner and method |
| US7976379B2 (en) | 2007-11-09 | 2011-07-12 | Igt | Gaming system and method having configurable bonus game triggering outcomes |
| US8491381B2 (en) | 2011-09-28 | 2013-07-23 | Igt | Gaming system, gaming device and method for providing a multiple player, multiple game bonusing environment |
| US10540855B2 (en) | 2016-09-21 | 2020-01-21 | Igt | Gaming system and method for redistributing funds amongst players of skill games |
| US10475293B2 (en) | 2017-12-11 | 2019-11-12 | Igt | Gaming system and method for redistributing funds amongst players of skill games |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4393628A (en) * | 1981-05-04 | 1983-07-19 | International Business Machines Corporation | Fixed abrasive polishing method and apparatus |
| TW358764B (en) * | 1997-07-07 | 1999-05-21 | Super Silicon Crystal Res Inst | A method of double-side lapping a wafer and an apparatus therefor |
| US6709981B2 (en) * | 2000-08-16 | 2004-03-23 | Memc Electronic Materials, Inc. | Method and apparatus for processing a semiconductor wafer using novel final polishing method |
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2002
- 2002-07-04 DE DE10230146A patent/DE10230146B4/en not_active Expired - Lifetime
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2003
- 2003-06-17 CN CNB031428975A patent/CN1206081C/en not_active Expired - Lifetime
- 2003-06-27 US US10/607,626 patent/US6811473B2/en not_active Expired - Lifetime
- 2003-07-01 KR KR1020030044331A patent/KR100555049B1/en not_active Expired - Lifetime
- 2003-07-01 JP JP2003189678A patent/JP4012488B2/en not_active Expired - Lifetime
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Also Published As
| Publication number | Publication date |
|---|---|
| CN1468685A (en) | 2004-01-21 |
| DE10230146A1 (en) | 2004-01-22 |
| JP2004034285A (en) | 2004-02-05 |
| US6811473B2 (en) | 2004-11-02 |
| TW200401405A (en) | 2004-01-16 |
| JP4012488B2 (en) | 2007-11-21 |
| US20040043709A1 (en) | 2004-03-04 |
| TWI224832B (en) | 2004-12-01 |
| DE10230146B4 (en) | 2004-11-04 |
| KR100555049B1 (en) | 2006-03-03 |
| CN1206081C (en) | 2005-06-15 |
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