KR20040001951A - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
- Publication number
- KR20040001951A KR20040001951A KR1020020037285A KR20020037285A KR20040001951A KR 20040001951 A KR20040001951 A KR 20040001951A KR 1020020037285 A KR1020020037285 A KR 1020020037285A KR 20020037285 A KR20020037285 A KR 20020037285A KR 20040001951 A KR20040001951 A KR 20040001951A
- Authority
- KR
- South Korea
- Prior art keywords
- film
- iridium
- semiconductor device
- contact hole
- interlayer insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000000034 method Methods 0.000 title claims abstract description 20
- 239000011229 interlayer Substances 0.000 claims abstract description 19
- 239000010410 layer Substances 0.000 claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 7
- 239000002184 metal Substances 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000004020 conductor Substances 0.000 claims abstract description 6
- 229910052741 iridium Inorganic materials 0.000 claims description 16
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 12
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 11
- 239000003990 capacitor Substances 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 229910052697 platinum Inorganic materials 0.000 claims description 4
- HTXDPTMKBJXEOW-UHFFFAOYSA-N dioxoiridium Chemical compound O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 claims 2
- 229910000457 iridium oxide Inorganic materials 0.000 claims 2
- 238000010030 laminating Methods 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910001385 heavy metal Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000010970 precious metal Substances 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 고집적 반도체 장치의 콘택홀을 안정적으로 형성할 수 있는 반도체 장치의 제조방법을 제공하기 위한 것으로, 이를 위해 본 발명은 활성영역이 형성된 반도체 기판에 층간절연막을 형성하는 단계; 상기 층간절연막 상에 상기 활성영역을 노출시키는 콘택홀을 형성하기 위한 하드마스크용 금속막 패턴을 형성하는 단계; 상기 금속막 패턴을 이용하여 상기 층간절연막을 제거하여 상기 콘택홀을 형성하는 단계; 상기 콘택홀을 도전성 물질로 매립하여 콘택플러그를 형성하는 단계를 포함하는 반도체 장치의 제조방법이 제공된다.The present invention is to provide a method for manufacturing a semiconductor device capable of stably forming a contact hole of a highly integrated semiconductor device, the present invention comprises the steps of forming an interlayer insulating film on a semiconductor substrate formed with an active region; Forming a metal layer pattern for a hard mask to form a contact hole exposing the active region on the interlayer insulating layer; Removing the interlayer insulating layer using the metal layer pattern to form the contact hole; A method of manufacturing a semiconductor device is provided, including forming a contact plug by filling the contact hole with a conductive material.
Description
본 발명은 반도체 장치의 제조기술에 관한 것으로, 특히 반도체 장치의 콘택플러그에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technology, and more particularly to a contact plug of a semiconductor device.
반도체 소자, 특히 디램(DRAM)이 고집적화 되어 감에 따라 워드 라인, 비트 라인등과 같은 도전성 패턴들은 그 간격이 점점 줄어들고 있고 있으며, 콘택 영역 또한 그 크기가 줄어들고 있다. 콘택 영역의 마진이 충분할 경우에는 포토레지스트 패턴을 마스크로 한 일반적인 식각 공정으로 콘택홀을 형성하고, 이 콘택홀과 배선 영역에 도전성 물질을 매립하여 하부 도전층과 전기적으로 연결하였다.As semiconductor devices, especially DRAMs, have become highly integrated, conductive patterns such as word lines, bit lines, and the like are becoming smaller, and contact areas are also decreasing in size. When the contact region had sufficient margin, a contact hole was formed by a general etching process using a photoresist pattern as a mask, and a conductive material was buried in the contact hole and the wiring region to be electrically connected to the lower conductive layer.
그러나, 소자가 점점 고집적화 되어감에 따라 콘택영역의 마진이 부족하여 자기정렬 콘택 공정을 통해 콘택홀을 형성하는 방식이 도입되었다. 또한, 콘택홀의 크기가 작아짐에 따라 도전성 물질로 콘택홀을 양호하게 매립하기 어려워 매립 특성이 우수한 도전성 물질을 사용하여 콘택홀만을 매립시키는 콘택 플러그 방식이 널리 채택되고 있다.However, as devices are becoming more and more integrated, a method of forming contact holes through self-aligned contact processes has been introduced due to a lack of margin of contact regions. In addition, as the size of the contact hole decreases, it is difficult to bury the contact hole with a conductive material satisfactorily, and a contact plug method for filling only the contact hole using a conductive material having excellent embedding characteristics has been widely adopted.
콘택플러그형성에 도핑된(Doping) 폴리 실리콘이나 텅스텐(W)을 사용하여 콘택플러그를 형성하나, 최근에는 도핑된 폴리 실리콘보다 상대적으로 저항이 낮은 텅스텐 플러그를 주로 사용하고 있다.Although contact plugs are formed using doped polysilicon or tungsten (W) for forming contact plugs, tungsten plugs having a relatively lower resistance than doped polysilicon are mainly used.
한편, 반도체 장치 특히 메모리 장치가 점점 더 고집적화 됨에 따라 콘택홀의 깊이도 점점 깊어지고 그 폭은 점점더 좁아져 종래에 감광막을 가지고 콘택홀을 형성하는 방법이 한계에 부딪히고 있다.On the other hand, as semiconductor devices, especially memory devices, are becoming more and more integrated, the depth of contact holes is getting deeper and their widths are getting narrower. Therefore, the method of forming contact holes with a photosensitive film has hit a limit.
도1a에 내지 도1b는 종래기술에 의한 반도체 장치의 콘택플러그 제조방법을 보여주는 공정단면도이다.1A to 1B are cross-sectional views illustrating a method of manufacturing a contact plug of a semiconductor device according to the prior art.
도1a에 도시된 바와 같이, 먼저 활성영역(11)이 형성된 기판(10)에 층간절연막(12)을 형성하고, 이어서 콘택홀형성을 위한 감광막패턴(13)을 형성한다.As shown in FIG. 1A, an interlayer insulating film 12 is first formed on a substrate 10 on which an active region 11 is formed, and then a photoresist pattern 13 for forming a contact hole is formed.
이어서 도1b에 도시된 바와 같이, 감광막패턴(13)을 이용하여 층간절연막(12)을 선택적으로 식각하여 콘택홀(14)를 형성한다.Subsequently, as shown in FIG. 1B, the interlayer insulating film 12 is selectively etched using the photosensitive film pattern 13 to form the contact hole 14.
그러나 반도체 장치가 점점 고집적화 됨에 따라 콘택홀의 깊이가 점점 깊어지고 폭은 좁아져 하부의 감광막을 이용하여 식각공정을 진행하게 되면 식각선택비부족등으로 안정적인 콘택홀의 형성이 어려워 지고, 이에 대해서 도1b의 'A'에 도시되어 있다.However, as semiconductor devices become more highly integrated, the depth of contact holes becomes deeper and the width becomes narrower. Therefore, when the etching process is performed using the lower photoresist film, it is difficult to form stable contact holes due to insufficient etching selectivity. It is shown in 'A'.
따라서 감광막 패턴 대신에 층간절연막(12)과 보다큰 식각선택비를 가지는 새로운 물질- 예컨대 폴리실리콘막, 또는 TiN막등-을 하드마스크로 콘택홀을 형성하고 있다.Therefore, instead of the photosensitive film pattern, a contact hole is formed by using the interlayer insulating film 12 and a new material having a larger etching selectivity such as a polysilicon film or a TiN film as a hard mask.
그러나 하드마스크를 사용하여 콘택홀을 형성하고 나면, 후속공정에서 이를 제거할 때 하부구조에 데미지를 가하게 되고 이로 인해 콘택플러그가 변형되는 문제점을 발생시킨다. 변형된 콘택플러그는 저항값이 증가되는등 반도체 장치의 동작상의 신뢰성이 저하되는 문제점을 일으킨다.However, after the contact hole is formed using the hard mask, damage is caused to the substructure when the contact hole is removed in the subsequent process, thereby causing a problem in that the contact plug is deformed. The deformed contact plug causes a problem of deterioration in operational reliability of the semiconductor device such as an increase in resistance value.
본 발명은 고집적 반도체 장치의 콘택홀을 안정적으로 형성할 수 있는 반도체 장치의 제조방법을 제공함을 목적으로 한다.An object of the present invention is to provide a method of manufacturing a semiconductor device capable of stably forming contact holes of a highly integrated semiconductor device.
도1a에 내지 도1b는 종래기술에 의한 반도체 장치의 콘택플러그 제조방법을 보여주는 공정단면도.1A to 1B are cross-sectional views showing a method of manufacturing a contact plug of a semiconductor device according to the prior art;
도2a 내지 도2d는 본 발명의 바람직한 실시예에 따른 반도체 장치의 콘택플러그 제조방법을 보여주는 공정단면도.2A through 2D are cross-sectional views illustrating a method of manufacturing a contact plug in a semiconductor device according to a preferred embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
20 : 기판20: substrate
21 : 활성영역21: active area
22 : 층간절연막22: interlayer insulating film
23 : 하드마스크용 이리듐막23: Iridium film for hard mask
24 : 감광막 패턴24: photosensitive film pattern
상기의 목적을 달성하기 위한 본 발명은 활성영역이 형성된 반도체 기판에 층간절연막을 형성하는 단계; 상기 층간절연막 상에 상기 활성영역을 노출시키는 콘택홀을 형성하기 위한 하드마스크용 금속막 패턴을 형성하는 단계; 상기 금속막 패턴을 이용하여 상기 층간절연막을 제거하여 상기 콘택홀을 형성하는 단계; 상기 콘택홀을 도전성 물질로 매립하여 콘택플러그를 형성하는 단계를 포함하는 반도체 장치의 제조방법이 제공된다.The present invention for achieving the above object comprises the steps of forming an interlayer insulating film on a semiconductor substrate formed with an active region; Forming a metal layer pattern for a hard mask to form a contact hole exposing the active region on the interlayer insulating layer; Removing the interlayer insulating layer using the metal layer pattern to form the contact hole; A method of manufacturing a semiconductor device is provided, including forming a contact plug by filling the contact hole with a conductive material.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
도2a 내지 도2d는 본 발명의 바람직한 실시예에 따른 반도체 장치의 콘택플러그 제조방법을 보여주는 공정단면도이다.2A through 2D are cross-sectional views illustrating a method of manufacturing a contact plug in a semiconductor device according to an embodiment of the present invention.
도2a에 도시된 바와 같이, 먼저 활성영역(21)이 형성된 기판(20)에 층간절연막(22)을 형성하고, 그 상부에 하드마스크용 이리듐막(23)을 1000Å 두께로 형성한다. 이어서 콘택홀형성을 위한 감광막패턴(13)을 형성한다.As shown in FIG. 2A, an interlayer insulating film 22 is first formed on a substrate 20 on which an active region 21 is formed, and an iridium film 23 for hard mask is formed on the upper portion of the substrate 20. Subsequently, a photoresist pattern 13 for forming a contact hole is formed.
이어서 도2b에 도시된 바와 같이, 감광막패턴(13)을 이용하여 하드마스크용 이리듐막(23)을 선택적으로 제거하여 패터닝하고 감광막패턴을 제거한다. 이 때 Ar/Cl2가스분위기로 Ar가스는 30~50sccm, Cl2가스는 5 ~10sccm의 범위에서 이리듐막을 패터닝하여 비교적 무거운 이리듐 중금속의 원할한 배출을 위하여 기판 온도를 80℃이상의 고온으로 유지시켜 공정을 진행한다.Subsequently, as illustrated in FIG. 2B, the hard mask iridium film 23 is selectively removed using the photoresist pattern 13 to pattern and remove the photoresist pattern. At this time, the Ar / Cl 2 gas atmosphere is used to pattern the iridium film in the range of 30 to 50 sccm and Cl 2 gas to 5 to 10 sccm. Proceed with the process.
이어서 도2c 패터닝된 하드마스크용 이리듐막(23)을 이용하여 층간절연막(22)을 식각하여 콘택홀(23)을 형성한다. 이 때 층간절연막(22)은 통상적으로 산화막계열의 절연막과 질화막계열의 절연막이 적층되어 형성되어 있는데 산화막계열의 절연막 식각을 위하여 C4F8/O2/CO/Ar의 혼합가스를 이용하여 공정을 진행하고, 질화막계열의 절연막 식각을 위하여는 CHF3/O2/CO/Ar의 혼합가스를 이용하여 공정을 진행한다.Subsequently, the interlayer insulating layer 22 is etched using the iridium layer 23 for hard mask patterned in FIG. 2C to form the contact hole 23. At this time, the interlayer insulating film 22 is formed by stacking an insulating film of an oxide film series and an insulating film of a nitride film series, using a mixed gas of C 4 F 8 / O 2 / CO / Ar for etching the insulating film of the oxide film series In order to perform the etching of the insulating film of the nitride film series, the process is performed using a mixed gas of CHF 3 / O 2 / CO / Ar.
이리듐은 식각반응성이 거의 없는 중금속이기 때문에 층간절연막과의 식각선택비가 50:1 이상인 고선택비의 식각이 가능하여 이리듐을 하드마스크로 사용하게 되면, 0.1㎛이하의 얇은 이리듐막으로 1㎛ 이상의 깊은 콘택홀 식각이 가능하다.Since iridium is a heavy metal with little etching reactivity, it is possible to etch a high selectivity with an etching selectivity of 50: 1 or more with an interlayer insulating film. When iridium is used as a hard mask, a thin iridium film of 0.1 μm or less can be used for deeper than 1 μm. Contact hole etching is possible.
또한, 이리듐은 최근의 고집적 메모리소자의 캐패시터 하부전극으로 사용되기 때문에 제거할 필요가 없다. 따라서 하드마스크를 제거할 때 생기는 데미지로 콘택홀의 변형이 생기지 않는다. 또한 하부전극으로 사용되면 층간절연막과의 고선택비가 가능한 귀금속인 백금을 전술한 바와 같이 콘택홀 식각을 위한 하드마스크로 사용할 수 있다.In addition, iridium does not need to be removed because it is used as a capacitor lower electrode of a recent high density memory device. Therefore, the damage caused when removing the hard mask does not cause contact hole deformation. In addition, when used as a lower electrode, platinum, a precious metal capable of high selectivity with an interlayer insulating layer, may be used as a hard mask for etching contact holes as described above.
이어서 도2d에 도시된 바와 같이, 콘택홀(23)이 매립되도록 텅스텐을 증착하고 에치백하거나 화학적기계적연마 공정을 이용하여 텅스텐 콘택플러그(24)를 형성한다. 이 때 SF6가스를 30 ~ 80 sccm 범위로 N2가스를 10 ~ 30 sccm 범위로 하여공정을 진행한다.Next, as shown in FIG. 2D, tungsten is deposited and etched back so that the contact hole 23 is buried, or a tungsten contact plug 24 is formed using a chemical mechanical polishing process. At this time, the SF 6 gas is in the range of 30 ~ 80 sccm N 2 gas in the range of 10 ~ 30 sccm proceeds.
이어서 콘택플러그(24) 상부에 이리윰막(23)을 채우고, 그 상부에 IrO2막과 Pt막을 형성하고 패터닝하여 캐패시터하부전극을 형성한다. Pt막(26)과 IrO2막(25)은 이리듐막과 함께 캐패시터 하부전극으로 사용되는데 도시된바와 같이 Pt/IrO2/Ir 로 적층된 구조로 되도록한다.Subsequently, the irreplacement film 23 is filled on the contact plug 24, and an IrO 2 film and a Pt film are formed and patterned on the contact plug 24 to form a capacitor lower electrode. The Pt film 26 and the IrO 2 film 25 are used as a capacitor lower electrode together with the iridium film, so as to have a stacked structure of Pt / IrO 2 / Ir as shown.
따라서 하드마스크용으로 형성한 이리듐막(23) 패턴을 제거하지 않아도 되어 후속공정에서 하드마크용 막을 제거할 때 생기는 콘택플러그의 데미지는 없게된다.Therefore, it is not necessary to remove the iridium film 23 pattern formed for the hard mask, and there is no damage of the contact plug caused when the hard mark film is removed in a subsequent step.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
본 발명에 의해 안정적인 콘택플러그 형성공정을 안정적으로 진행할 수 있어 반도체 제조공정의 신뢰도가 향상되는 효과를 기대할 수 있다.According to the present invention, the stable contact plug forming process can be stably performed, and thus the effect of improving the reliability of the semiconductor manufacturing process can be expected.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020037285A KR20040001951A (en) | 2002-06-29 | 2002-06-29 | Method for fabricating semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020037285A KR20040001951A (en) | 2002-06-29 | 2002-06-29 | Method for fabricating semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20040001951A true KR20040001951A (en) | 2004-01-07 |
Family
ID=37313681
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020020037285A Withdrawn KR20040001951A (en) | 2002-06-29 | 2002-06-29 | Method for fabricating semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20040001951A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100560821B1 (en) * | 2004-08-17 | 2006-03-13 | 삼성전자주식회사 | Capacitor Formation Method of Semiconductor Device |
-
2002
- 2002-06-29 KR KR1020020037285A patent/KR20040001951A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100560821B1 (en) * | 2004-08-17 | 2006-03-13 | 삼성전자주식회사 | Capacitor Formation Method of Semiconductor Device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR19980024825A (en) | How to Form Contact Holes / Through Holes | |
| US7910485B2 (en) | Method for forming contact hole using dry and wet etching processes in semiconductor device | |
| KR20040001951A (en) | Method for fabricating semiconductor device | |
| US6558999B2 (en) | Method for forming a storage electrode on a semiconductor device | |
| JP2005072176A (en) | Semiconductor device and manufacturing method therefor | |
| KR100753031B1 (en) | Contact hole formation method of semiconductor device | |
| KR100321733B1 (en) | A method for fabricating semiconductor device using nitride film for preventing oxidation metal bit line | |
| KR19990033881A (en) | Method for forming self-aligned contacts in semiconductor devices | |
| KR100859254B1 (en) | Capacitor manufacturing method of semiconductor device | |
| KR100568395B1 (en) | Method of manufacturing semiconductor device using metal contact plug | |
| KR100532954B1 (en) | Method for forming contact of semiconductor device | |
| KR20010048350A (en) | Method for fabricating a semiconductor device | |
| KR20050002005A (en) | Method for fabricating semiconductor device capable of forming storage node contact hole and insulating spacer of bit line | |
| KR20060000964A (en) | Manufacturing Method of Semiconductor Device | |
| KR100399935B1 (en) | Semiconductor device manufacturing method | |
| KR100780616B1 (en) | Manufacturing Method of Semiconductor Device | |
| KR100443244B1 (en) | Method for forming a self aligned contact | |
| KR20040024685A (en) | Method for fabricating semiconductor device with buried-bitline | |
| KR20010036161A (en) | Method for forming a contact hole of a self-aligned contact using a hard mask | |
| KR20030002110A (en) | Method for forming self aligned contact plug | |
| KR20040003960A (en) | Method for fabricating semiconductor device | |
| KR20020051154A (en) | Method for forming self-aligned contact plug of semiconductor device | |
| KR20020018874A (en) | Method for manufacturing a contact of storage node electrode in memory device | |
| KR20020065123A (en) | Method for fabricating a landing plug of semiconductor device | |
| KR20030059440A (en) | Method of forming capacitor of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 20020629 |
|
| PG1501 | Laying open of application | ||
| PC1203 | Withdrawal of no request for examination | ||
| WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |