KR20040001492A - Manufacturing method for reducing a resistance of a gate electrode using damascene method in a semiconductor device - Google Patents

Abstract

The present invention relates to a method of manufacturing a semiconductor device that reduces the resistance of a gate electrode by using a damascene process. The method of manufacturing a semiconductor device according to the present invention comprises forming a nitride film on a substrate and forming an oxide film on the resultant. Doing; Exposing the oxide film on which a gate electrode is to be formed to form a photoresist film pattern on the oxide film; Forming a trench by plasma etching the oxide film of the portion to be a gate electrode using the photoresist pattern as a mask; Forming a polysilicon film on the surface of the oxide film including the trench; Forming a gate electrode by planarizing the polysilicon layer and the oxide layer using a chemical mechanical polishing (CMP) process; Forming a silicide on the surface of the gate electrode after etching the entire oxide layer by plasma etch back etching; Etching the oxide film and the nitride film to form an LDD spacer on sidewalls of a gate electrode; And forming silicide on the surface of the active region.

Description

Manufacturing method for reducing a resistance of a gate electrode using damascene method in a semiconductor device}

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device to reduce the resistance of the gate electrode using a damascene process.

In the manufacturing process of a semiconductor device, the formation method of the gate electrode is very important. As the device size is reduced and the gate oxide film is thinned to 20 kPa or less in forming the gate electrode, the uniformity of the gate oxide film and its characteristic formation technique This is very difficult and also the plasma etching process is difficult.

In view of this, the conventional gate forming technique will be described as follows.

First, a gate oxide film is formed by a diffusion method, and a polysilicon film to be used as a gate electrode is formed thereon.

Then, patterning is performed using a photolithography process and an etching process is performed by plasma etching to implement a gate electrode. In addition, in the 0.15 탆 CMOS technology, the doping degree of n-MOS and p-MOS is different when the gate is formed.

In other words, in the case of n-MOS, since the p-MOS region is masked and phosphorus (P) is first doped into the n-MOS region by an ion implantation process, the gate electrode films of the n-MOS and p-MOS regions are different from each other. The following problems arise from being different.

In the complementary transistor (CMOS), since n-MOS and p-MOS are simultaneously implemented, the polysilicon of the gate electrodes of n-MOS and p-MOS has different doping degrees, thereby allowing n-MOS and p-MOS. Since each has different physical properties, there is a problem that the etching shapes are different due to different etching speeds during plasma etching.

In addition, since the gate oxide film is too thin, there is a problem that it is difficult to control the transient etching during plasma etching. In other words, too much transient etching may invade the gate oxide and etch the silicon substrate under the gate oxide due to the punch through of the gate oxide, and if too little is excessively etched, the residue remains after etching. There is a problem of generating a bridge.

On the other hand, in the prior art, a spacer was formed on the gate sidewall when the gate was formed and the transistor element was formed for proper device implementation. That is, in the conventional spacer forming technique on the gate sidewall, an oxide film and a nitride film are formed on the gate electrode, and then a plasma etching process is performed by using a front surface etching without a mask, and the insulating layer is formed on the sidewall of the gate electrode according to the anisotropic etching characteristic of the plasma etching. It is a technique of forming a spacer of a nitride film.

This conventional spacer formation technique has the following problems.

When the spacer is formed, its width is difficult to control, and when the plasma overetching is severe during the entire surface etching, there is a problem in that the device characteristics are deteriorated by invading the active region of the source drain and the field oxide layer and generating a leakage current.

In addition, it is essential to implement a high-speed device is required to lower the resistance of the gate electrode to less than 10Ω, there is a method of changing the gate material to a metallic material to implement this.

However, this method has a disadvantage in that it is difficult to etch the metallic material and deteriorates the characteristics of the gate oxide film when forming the gate.

Another method of lowering the resistance of the gate electrode to 10 kΩ or less is to use a silicide process of forming a metal film on the gate electrode, that is, a gate formed of polysilicon, which is a general gate material, and then reacting with the polysilicon thereon. To form a metallic material.

However, this method also requires a subsequent process of many heat treatment processes due to the thermal instability of the silicide, and thus has the disadvantage of deteriorating the resistance of the gate electrode.

This is known to be caused by the growth of the grain (grain) of polysilicon by heat treatment, especially in the case of applying the non-silicide process (Non-Silicide) the resistance of the gate electrode during the etching of the silicide region becomes even worse.

Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, by using a damascene process in forming the gate and the spacer on the gate sidewalls to form the gate and LDD spacers and to form the silicide of the gate electrode to the gate side The purpose is to provide a method of manufacturing a semiconductor device to reduce the gate resistance.

In addition, another object of the present invention is to provide a method for manufacturing a semiconductor device that prevents gate punch through, silicon substrate infringement, etc., which may adversely affect the device when the gate electrode is formed using a damascene process during gate patterning.

Another object of the present invention is to apply the gate forming technique of the present invention and to form LDD spacers by etching between gate electrodes, thereby preventing the invasion of the active region of the source drain due to the transient etching generated during plasma etching. The present invention also provides a method of manufacturing a semiconductor device capable of controlling the width of an LDD spacer by adjusting the excessive etching time of etching.

Another object of the present invention is to form a silicide having a thickness of preferably 135 to 165 Å on a gate electrode surface in a silicide process of forming a gate as a metal film to form a high-speed device, and then to form an LDD spacer. In addition, when a silicide having a thickness of preferably 135 to 165 상 에 is formed on the surface of the active region, it is also formed on the surface of the gate electrode to provide a method of manufacturing a semiconductor device which increases the thermal stability of the silicide.

Another object of the present invention is to provide a method for manufacturing a semiconductor device that can form a gate silicide on the sidewall of the upper gate to increase the silicide formation area and prevent the degradation of the silicide resistance.

The present invention for achieving the above object, forming a nitride film on a substrate and forming an oxide film on top of the result; Exposing the oxide film on which a gate electrode is to be formed to form a photoresist film pattern on the oxide film; Forming a trench by plasma etching the oxide film of the portion to be a gate electrode using the photoresist pattern as a mask; Forming a polysilicon film on the surface of the oxide film including the trench; Forming a gate electrode by planarizing the polysilicon layer and the oxide layer using a chemical mechanical polishing (CMP) process; Forming a silicide on the surface of the gate electrode after etching the entire oxide layer by plasma etch back etching; Etching the oxide film and the nitride film to form an LDD spacer on sidewalls of a gate electrode; And forming silicide on the surface of the active region.

1A to 1G are cross-sectional views of respective processes illustrating a method of manufacturing a semiconductor device using a damascene process according to the present invention.

(Explanation of symbols for the main parts of the drawing)

5: silicon substrate 10: field oxide film

20: nitride film 30, 30a: oxide film

40: photoresist film 45: trench

50 polysilicon film 55 gate electrode

60: silicide on the gate electrode surface

65: silicide on active surface

70: LDD spacer

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1A illustrates a process of forming the nitride film 20 after the isolation process and forming the oxide film 30 thereon.

Referring to FIG. 1A, after forming the field oxide film 10, a nitride film 20 having a thickness of 200 μs is formed. The nitride film 20 forms a trench 45 for forming the gate electrode 55 in FIG. 1C to serve as an etching end point when the oxide film 30 is etched. That is, this is possible because the selectivity with the nitride film is high when the oxide film 30 is etched, and if the etch stop is not performed during the etching of the oxide film 30, the silicon substrate 5, which is the lower layer, is etched and the lower layer invasion occurs. After the nitride film 20 is formed, the oxide film 30 is formed to have a thickness of 2000 GPa corresponding to the formation height of the gate electrode 55.

FIG. 1B illustrates a process of forming the oxide film 30 to the thickness of the gate electrode 55 to form the gate electrode 55, and then patterning a portion of the gate electrode 55 using the photoresist film 40. Figure is shown.

Referring to FIG. 1B, an upper portion of the oxide layer 30 corresponding to a portion where the gate electrode 55 is to be formed is patterned by a mask lithography process. The thickness of the photoresist film 40 required at this time may be as thin as 5000 mm or less, so that patterning of 0.15 m or less, which is the width of the gate electrode 55, is possible. The reason why the thickness of the photoresist film 40 can be thin as described above is because the etching rate of the oxide film 30 of 2000 kV is etched because the selectivity of the oxide film 30 with the photoresist film 40 is 2: 1 or more. This is because the 2000 nm oxide film 30 can be etched with the resist film 40 as well.

FIG. 1C illustrates a process of forming a portion to be the gate electrode 55 by plasma etching an oxide film of the portion to be the gate electrode 55 as patterned.

Referring to FIG. 1C, after the mask patterning of FIG. 1B, plasma etching is performed to form the trench 45. At this time, in the first step of the plasma etching, in a 18C ₄ F ₈ , 10O ₂ and 420Ar gas atmosphere, a pressure of about 28 to 32mT, preferably a pressure of 30mT, about 2090W and about 2310W preferably about 2200W and about 1600W Power, and for about 70 seconds, about 20 to 22 mm, preferably 21 mm gap, about 9.5 to 10.5 T, preferably 10 T helium gas pressure, about 33 to 36 T preferably 35 T helium gas pressure, about 28.5 to 31.5 C is preferably carried out at an upper temperature of 30 ° C., a side wall temperature of approximately 47.5-52.5 ° C. preferably 50 ° C. and a bottom temperature of approximately 9.5-10.5 ° C. preferably 10 ° C.

Further, in the second stage of plasma etching, in a gas atmosphere of 20CHF ₃ , 20O ₂ and 400Ar, a pressure of approximately 47 to 52 mT preferably 50 mT, approximately maximum 950-1050 W preferably 1000 W and approximately minimum 190-210 W preferably 200 W Between the power source, and for about 10 seconds, approximately 20-22 mm, preferably 20 mm gap, approximately 9.5-10.5T, preferably 10T helium gas pressure, approximately 33-36T preferably 35T helium gas pressure, approximately 28.5- 31.5 ° C., preferably at a top temperature of 30 ° C., at a side wall temperature of approximately 47.5 to 52.5 ° C. preferably at 50 ° C., and at a bottom temperature of approximately 9.5 to 10.5 ° C. preferably at 10 ° C. In this case, as shown in FIG. 1C, in order not to invade the silicon substrate 5, the etching end point of the nitride film 20, which is formed initially, should be etched by increasing the selectivity between the oxide film 30 and the nitride film 20. After the etching, a 20 占 thick gate oxide film (not shown) is formed by the diffusion method.

FIG. 1D is a view illustrating a process of forming a polysilicon film 50 as an electrode material on an oxide film 30 to form a gate to be an electrode, and FIG. 1E is chemical mechanical polishing (hereinafter referred to as “CMP”). The process of planarizing the polysilicon film 50 and the oxide film 30 using the process "is called."

As shown in FIG. 1D, the polysilicon film 50 is formed to a thickness of 7000 kPa. Then, the polysilicon film 50 is planarized together with the oxide film 30 using a CMP process to form the gate electrode 55 as shown in FIG. 1E. When the planarization process is performed, the gate electrode 55 is formed. When the gate electrode 55 is formed by the damascene process, the grains of the polysilicon film 50 are evenly planarized.

Next, the 300 nm thick oxide film 30 is etched back and etched by a plasma etch back etching process. In this case, the silicide 60 may be formed on the sidewalls of the gate electrode 55. The plasma etchback etching may be performed at 18C ₄ F ₈ , 10O ₂ and 420Ar gas atmospheres, at a pressure of approximately 28 to 32 mT, preferably at a pressure of 30 mT, approximately up to 2090 W and approximately at least 2310 W, preferably at most 2200 W and at least 1600 W, And for about 70 seconds, about 20-22 mm preferably 21 mm gap, about 9.5-10.5T preferably 10T helium gas pressure, about 33-36T preferably 35T helium gas pressure, about 28.5-31.5 ° C. preferably Is carried out at an upper temperature of 30 ° C., a side wall temperature of approximately 47.5 to 52.5 ° C. preferably 50 ° C., and a bottom temperature of approximately 9.5 to 10.5 ° C. preferably 10 ° C.

Therefore, when the silicide 60 is formed on the surface of the gate electrode 55, the silicide formation area becomes wider, thereby ensuring thermal stability.

Referring to FIG. 1F, a silicide, preferably a titanium film 60 having a thickness of 135 to 165 Å is formed on the gate electrode 55. The silicide 60 in the undesired region (ie, region other than the gate electrode) is then etched away.

Referring to FIG. 1G, the nitride layer 20 and the oxide layer 30a are etched to form the LDD spacer 70, wherein the oxide layer 30a is etched using BOE (Buffered Oxide Etchant), and the nitride layer ( 20) is etched using phosphoric acid. When the silicon substrate 5 is etched to the end point where the silicon substrate 5 is exposed by the BOE etchant, the LDD spacer 70 as shown in FIG. 1G may be formed due to the isotropic etching characteristic. In addition, the width of the LDD spacer 70 may be adjusted by adjusting the transient etching time.

After the LDD spacer 70 is formed, a silicide 65 having a thickness of 135 to 165 占 퐉 is preferably formed on the surface of the active region in the same manner as the silicide 60 on the gate electrode 55. At this time, the silicide 60 is formed again on the surface of the gate electrode 55. When the silicide is formed in this manner, the silicide 60 is formed on the gate electrode 55 to have a thickness of 300 占 퐉, thereby increasing the thermal stability of the silicide, thereby preventing the deterioration of the gate resistance, and the gate electrode 55 in the active region. Since the silicide 65 having a thickness of preferably 135 to 165 까지 can be formed on the upper sidewall, the degradation of the silicide and the resistance value itself can be reduced. That is, in the past, when silicides 60 and 65 are simultaneously formed on the gate electrode and the active region, thickening of the silicides 60 and 65 causes deterioration of the contact leakage characteristics. However, the formation of the silicides in the above-described manner prevents deterioration of the contact leakage characteristics. have.

As described above, the present invention can prevent the gate punch through, silicon substrate invasion, etc., which may adversely affect the device by forming a gate electrode using a damascene process during gate patterning.

In addition, in the present invention, by applying the above-described gate forming technique and forming the LDD spacer by etching between the gate electrodes, it is possible to prevent the invasion of the active region of the source drain due to the transient etching that occurred during the plasma etching, and the transient etching time By adjusting the width of the LDD spacer can be adjusted.

In addition, in the silicide process of forming a gate as a metal film to form a high-speed device, firstly, a silicide 60 having a thickness of preferably 135 to 165 Å is formed on the gate electrode 55, and then an LDD spacer is formed. After the formation, the silicide 65, which is preferably 135 to 165 mm thick, is also formed on the surface of the gate electrode 55 when the silicide 65 is formed on the surface of the active region, thereby increasing the thermal stability of the silicide. In addition, the silicide is formed on the sidewalls of the upper portion of the gate electrode 55 to increase the silicide formation area, thereby preventing the silicide from deteriorating in resistance.

Although the preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the above-described embodiments, and the present invention is not limited to the above-described claims, and the present invention is not limited to the scope of the present invention. Anyone with knowledge will be able to make various changes.

Claims (9)

In the method of manufacturing a semiconductor device to reduce the resistance of the gate electrode using a damascene process, Forming a nitride film on the substrate and forming an oxide film on top of the resultant; Exposing the oxide film on which a gate electrode is to be formed to form a photoresist film pattern on the oxide film; Forming a trench by plasma etching the oxide film of the portion to be a gate electrode using the photoresist pattern as a mask; Forming a polysilicon film on the surface of the oxide film including the trench; Forming a gate electrode by planarizing the polysilicon layer and the oxide layer using a chemical mechanical polishing (CMP) process; Forming a silicide on the surface of the gate electrode after etching the entire oxide layer by plasma etch back etching; Etching the oxide film and the nitride film to form an LDD spacer on sidewalls of a gate electrode; And Forming a silicide on the surface of the active region. The method of claim 1, wherein in the first step of plasma etching, a nitride film having a thickness of 150 to 250 microseconds is selected as an etching end point. The method of claim 1, wherein a selectivity ratio between the oxide layer and the photoresist layer during the plasma etching is about 2: 1 or more. The method of claim 1, wherein the forming of the spacer is performed by etching an oxide layer with a buffered oxide etch (BOE) and etching the nitride layer with a phosphate solution. The method of claim 1, wherein a width of the spacer is adjustable by adjusting a transient etching time. 2. The method of claim 1, wherein the thickness of the silicide on the surface of the gate electrode is greater than the thickness of the silicide on the surface of the active region. The method of claim 1, wherein the silicide forming step further includes forming silicide on the surface of the gate electrode when the silicide having a thickness of 135 to 165 Å is formed on the surface of the active region. A manufacturing method of a semiconductor device, characterized in that formed to a thickness of 330Å. 8. The method of claim 7, wherein silicide is formed up to sidewalls of the gate electrode when silicide is formed on the surface of the active region. The method of manufacturing a semiconductor device according to claim 1, wherein when silicide is formed on the surface of the gate electrode, silicide is also formed on sidewalls of the gate electrode to increase the silicide formation area.