KR20030002837A - A method for manufacturing of semiconductor device with elector static discharge protector - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an electrostatic protection device capable of reducing and eliminating input capacitance of a high speed semiconductor device and improving ESD characteristics. The present invention relates to a gate electrode formed on a first conductive semiconductor substrate, and to a gate electrode. A second conductivity type low concentration drain region formed in the semiconductor substrate on one side of the electrode, a second conductivity type high concentration drain region selectively formed in the second conductivity type low concentration drain region, and a second formed on the semiconductor substrate on the other side of the gate electrode A second conductive high concentration source region, an interlayer insulating film formed on the resultant, a first contact hole formed to selectively expose a second conductive high concentration source region by selectively etching the interlayer insulating film, and the interlayer insulating film Selectively etched to form deeper at the surface of the second conductivity type high concentration drain region It characterized by including the second contact hole.

Description

A manufacturing method of a semiconductor device having an electrostatic protection device {A METHOD FOR MANUFACTURING OF SEMICONDUCTOR DEVICE WITH ELECTOR STATIC DISCHARGE PROTECTOR}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having an electrostatic protection device, and more particularly, to an electrostatic protection device capable of reducing and eliminating input capacitance and improving electrostatic discharge (ESD) characteristics of a high-speed semiconductor device. It relates to a method of manufacturing a semiconductor device provided with.

In general, a semiconductor device is used after being fabricated in a wafer state and then cut and packaged into chips. When an ESD generated by a human body is applied during a manufacturing process or transportation in a wafer state or a package state, a high voltage of 4000 V or more is applied. Applied to destroy the device.

Such internal circuit damage is caused by joule heat caused by the charge injected through the input pad when ESD is applied and finally escapes to the other terminal through the internal circuit. That is, damage to the internal circuit as described above occurs due to junction spiking and oxide rupture caused by the Joule heat.

To solve this problem, insert an electrostatic discharge protection circuit that discharges the charge injected into the input pad directly to the power supply terminal before the injected charge is discharged through the internal circuit. prevent.

On the other hand, the ESD protection device is a field transistor that consumes most of the current when the ESD is applied between the input pad and the internal circuit, a gate ground NMOS transistor to protect the gate insulating film of the internal circuit, and excessive current flow into the NMOS transistor. It consists of a circuit with a resistance to prevent it.

The ESD protection field transistor has n ⁺ impurity diffusion regions, which are source / drain regions of the field transistor, formed on one side and the other side of the device isolation layer formed on the semiconductor substrate having p wells, and the n side of the side ^{The +} impurity diffusion region is connected to the input pin and the other n ⁺ impurity diffusion region is connected to V _SS .

Such an ESD protection device destroys the protection element itself when ESD is applied, among which the drain region of the field transistor is mainly damaged. This is because the drain region is integrated with the input pin.

Hereinafter, a semiconductor device and a manufacturing method equipped with a conventional static electricity protection device will be described with reference to the accompanying drawings.

FIG. 1A is a layout diagram illustrating an ESD transistor of a conventional static electricity protection device, and FIG. 1B is a structural cross-sectional view of the ESD transistor of the static electricity protection device along line II ′ of FIG. 1A.

As shown in FIGS. 1A and 1B, after the active region and the field region are defined in the semiconductor substrate 10 having the p wells, the device isolation layer 11 is formed in the field region of the semiconductor substrate 10.

Subsequently, a gate electrode 13a having the gate insulating layer 12 in one direction is formed in an active region on the semiconductor substrate 10 isolated by the device isolation layer 11. The source region 15 and the drain region 16 are formed in the semiconductor substrate 10 on both sides of the gate electrode 13a, respectively.

Subsequently, a first interlayer insulating layer 17 having a plurality of first contact holes 18a and 18b is formed such that the surfaces of the source region 15 and the drain region 16 are partially exposed. In this case, the first contact hole 18b formed in the drain region 16 is formed at a distance spaced apart from the gate electrode 13a by about 2 μm or more.

On the other hand, when the distance between the gate electrode 13a and the first contact 18b is short and the resistance is small, static electricity is discharged to the gate electrode 13a to destroy the gate insulating layer 12 of the transistor channel portion.

The distance between the gate electrode 13a and the first contact 18b is a main parameter of the input capacitance.

Subsequently, a first conductive layer 19 is formed in the first contact holes 18a and 18b, is connected to the first conductive layer 19, and does not overlap the gate electrode 13a. And the first metal layer pattern 20 is formed in the drain region 16. In this case, the first conductive layer 19 is tungsten.

After the second interlayer insulating film 21 having the second contact holes 22a and 22b is formed to expose the first metal layer pattern 20 by a predetermined portion, a second conductive layer is formed in the second contact holes 22a and 22b. Layer 23 is formed. In this case, the second contact hole 22b formed in the drain region 16 is formed so as not to overlap between the first contact holes 18b, and the second conductive layer 23 is tungsten.

Subsequently, a second metal layer pattern 24 is selectively formed in the source region 15 and the drain region 16 so as to be connected to the second conductive layer 23 and not overlap with the gate electrode 13a.

Here, the input capacitance occupies 80 to 90% of the area C × D of the drain region 16 in FIG. 1A.

The semiconductor device with the conventional static electricity protection device as described above has the following problems.

That is, in the conventional ESD protection device, the main parameter is a separation distance between the contact and the gate electrode formed to secure the drain region resistance, and when the resistance of the separation distance is small, the gate of the transistor channel portion is discharged to the gate electrode of the ESD transistor. The insulating film is destroyed.

Therefore, a large separation distance between the contact and the gate electrode for securing the resistance of the drain region is designed.

In addition, when a large distance between the contact and the gate electrode to secure the resistance of the drain region is designed, the area of the drain region is widened, thereby increasing the input capacitance.

Therefore, the increase in input capacitance delays the input / output of data and prevents the device from speeding up.

In addition, when using a CSP (Chip Scale Package) type with high integration and heat dissipation in high-speed operation products, it is vulnerable to a charged device model (CDM).

The present invention has been made to solve the above problems, it is possible to improve the characteristics of the ESD by reducing or eliminating the relationship between the ESD characteristics and the distance between the contact and the gate electrode formed to ensure the drain resistance of the ESD transistor. It is an object of the present invention to provide a method for manufacturing a semiconductor device having an electrostatic protection device.

1A is a layout diagram illustrating an ESD transistor of a conventional static electricity protection device.

FIG. 1B is a structural cross-sectional view of an ESD transistor of the electrostatic protection device according to line II ′ of FIG. 1A.

2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device having an electrostatic protection device according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100 semiconductor substrate 101 device isolation region

102 gate insulating film 103a gate electrode

105a: high concentration source region 106: low concentration drain region

106a: high concentration drain region 108: first insulating film for planarization

109a and 109b: first contact hole 110: first conductive layer

111a: first metal layer pattern 112: second insulating film for planarization

113a and 113b: third contact hole 114: second conductive layer

115a: second metal layer pattern

The manufacturing method of a semiconductor device with an electrostatic protection device of the present invention for achieving the above object is

The first conductivity type is p-type, and the second conductivity type is n-type.

In addition, the second conductivity type high concentration drain region is characterized in that formed deeper than the second conductivity type low concentration drain region.

Hereinafter, a method of manufacturing a semiconductor device with an electrostatic protection device according to the present invention will be described in detail with reference to the accompanying drawings.

2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device with an electrostatic protection device according to an embodiment of the present invention.

As shown in FIG. 2A, after defining the active region and the field region in the semiconductor substrate 100 having the p well, the trench is formed to selectively remove the field region to form a trench having a predetermined depth, and the semiconductor substrate including the trench. An insulating film (not shown) is formed on the entire surface of the 100.

Subsequently, an etch back process or a CMP process is performed on the entire surface of the semiconductor substrate 100 so that the insulating layer remains only inside the trench, and then the device isolation layer 101 having the STI structure is formed, and then the entire surface of the semiconductor substrate 100 is formed. The gate insulating film 102 and the polysilicon 103 for the gate electrode are sequentially deposited.

After depositing the first photoresist 104 on the polysilicon 103, the gate region is defined by patterning the first photoresist 104 using an exposure and development process.

As shown in FIG. 2B, the gate insulating layer 102 and the polysilicon 103 are selectively removed using the patterned first photoresist 104 as a mask to form a gate electrode 103a.

As shown in FIG. 2C, the patterned first photoresist 104 is removed, and low concentration source / drain impurity ions are implanted into the entire surface of the semiconductor substrate 100 using the gate electrode 103a as a mask. The low concentration source region 105 and the low concentration drain region 106 are formed in the semiconductor substrate 100 on both sides of the gate electrode 103a.

On the other hand, in order to ensure sufficient drain resistance, the ESD transistor is formed by using a Salicide Protection Mask (not shown), so that the salicide film is not formed, and the remaining transistors (not shown). In the negative), a titanium (Ti) film or a cobalt (Co) film is formed on the entire surface of the semiconductor substrate 100, and then a heat treatment process is performed on the entire surface of the semiconductor substrate 100 so that the gate electrodes and source regions of the remaining transistors except the portion where the ESD transistor is to be formed, A salicide film (not shown) is formed on the surface of the substrate on which the drain region is formed.

As shown in FIG. 2D, a first interlayer insulating layer 108 is formed on the entire surface of the semiconductor substrate 100 including the gate electrode 103a, and the low concentration source region 105 and the low concentration drain region 106 are formed at predetermined portions. The first interlayer insulating layer 108 is selectively removed to expose the first contact holes 109a and 109b.

In this case, the contact interface of the first contact hole 109b formed in the low concentration drain region 106 is formed deeper on the surface of the low concentration drain region 106 than in the conventional structure.

As shown in FIG. 2E, a high concentration source / drain impurity ions are implanted using the first interlayer insulating layer 108 as a mask to form a high concentration source region 105a on one side of the gate electrode 103a, and the gate The high concentration drain region 106a is selectively formed in the low concentration drain region 105 spaced apart from the electrode 103a by a predetermined distance.

In this case, the high concentration drain region 105a is spaced apart from the gate electrode 103a by a necessary resistance value. The high concentration drain region 106a is formed deeper than the low concentration drain region 106.

As illustrated in FIG. 2F, after the first conductive layer 110 is deposited on the first interlayer insulating layer 108 including the first contact holes 109a and 109b, the first conductive layer 110 is deposited using an etch back process and a CMP process. The first conductive layer 110 remains only inside the first contact holes 109a and 109b. In this case, tungsten is used as the first conductive layer 110.

The first metal layer 111 is deposited on the first interlayer insulating layer 108 including the first conductive layer 110, and selectively removed so as not to overlap the gate electrode 103a. ).

As shown in FIG. 2G, after the second interlayer insulating layer 112 is formed on the first metal layer pattern 111a, the second interlayer insulating layer 112 is exposed so that the first metal layer pattern 111a is partially exposed. Is selectively removed to form second contact holes 113a and 113b.

The second conductive layer 114 is formed only in the second contact holes 113a and 113b, and the gate electrode 103a is formed on the second interlayer insulating layer 112 including the second conductive layer 114. The second metal layer pattern 115a is selectively formed so as not to overlap.

Subsequently, although not shown in the drawing, a contact hole is formed to expose the gate electrode 103a for a wiring process in a later process, and then a third metal layer pattern is formed.

As described above, according to the method of manufacturing a semiconductor device with an electrostatic protection device of the present invention, a product having low input capacitance and good ESD characteristics can be designed by resolving an inverse relationship between an ESD characteristic and an input capacitance. Can be.

In addition, the present invention can be applied to high-speed operation products (DDR, Rambus DRAM SRAM, etc.) since the size of the ESD protection device can be doubled when maintaining the same input capacitance as in the prior art.

Claims (3)

Forming a gate electrode on the first conductivity type semiconductor substrate; Forming a second conductivity type low concentration source region on one side of the gate electrode and forming a second conductivity type low concentration drain region on the other side of the gate electrode; After forming the interlayer insulating film on the upper portion, and forming a first contact hole to expose the second low concentration source region and at the same time to form a second contact hole having a deeper contact interface on the surface of the second low concentration drain region Steps; A second conductive high concentration source region is formed on one side of the gate electrode by using the interlayer insulating film as a mask, and a second conductive high concentration drain region is formed on the second conductive low concentration drain region under the second contact hole. Method of manufacturing a semiconductor device with an electrostatic protection device comprising the step of. The method of claim 1, And the first conductivity type is p-type, and the second conductivity type is n-type. The method of claim 1, And the second conductivity type high concentration drain region is deeper than the second conductivity type low concentration drain region.