KR20030000195A - Method for forming plug in semiconductor device - Google Patents

Abstract

PURPOSE: A method for fabricating a plug of a semiconductor device is provided to control a leakage current, by performing a heat treatment process on amorphous silicon by a low temperature deposition process so that a grain boundary is increased. CONSTITUTION: An insulation layer is formed on a semiconductor substrate(21). The insulation layer is selectively etched to form a contact hole and a material layer for forming an amorphous plug filling the contact hole is formed. The material layer for forming the amorphous plug is annealed to increase a grain boundary. The material layer for forming the plug having the increase of grain boundary is planarized to be left only in the contact hole so that a grain boundary growth plug layer is formed.

Description

Method for forming plug in semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method of forming a plug of a semiconductor device in which crystal grains are increased by low temperature deposition and heat treatment to relatively reduce the area of grain boundaries to lower the bonding resistance.

In general, the polysilicon used for the cell plug is used in a state in which the crystalline phase is a mixture of crystalline and amorphous or all crystalline.

It is known that the grain size does not increase significantly even after the subsequent thermal history.

Hereinafter, with reference to the accompanying drawings will be described with respect to the plug formation of the prior art.

1 is a cross-sectional view of a structure for forming a plug of a semiconductor device of the prior art.

In the polysilicon plug forming process, a chemical mechanical polishing process is used. That is, the interlayer insulating film formed on the semiconductor substrate is selectively removed by a photolithography process to form contact holes, a polysilicon film for plug formation is deposited, and a chemical mechanical polishing process is performed to perform all polysilicon on the interlayer insulating film. The film is removed to form a polysilicon plug in the contact hole.

That is, as shown in FIG. 1, the word line insulating layer 3 including a sidewall spacer and a cap insulating layer for insulating the word lines 2 and the word lines, respectively, is formed on the semiconductor substrate 1. Form.

Then, the first interlayer insulating layer 4 is formed and selectively etched to form contact holes, and then a polysilicon layer is formed to fill the contact holes.

The first plug layer 6 is formed by planarizing the polysilicon layer to remain only in the contact hole by a chemical mechanical polishing (CMP) process.

Subsequently, the bit line 5 is formed to pass through the direction perpendicular to the word line 2 so as to contact one electrode of the word line 2, and the second interlayer insulating layer 8 is formed on the entire surface thereof.

The second interlayer insulating layer 8 is selectively etched to form another contact hole at least partially overlapping the first plug layer 6.

Next, a polysilicon layer is formed to fill the contact hole, and the second plug layer 7 is formed by planarization using a CMP process.

The capacitor lower electrode 9 is formed to contact the second plug layer 7.

In the plug layer forming process of the prior art which proceeds with such a process, it is necessary to consider reducing the junction resistance and suppressing the junction leakage current at the interface between the substrate and the plug.

In order to reduce the junction resistance, a method of doping phosphorous ions in the plug layer is used, but this has a limitation because it increases leakage current.

However, such a plug of the semiconductor device of the prior art has the following problems.

In the prior art, a poly plug is used to contact a capacitor electrode and one electrode of a cell transistor, but there are limitations in satisfying both a reduction in junction resistance and a suppression of leakage current.

Such a limitation affects the electrical characteristics of the device, thereby lowering the reliability of the device.

The present invention is to solve the problem of the plug and plug forming process of the prior art, to increase the grains by low temperature deposition and heat treatment to relatively reduce the area of the grain boundary (Grain Boundary) to lower the bonding resistance It is an object of the present invention to provide a method for forming a plug of a semiconductor device.

1 is a cross-sectional view of a structure for forming a plug of a semiconductor device of the prior art

2 is a cross-sectional view of a structure for forming a plug of a semiconductor device according to the present invention.

Explanation of symbols for the main parts of the drawings

21. Semiconductor substrate 22. Word line

23. Word Line Insulation Layer 24. First Interlayer Insulation Layer

25. Bit line 26. Grain growth first plug

27. Grain growth second plug 28. Second interlayer insulating layer

29. Capacitor bottom electrode

According to an aspect of the present invention, there is provided a method of forming a plug of a semiconductor device, the method including: forming an insulating layer on a semiconductor substrate; an amorphous state of selectively etching the insulating layer to form a contact hole and filling the contact hole Forming a material layer for forming a plug of the; Forming a layer of the material for forming the plug of the amorphous state to increase the crystal grains; Flattening the material layer for forming the plug forming the crystal grains so as to remain only in the contact hole grain growth plug Forming a layer.

Hereinafter, a plug forming method of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a structural cross-sectional view for forming a plug of a semiconductor device according to the present invention.

According to the present invention, a silicon layer for forming a plug is deposited at a low temperature and a thermal process is performed in an amorphous state to increase the size of crystal grains so that the bonding resistance can be efficiently reduced even when having the same impurity concentration.

This relatively suppresses the doping of phosphorus to realize the effect of preventing the increase of leakage current.

The process proceeds to form a word line insulating layer 23 including a sidewall spacer and a cap insulating layer for insulating the word lines 22 and the word lines, respectively, on the semiconductor substrate 21 as shown in FIG. 2. .

Then, the first interlayer insulating layer 24 is formed and selectively etched to form contact holes, and then a plug forming material layer, eg, a silicon layer, is formed to fill the contact holes.

Here, the silicon layer is deposited at a low temperature of 340 ° C. to 540 ° C. and then subjected to a heat treatment process in an amorphous state to form a polysilicon layer having increased grain size.

In addition, the grain growth polysilicon layer is planarized to remain only in the contact hole by a chemical mechanical polishing (CMP) process to form the grain growth first plug layer 26.

Subsequently, the bit line 25 is formed to pass through a direction perpendicular to the word line 22 so as to contact one electrode of the word line 22, and a second interlayer insulating layer 28 is formed on the entire surface thereof.

The second interlayer insulating layer 28 is selectively etched to form another contact hole at least partially overlapping the grain growth first plug layer 26.

Subsequently, a plug forming material layer, for example, a silicon layer is formed at a low temperature of 340 ° C to 540 ° C so as to fill the contact hole, and a polysilicon layer having crystal grains increased by a heat treatment process.

After the planarization is performed by the CMP process to form the grain growth second plug layer 27, the capacitor lower electrode 29 is formed to contact the grain growth second plug layer 27.

One of the factors contributing to the resistive component of the conductor material is grain boundary scattering, which means that reducing the area of the grain boundary (increasing the grain size) can reduce the resistance.

According to the present invention, the heat treatment process in the amorphous state is more effective in increasing the grain size than in the subsequent heat treatment in the presence of some crystallization or micro crystals.

Increasing the grain size means reducing the crane size, which is effective in reducing the bonding resistance.

The polysilicon plug forming process of the present invention has the following effects by forming a plug layer by increasing the grain boundary by heat-treating the silicon present in an amorphous state by low temperature deposition.

In other words, due to the reduction in grain size, it is advantageous in terms of junction resistance and does not have to increase the doping concentration of impurities, which is excellent in suppressing leakage current.

Claims (5)

Forming an insulating layer on the semiconductor substrate; Selectively etching the insulating layer to form a contact hole and to form an amorphous plug forming material layer filling the contact hole; Heat-treating the amorphous plug-forming material layer to increase crystal grains; And forming a grain growth plug layer by planarizing the plug forming material layer having the grains increased so as to remain only in the contact hole. The method of claim 1, wherein the process of the plug forming material layer is performed at a low temperature of 340 ° C. to 540 ° C. to deposit the plug forming material layer in an amorphous state. The method for forming a plug of a semiconductor device according to claim 1, wherein the plug forming material layer is made of silicon. The method for forming a plug of a semiconductor device according to claim 1, wherein the planarization process for forming the grain growth plug layer is performed in a CMP process. The method of claim 1, wherein the grain growth plug layer electrically connects the lower electrode of the capacitor and the conductive region of the substrate to each other.