KR20030000575A - Manufacturing method for semiconductor device - Google Patents
Manufacturing method for semiconductor device Download PDFInfo
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- KR20030000575A KR20030000575A KR1020010036608A KR20010036608A KR20030000575A KR 20030000575 A KR20030000575 A KR 20030000575A KR 1020010036608 A KR1020010036608 A KR 1020010036608A KR 20010036608 A KR20010036608 A KR 20010036608A KR 20030000575 A KR20030000575 A KR 20030000575A
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- H10D64/01344—
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- H10D64/0134—
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
- H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
- H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
- H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 반도체소자의 제조방법에 관한 것으로, 게이트절연막의 표면을 DPN(decoupled plasma nitridation)방법으로 질화처리하여 게이트절연막과 반도체기판 간에 계면 특성을 유지하면서 게이트전극에 함유된 도펀트가 게이트절연막을 통하여 반도체기판으로 침투하는 것을 방지하고, 그로 인하여 소자의 동작 특성 및 신뢰성을 향상시키는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, wherein a surface of a gate insulating film is nitrided by a decoupled plasma nitridation (DPN) method to maintain dopants contained in the gate electrode through the gate insulating film while maintaining interfacial properties between the gate insulating film and the semiconductor substrate. It is a technique of preventing penetration into a semiconductor substrate, thereby improving the operating characteristics and reliability of the device.
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 보다 상세하게 게이트절연막의 표면을 DPN(decoupled plasma nitridation)방법으로 질화처리하여 게이트전극에 함유된 도펀트(dopant)가 게이트절연막을 통하여 반도체기판으로 침투하는 것을 방지하는 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. More particularly, the surface of a gate insulating film is nitrided by a decoupled plasma nitridation (DPN) method so that a dopant contained in the gate electrode penetrates into the semiconductor substrate through the gate insulating film. The present invention relates to a method for manufacturing a semiconductor device.
일반적으로 MOSFET 의 게이트 절연막은 반도체기판과 게이트 전극을 중계하는 역할로서 반도체기판 및 상기 게이트 전극의 사이에 위치한다. 그리고, 상기 게이트 절연막은 게이트 전극으로 주로 사용되는 다결정실리콘층과의 계면 상태가 가장 양호한 열산화막(SiO2)을 주로 사용한다.In general, the gate insulating film of the MOSFET serves as a relay between the semiconductor substrate and the gate electrode and is located between the semiconductor substrate and the gate electrode. In addition, the gate insulating film mainly uses a thermal oxide film (SiO 2 ) having the best interface state with the polysilicon layer mainly used as the gate electrode.
PMOS 소자의 경우 p+ 다결정실리콘 게이트를 적용할 경우 활성화(activation)를 위한 열처리과정에서 p+ 다결정실리콘이 포함하고 있는 보론(boron)과 같은 도펀트(dopant)가 하부 게이트절연막인 SiO2막을 뚫고 반도체기판까지 침투를 하기 때문에 플랫 밴드 전압(flat band voltage, VFB)과 문턱전압(threshold voltage, Vt) 등에 큰 영향을 미치게 된다. 이를 방지하기 위하여 SiO2막 상부를 질화막으로 만들어 보론과 같은 3족 도펀트와 질소가 결합을 이루면서 3족 도펀트가 반도체기판으로 침투되는 것을 억제한다. 게이트절연막의 질화처리 시 MOS 소자의 동작 특성에 영향을 주지 않기 위해서는 SiO2막의 표면만 질화처리하는 것이 중요하다. 특히, 서브 0.1 ㎛ MOS 소자의 경우에는 SiO2막의 두께가 35Å 이하로 매우 작기 때문에 SiO2막의 상부만 질화시키는 것이 매우 어려운 문제점이 있다.In the case of the PMOS device, when a p + polysilicon gate is applied, a dopant such as boron containing p + polysilicon is pierced through a SiO 2 film, which is a lower gate insulating film, to the semiconductor substrate during a heat treatment process for activation. Because it penetrates, it has a great influence on the flat band voltage (V FB ) and threshold voltage (V t ). In order to prevent this, the upper part of the SiO 2 film is formed as a nitride film to prevent the Group 3 dopant from penetrating into the semiconductor substrate while forming nitrogen and a Group 3 dopant such as boron. In order to nitrate the gate insulating film, it is important to nitrate only the surface of the SiO 2 film in order not to affect the operation characteristics of the MOS device. In particular, in the case of a sub-0.1 μm MOS device, since the thickness of the SiO 2 film is very small, such as 35 kPa or less, it is very difficult to nitride only the upper portion of the SiO 2 film.
참고로, 최근에 이를 위하여 고안된 질화방법은 RPN(remote plasma nitridation), DPN(decoupled plasma nitridation) 등의 방법이 있다.For reference, recent nitriding methods designed for this include methods such as remote plasma nitridation (RPN) and decoupled plasma nitridation (DPN).
도 1a 및 도 1b 는 게이트절연막에 DPN(decoupled plasma nitridation) 처리했을 때 질소(nitrogen) 분포를 SIMS(secondary ion mass spectroscopy) 분석한 그래프로서, 게이트절연막의 두께가 30Å과 15Å인 경우 질소의 양을 달리하여 측정한 값을 나타낸다. 이때, 상기 DPN방법은 SiO2막의 가장 표면 쪽만 질화시키는 방법이지만, SiO2막이 20Å 이하인 경우 SiO2막과 반도체기판 사이에도 질소(N)가 확산되는 것으로 확인되었다.1A and 1B are graphs of secondary ion mass spectroscopy (SIMS) analysis of nitrogen distribution when DPN (decoupled plasma nitridation) is applied to a gate insulating film. The measured value is shown differently. In this case, the DPN method is a method of nitriding only the outermost surface of the SiO 2 film, but when the SiO 2 film is 20 kPa or less, it was confirmed that nitrogen (N) is also diffused between the SiO 2 film and the semiconductor substrate.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 반도체기판 상부에 제1게이트절연막을 형성하고, 상기 제1게이트절연막의 표면을 DPN방법으로 질화처리한 다음, 상기 질화처리된 제1게이트절연막 하부에 제2게이트절연막을 형성하여 게이트절연막과 반도체기판 간의 계면 특성을 유지하면서 게이트전극에 함유되어 있는 도펀트가 반도체기판으로 침투하는 것을 방지하여 소자의 동작 특성 및 신뢰성을 향상시키는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.According to the present invention, in order to solve the above-mentioned problems of the prior art, a first gate insulating film is formed on a semiconductor substrate, the surface of the first gate insulating film is nitrided by a DPN method, and then the nitrided first gate insulating film is processed. A method of fabricating a semiconductor device, in which a second gate insulating film is formed on the lower portion to prevent the dopant contained in the gate electrode from penetrating into the semiconductor substrate while maintaining the interface characteristics between the gate insulating film and the semiconductor substrate. The purpose is to provide.
도 1a 은30Å 두께의 게이트절연막에 DPN(decoupled plasma nitridation) 처리했을 때 질소(nitrogen) 분포를 SIMS(secondary ion mass spectroscopy) 분석한 그래프.FIG. 1A is a graph illustrating secondary ion mass spectroscopy (SIMS) analysis of nitrogen distribution when DPN (decoupled plasma nitridation) treatment is performed on a gate insulating film having a thickness of 30 kHz.
도 1b 는15Å 두께의 게이트절연막에 DPN(decoupled plasma nitridation) 처리했을 때 질소(nitrogen) 분포를 SIMS(secondary ion mass spectroscopy) 분석한 그래프.FIG. 1B is a graph illustrating secondary ion mass spectroscopy (SIMS) analysis of nitrogen distribution when DPN (decoupled plasma nitridation) is applied to a gate insulating film having a thickness of 15 kHz.
도 2a 내지 도 2d 는 본 발명에 따른 반도체소자의 제조방법에 의한 공정 단면도.2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
21 : 반도체기판 23 : 소자분리절연막21 semiconductor substrate 23 device isolation insulating film
25 : 제1게이트절연막 27 : 질화처리된 제1게이트절연막25: first gate insulating film 27: nitrided first gate insulating film
29 : 제2게이트절연막 31 : 게이트전극29: second gate insulating film 31: gate electrode
이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 제조방법은,Method for manufacturing a semiconductor device according to the present invention for achieving the above object,
반도체기판에 활성영역을 정의하는 소자분리절연막을 형성하는 공정과,Forming a device isolation insulating film defining an active region on the semiconductor substrate;
상기 반도체기판 상부에 제1게이트절연막을 형성하는 공정과,Forming a first gate insulating film on the semiconductor substrate;
상기 제1게이트절연막을 질화처리하는 공정과,Nitriding the first gate insulating film;
상기 구조를 제1열처리하는 공정과,First heat treating the structure;
상기 질화처리된 제1게이트절연막 하부에 제2게이트절연막을 형성하는 공정과,Forming a second gate insulating film under the nitrided first gate insulating film;
전체표면 상부에 게이트전극용 도전층을 형성하는 공정과,Forming a conductive layer for the gate electrode on the entire surface;
게이트전극 마스크를 식각마스크로 상기 게이트전극용 도전층, 질화처리된 제1게이트절연막 및 제2게이트절연막을 식각하는 공정과,Etching the conductive layer for the gate electrode, the nitrided first gate insulating film and the second gate insulating film using a gate electrode mask as an etching mask;
상기 구조를 제2열처리하는 공정을 포함하는 것을 특징으로 한다.And a second heat treatment of the structure.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 2a 내지 도 2d 는 본 발명에 따른 반도체소자의 제조방법에 따른 공정 단면도이다.2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
먼저, 반도체기판(21)에 활성영역을 정의하는 소자분리절연막(23)을 형성한다.First, an element isolation insulating film 23 defining an active region is formed on the semiconductor substrate 21.
다음, 상기 반도체기판(21) 표면에 제1게이트절연막(25)을 형성한다. 이때, 상기 제1게이트절연막(25)은 ISSG(in-situ steam generation)방법 또는 건식 산화(dry oxidation)공정에 의한 급속열처리(rapid thermal annealing)방법으로 형성되고, SiO2막을 사용하여 3 ∼ 20Å 두께로 형성된다. 한편, 상기 제1게이트절연막(25)은 Al2O3막, Ta2O5막, Y2O3막, CeO2막, ZrO2막, HfO2막, 그들의 적층구조 또는 그 실리케이트막으로 형성될 수도 있다. (도 2a 참조)Next, a first gate insulating film 25 is formed on the surface of the semiconductor substrate 21. At this time, the first gate insulating film 25 is formed by an in-situ steam generation (ISSG) method or a rapid thermal annealing method by a dry oxidation process, using a SiO 2 film to 3 ~ 20Å It is formed in thickness. The first gate insulating film 25 may be formed of an Al 2 O 3 film, a Ta 2 O 5 film, a Y 2 O 3 film, a CeO 2 film, a ZrO 2 film, an HfO 2 film, a laminated structure thereof, or a silicate film thereof. May be (See Figure 2A)
그 다음, 상기 제1게이트절연막(25)의 표면을 질화처리한다. 이때, 상기 질화 처리 공정으로 형성된 질화처리된 제1게이트절연막(27)은 후속공정으로 형성되는 게이트전극으로부터 도펀트가 반도체기판(21)으로 침투하는 것을 방지한다. 상기 질화 처리 공정은 DPN(decoupled plasma nitridation)방법으로 실시되고, -50 ∼ 200℃의 기판온도와 1 ∼ 20mTorr의 압력 하에서 1 ∼ 500W의 RF(radio frequency) 플라즈마 파워를 인가하고 N2, NH3, N2O 또는 NO 가스를 사용하여 1 ∼ 30초 동안 실시된다.Next, the surface of the first gate insulating film 25 is nitrided. In this case, the nitrided first gate insulating layer 27 formed in the nitriding process prevents the dopant from penetrating into the semiconductor substrate 21 from the gate electrode formed in a subsequent process. The nitriding process is carried out by a decoupled plasma nitridation (DPN) method, applying a radio frequency (RF) plasma power of 1 to 500 W under a substrate temperature of -50 to 200 ° C. and a pressure of 1 to 20 mTorr, and N 2 , NH 3. , Using N 2 O or NO gas for 1 to 30 seconds.
다음, 상기 구조를 N2, Ar 또는 진공 분위기에서 100 ∼ 800℃의 온도로 1 ∼ 30분간 제1열처리한다. (도 2b 참조)Next, the structure is first heat treated for 1 to 30 minutes at a temperature of 100 to 800 ° C. in N 2 , Ar or a vacuum atmosphere. (See Figure 2b)
그 다음, 상기 질화처리된 제1게이트절연막(27) 하부에 제2게이트절연막(29)을 형성한다. 이때, 상기 제2게이트절연막(29)은 400 ∼ 1100℃의 온도에서 O2와 H2의 유량을 각각 0.1 ∼10slm으로 하는 ISSG-RTA(in-situ steam generation-rapid thermal annealing)방법을 5 ∼ 300초간 실시하여 SiO2막을 5 ∼ 20Å 두께로 형성한다. (도 2c 참조)Next, a second gate insulating film 29 is formed under the nitrided first gate insulating film 27. At this time, the second gate insulating film 29 has an in-situ steam generation-rapid thermal annealing (ISSG-RTA) method in which the flow rates of O 2 and H 2 are 0.1 to 10 slm at temperatures of 400 to 1100 ° C., respectively. embodiment 300 seconds to form a SiO 2 film 5 ~ 20Å thick. (See Figure 2c)
다음, 전체표면 상부에 게이트전극용 도전층을 형성한다. 상기 게이트용 도전층은 TiN, Ta, TaN, HfN, ZrN, TiAlxNy, TaSixNy또는 TiSixNy등의 금속층 또는 n+ 다결정실리콘층 또는 p+ 다결정실리콘층으로 형성한다.Next, a conductive layer for the gate electrode is formed on the entire surface. The gate conductive layer is formed of a metal layer such as TiN, Ta, TaN, HfN, ZrN, TiAl x N y , TaSi x N y or TiSi x N y , or an n + polysilicon layer or a p + polysilicon layer.
그 다음, 게이트전극 마스크를 식각마스크로 사용하여 상기 게이트전극용 도전층, 질화처리된 제1게이트절연막(27) 및 제2게이트절연막(29)을 식각하여 게이트전극(31)과 제1게이트절연막(27)패턴 및 제2게이트절연막(29)패턴의 적층구조를 형성한다.Next, using the gate electrode mask as an etching mask, the gate electrode conductive layer, the nitrided first gate insulating layer 27 and the second gate insulating layer 29 are etched to etch the gate electrode 31 and the first gate insulating layer. (27) A lamination structure of the pattern and the second gate insulating film 29 pattern is formed.
그 후, 상기 구조를 N2, Ar 또는 진공분위기에서 제2열처리한다. 이때, 상기 제2열처리공정은 5 ∼ 10slm의 N2또는 Ar를 주입하여 실시한다. 또한, 상기 제2열처리공정은 퍼니스에서 500 ∼ 900℃로 10분 ∼ 1시간 동안 실시하거나, 급속열처리방법을 이용하여 500 ∼ 1100℃로 10초 ∼ 10분 동안 실시한다. (도 2d 참조)The structure is then subjected to a second heat treatment in N 2 , Ar or vacuum atmosphere. At this time, the second heat treatment step is carried out by injecting 5 to 10 slm N 2 or Ar. In addition, the second heat treatment step is performed for 10 minutes to 1 hour at 500 ~ 900 ℃ in the furnace, or 10 seconds to 10 minutes at 500 ~ 1100 ℃ using a rapid heat treatment method. (See FIG. 2D)
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 제조방법은, 게이트절연막의 표면을 DPN방법으로 질화처리하여 게이트절연막과 반도체기판 간에 계면 특성을 유지하면서 게이트전극에 함유된 도펀트가 게이트절연막을 통하여 반도체기판으로 침투하는 것을 방지하고, 그로 인하여 소자의 동작 특성 및 신뢰성을 향상시키는 이점이 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, the surface of the gate insulating film is nitrided by the DPN method to maintain the interface characteristics between the gate insulating film and the semiconductor substrate while the dopant contained in the gate electrode is formed through the gate insulating film. There is an advantage of preventing penetration into the substrate, thereby improving the operating characteristics and reliability of the device.
Claims (15)
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| KR1020010036608A KR20030000575A (en) | 2001-06-26 | 2001-06-26 | Manufacturing method for semiconductor device |
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| KR1020010036608A KR20030000575A (en) | 2001-06-26 | 2001-06-26 | Manufacturing method for semiconductor device |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030044394A (en) * | 2001-11-29 | 2003-06-09 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device with dual gate dielectric layer |
| KR100762238B1 (en) * | 2006-03-21 | 2007-10-01 | 주식회사 하이닉스반도체 | Transistor of semiconductor device and method of forming same |
| US7601404B2 (en) * | 2005-06-09 | 2009-10-13 | United Microelectronics Corp. | Method for switching decoupled plasma nitridation processes of different doses |
| KR100936577B1 (en) * | 2007-12-03 | 2010-01-13 | 주식회사 동부하이텍 | Semiconductor device and manufacturing method |
| US8673747B2 (en) | 2010-06-09 | 2014-03-18 | Samsung Electronics Co., Ltd. | Method of fabricating semiconductor device |
-
2001
- 2001-06-26 KR KR1020010036608A patent/KR20030000575A/en not_active Withdrawn
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030044394A (en) * | 2001-11-29 | 2003-06-09 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device with dual gate dielectric layer |
| US7601404B2 (en) * | 2005-06-09 | 2009-10-13 | United Microelectronics Corp. | Method for switching decoupled plasma nitridation processes of different doses |
| KR100762238B1 (en) * | 2006-03-21 | 2007-10-01 | 주식회사 하이닉스반도체 | Transistor of semiconductor device and method of forming same |
| KR100936577B1 (en) * | 2007-12-03 | 2010-01-13 | 주식회사 동부하이텍 | Semiconductor device and manufacturing method |
| US8673747B2 (en) | 2010-06-09 | 2014-03-18 | Samsung Electronics Co., Ltd. | Method of fabricating semiconductor device |
| US9023718B2 (en) | 2010-06-09 | 2015-05-05 | Samsung Electronics Co., Ltd. | Method of fabricating semiconductor device |
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