KR200283421Y1 - Stacked chip ceramic package device and stacked package device stacking the same - Google Patents

Abstract

The present invention provides a chip stacked ceramic package device in which a plurality of chips are stacked in one ceramic package without increasing the thickness of the substrate. The chip stacked ceramic package device includes a substrate, upper and lower semiconductor chips, bonding wires, and a package body. The substrate includes a terminal surface having a plurality of terminals having input / output functions on both upper and lower sides, a bonding surface on which bonding pads for wire bonding are formed, and a chip mounting surface on which a chip is attached, and including a terminal surface, a bonding surface, and a chip. The mounting surface is formed stepwise so that the height gradually decreases in this order. In addition, the substrate may include a bonding cavity and a space for accommodating the semiconductor chip, including a first cavity and a chip mounting surface to provide a space for electrical connection between the semiconductor chip and the substrate. Contains cavities. The upper and lower semiconductor chips are attached to the mounting surface of the substrate through adhesive layers, and the electrode pads of the upper and lower semiconductor chips are electrically connected to the bonding pads of the bonding surfaces of the substrate through bonding wires. The package body is formed by filling the first and second cavities of the substrate with a predetermined filler.

Description

Stacked chip ceramic package device and stacked package device {stacked chip ceramic package device and stacked package device stacking the same}

The present invention relates to a chip stacked packaging technology, and more particularly, to a chip stacked ceramic package device in which a plurality of chips are stacked in one package, and a package stacked device in which the package devices are stacked.

As the degree of integration of semiconductor devices and the demand for high performance increase, the size of the semiconductor chip itself increases, and thus the necessity of increasing the mounting density of the semiconductor devices has arisen. In particular, in the case of a ceramic package, high reliability is achieved despite the high price due to the advantage of preventing gas or liquid from entering the package when the chip is mounted, and being able to withstand even higher temperatures than ordinary plastic packages. It is widely used for military equipment, aerospace, high-end server systems, etc. that are required. Therefore, in such a highly reliable and high performance ceramic package, further improvement in mounting density is required. Multilayer ceramic package devices can be an alternative to meet these needs. Multilayer package devices have the advantage that multiple chips with different functions can be implemented in one package.

However, in general, chip stacked package devices are inevitably thicker than package devices in which one chip is mounted, and a stacking technology capable of meeting the demand for ultra-thin packages and maintaining high reliability of ceramic packages is still In the field of ceramic packages, more technical development and advancement is required than plastic packages.

Accordingly, an object of the present invention is to provide a chip stacked ceramic package device in which a plurality of chips are stacked in one ceramic package without increasing the thickness of the substrate.

Another object of the present invention is to provide a package stacked device in which the above-described chip stacked ceramic package is laminated.

1 is a plan view of a substrate used in the chip stacked ceramic package device according to the first embodiment of the present invention,

2A and 2B are cross-sectional views of a substrate used in a chip stacked ceramic package device according to a first embodiment of the present invention;

3 is a cross-sectional view of a chip stacked ceramic package device having an upper side according to a first embodiment of the present invention;

4 is a cross-sectional view of a chip stacked ceramic package device in which both upper and lower portions according to the first embodiment of the present invention are completed;

5 is a plan view of a chip multilayer ceramic package according to a first embodiment of the present invention;

6 is a cross-sectional view of a chip stacked ceramic package device according to a second embodiment of the present invention.

7 is a cross-sectional view of a package stacked device in which package devices according to the present invention are stacked.

<Brief description of the main parts of the drawing>

1 ... Board 1a ... Terminal Face

1b ... bonding surface 1c ... mounting surface

1d ... sealing surface 1a ', 1b' ... metal pattern

2a, 2b ... upper and lower semiconductor chip 3 ... package body

4 ... adhesive 5a, 5b ... electrode pad

6 ... bonding wires 7a, 7b ... bonding pads

8 ... metal cap 9 ... via hole

10, 20 ... chip stacked ceramic package elements

Chip stack type ceramic package device according to an embodiment of the present invention, the terminal surface formed with a plurality of terminals for input / output functions on both sides of the upper and lower sides, a bonding surface formed with a bonding pad for wire bonding and a chip seal to which the chip is attached A substrate having a scene, wherein the terminal surface, the bonding surface, and the chip mounting surface are formed stepwise so that the height gradually decreases in this order, and a space for electrical connection between the semiconductor chip and the substrate including the bonding surface is formed. A substrate having a first cavity to provide a second cavity, the second cavity providing a space to accommodate a semiconductor chip, including the chip mounting surface; Upper and lower semiconductor chips respectively attached to upper and lower mounting surfaces of the substrate through an adhesive layer; Bonding wires electrically connecting the electrode pads of the upper and lower semiconductor chips to the bonding pads of the bonding surface of the substrate; And a package body formed by filling the first and second cavities with a predetermined filler, wherein a distance from the chip mounting surface to an upper surface of the package body and a distance from the chip mounting surface to the terminal surface are substantially It characterized in that it comprises the same package body.

Chip stack type ceramic package device according to another embodiment of the present invention, the terminal surface formed with a plurality of terminals for input / output functions on both sides of the upper and lower sides, the sealing surface formed with the element for sealing the package, the bonding pad for wire bonding A substrate having a bonding surface on which a chip is formed and a chip mounting surface to which a chip is attached, wherein the terminal surface, the sealing surface, the bonding surface, and the chip mounting surface are formed in a stepped manner such that the height is gradually lowered in this order; Upper and lower semiconductor chips respectively attached to upper and lower mounting surfaces of the substrate through an adhesive layer; Bonding wires electrically connecting the electrode pads of the upper and lower semiconductor chips to the bonding pads of the bonding surface of the substrate; And a metal cap formed on the sealing surface, wherein a distance from the chip mounting surface to an upper surface of the metal cap and a distance from the chip mounting surface to the terminal surface include substantially the same metal caps. It features.

The package stacked device according to another embodiment of the present invention is characterized by being configured by stacking a plurality of chip stacked ceramic package devices of the above-described embodiments.

Example

Hereinafter, with reference to the accompanying drawings, it will be described in more detail the chip stacked ceramic package device and the package stacked device stacked thereon according to the present invention. The elements shown in the drawings are for illustrative purposes and do not necessarily reflect the size of actual elements. Like reference numerals in the drawings denote the same or corresponding components.

1 is a plan view of a substrate used in a chip stacked ceramic package device according to a first embodiment of the present invention, and FIGS. 2A and 2B are cross-sectional views of a substrate used in a chip stacked ceramic package device according to a first embodiment; 3 is a cross-sectional view of a chip stacked ceramic package device having an upper side according to a first embodiment, and FIG. 4 is a cross-sectional view of a chip stacked ceramic package device having both upper and lower parts according to a first embodiment implemented.

The chip stacked package device 10 includes a substrate 1, a plurality of semiconductor chips 2a and 2b, and a package body 3.

As shown in FIG. 1, the substrate 1 is a multilayer ceramic substrate, and wiring patterns (not shown) are formed therein. The substrate 1 includes a region 1a in which a plurality of terminals serving as input / output functions are formed, and a plurality of bonding pads 7a and 7b for electrical connection with electrode pads 5a and 5b of the chip. The formed region 1b and the region 1c on which the chips 2a and 2b are mounted are formed. That is, as shown in FIGS. 2A and 2B, the substrate 1 includes a terminal surface 1a on which terminals are formed, a bonding surface 1b for wire bonding between the chip and the substrate, and a chip mounting surface 1c. The terminal surface 1a, the bonding surface 1b, and the mounting surface 1c are formed in a stepwise manner in which the height gradually decreases in this order. In addition, the substrate includes a first cavity including a bonding surface 1b and a second cavity including a chip mounting surface 1c below it. The second cavity provides a space on the chip mounting surface 1c to accommodate the semiconductor chip, and the first cavity can form a loop of metal wire for electrical connection between the semiconductor chip and the substrate bonding surface 1b. Provide space. The first cavity and the second cavity provide space for forming a package body of a unique structure according to the present invention. The lower part of the board | substrate 1 also has the same shape as the upper part, The terminal surface 1a, the bonding surface 1b, and the mounting surface 1c are formed, and the 1st cavity and 2nd cavity of the same structure as the upper part Include.

Electrical connection between the chip stacked package element and the external device will be described with reference to FIGS. 2A and 2B.

First, as shown in FIG. 2A, metal patterns 1a 'and 1b' are formed on the bonding surface 1b and the terminal surface 1a of the substrate, respectively. The metal pattern is made of copper, for example. The metal pattern 1b 'of the bonding surface and the metal pattern 1a' of the terminal surface are electrically connected by metal plated via holes 9. The metal pattern 1a 'of the terminal surface 1a includes an external terminal electrically connected to an external element (eg, a main board or another chip stacked package element of a computer system). The semiconductor chip of the package device is electrically connected to the outside through a bonding wire, a metal pattern 1b ', a via hole 9, and a terminal surface metal pattern 1a'.

According to another embodiment of the present invention, the terminal surface metal pattern 1a 'and the bonding surface metal pattern 1b' are electrically connected to each other by a plated metal in the hemisphere hole 90 formed at the end of the substrate.

The present invention may use any connection method of FIG. 2A or 2B for electrical connection between a package element and an external device.

In the upper semiconductor chip 2a, an on-chip circuit is formed on an active surface, and a center pad type IC element in which a plurality of electrode pads 5a are formed in the center of the active surface. to be. The lower semiconductor chip 2b has the same on-chip circuit and the arrangement, shape, and size of the electrode pad 5b as the upper semiconductor chip 2a. It is also possible to stack the upper and lower chips 2a and 2b having different functions.

In the present invention, the upper semiconductor chip is first attached only to the mounting surface on the upper surface of the substrate, and after the bonding step, the package body forming step, or the sealing step, the electrical characteristics of the upper semiconductor chip are examined to determine the upper structure. It is preferable to perform the same process as that applied to the upper semiconductor chip only to the mounting surface under the substrate only when the inspection conditions are satisfied. As a result, the defective chips can be sorted out faster than in the case of chip inspection after mounting both the upper and lower semiconductor chips, thereby improving productivity and reducing costs.

As shown in FIG. 3, the upper semiconductor chip 2a is attached only to the mounting surface 1c on the substrate by the adhesive layer 4. The adhesive layer 4 is, for example, a silver-epoxy adhesive or a film-type adhesive tape made of an epoxy resin.

The electrode pad 5a of the upper semiconductor chip 2a is electrically connected to the bonding pad 7a of the bonding surface 2b of the substrate via the bonding wire 6. As shown in FIG. 3, the height difference between the mounting surface and the bonding surface of the substrate, that is, the height of the bonding surface is equal to the thickness of the chip.

By filling the first cavity and the second cavity of the substrate with a predetermined filler, the package body 3 is formed, thereby protecting the chip, the electrode pad and the bonding wire from the external environment. Since the top surface of the package body is defined by the first cavity, the package body is formed not to exceed the overall height of the substrate. Therefore, the distance from the chip mounting surface to the upper surface of the package body is substantially the same as the distance from the chip mounting surface to the terminal surface. The package body 3 is formed by injecting a polyimide-based potting material into the first cavity and the second cavity by a dispenser or the like. However, if the package body is formed of the potting material instead of the metal seal, voids or the like may occur and the reliability of the package element may deteriorate. In the present invention, when the potting material in a glue state is left in a vacuum state, the voids are exposed and exploded, thereby solving the problem of deterioration in reliability by utilizing the fact that the voids are removed. In forming the package body by the potting process, a void removal step is performed prior to curing the potting material.

When the assembly and inspection process for the upper structure of the substrate is finished, as shown in FIG. 4, the lower semiconductor chip 2b is attached to the mounting surface 1c of the lower substrate through the adhesive layer 4 in the same process as the upper semiconductor chip 2a. Attach). Next, the electrode pad 5b of the lower semiconductor chip 2b and the bonding pad 7b of the bonding surface 1b are wire bonded to form a package body 3. Thereby, the chip laminated ceramic package element 10 is completed.

5 is a plan view of a chip multilayer ceramic package according to a first embodiment of the present invention.

5 is a view illustrating an electrical connection structure of the stacked package elements when a plurality of chip stacked ceramic packages are stacked.

In a package element in which two or more semiconductor chips are stacked, the operation of individual chips must be selected for the operation of the device. Selecting the operation of each chip includes a method of operating only one chip among a plurality of stacked semiconductor chips and a method of operating both stacked chips. When only one chip is operated, data input / output (DQ) of each chip is used. ) Can be connected to the data input / output terminals of the package in common, thereby reducing the number of pins of the package. Meanwhile, when all the stacked chips are operated, the DQs of the individual chips must be connected to separate package terminals, which can increase the utilization of the stacked chips. In order to select the operation of the chip in the chip stack package device, the DQ and I / O are connected in common and the CS signals are separated, the CS and CKE are separated, and the DQ and I / O are connected separately and the CS is connected. There is a way to not provide a signal.

In the present invention, all three methods may be implemented by using one substrate pattern and applying a bonding option. For example, as shown in FIG. 5, the DQ # of the upper semiconductor chip # and the lower semiconductor chip # are connected to the package I / O terminal # in common, and the upper and lower semiconductor chips # Connect CS signal pad (#) to CKE terminal (#) of package and metal wire (#), CKE signal pad (#) of semiconductor chip (#), CLK terminal (#) and metal wire (#) of package Next, the operation of the upper semiconductor chip and the lower semiconductor chip may be selectively controlled by a combination of the CLK signal and the CKE signal. The CS signal separation method and the DQ and I / O separate connection methods among the chip selection methods described above are easily understood by those skilled in the art, and thus detailed descriptions thereof will be omitted.

6 is a cross-sectional view of a chip stacked ceramic package device 20 according to a second embodiment of the present invention.

As shown in FIG. 6, in the chip stacked ceramic package element 20 of the second embodiment, the thickness is thinner than the mounting surface 1c of the substrate of the package element 10 of the first embodiment, and the thickness of the mounting surface is thinner. The height of the terminal surface 1a is increased as much as possible, and a substrate is formed to form one more stepped portion on the terminal surface having a thick thickness. This step is a sealing surface 1d on which a member for sealing the inside of the package, for example, a metal cap (metal cap or metal lid), is formed. With this substrate configuration, it is preferable that the bonding surface and the chip are not formed at the same height as in the first embodiment, but the chip is formed lower than the bonding surface to secure the space necessary for the loop for the bonding wire. Also, in the second embodiment, unlike the first embodiment in which the potting material is used to form the package body, the sealing surface 1d is formed by the sealing surface 1d formed in the space secured by the thickened thickness of the terminal surface. The package is sealed by forming a metal cap in 1d). The other configuration of the chip stacked ceramic package device 20 of the second embodiment is the same as the package device 10 of the first embodiment.

In the present invention, a plurality of chip stacked ceramic package devices 100A and 100B according to the first and second embodiments described above are stacked to form the package stacked device 100 as illustrated in FIG. 7. The package elements are completed by attaching the package elements through an adhesive such as silver-epoxy and soldering the terminals of the package substrate using a lead-free solder. In the present invention, since a solder containing no lead is used, it does not adversely affect the environment. The electrical connection between the stacked package elements is made by external connection terminals formed on the terminal surface 1a of the individual package elements. As described above, the terminal face 1a is not lower than the upper surface of the package body 3 or the metal cap 8, so that the terminal face 1a can be easily stacked without any consideration for electrical connection between the individual stacked package elements. have.

As described above, according to the present invention, since the substrate is formed with the stepped surface as the terminal surface, the bonding surface, and the chip mounting surface, and the chip is mounted in the stepped portion, a plurality of substrates in one ceramic package can be increased without increasing the thickness of the substrate. A chip stacked ceramic package device in which chips are stacked may be implemented.

In addition, in the present invention, since the chip has the same height or lower than the bonding surface of the substrate, even if the electrode pad is disposed at the center of the chip, sagging due to the loop of the metal wire does not occur during wire bonding.

A plurality of chip stacked ceramic packages according to the present invention can be easily stacked to implement a package stacked device.

Claims (8)

A substrate having a terminal surface having a plurality of terminals having input / output functions on both sides of upper and lower sides, a bonding surface on which a bonding pad for wire bonding is formed, and a chip mounting surface on which a chip is attached, wherein the terminal surface, the bonding surface, and the chip are provided. The mounting surface is formed in a stepped manner such that the height gradually decreases in this order, and includes a first cavity, which provides a space for electrical connection between the semiconductor chip and the substrate, including the bonding surface, and the chip mounting surface. A substrate having a second cavity, the substrate having a space to accommodate a semiconductor chip; Upper and lower semiconductor chips respectively attached to upper and lower mounting surfaces of the substrate through an adhesive layer; Bonding wires electrically connecting the electrode pads of the upper and lower semiconductor chips to the bonding pads of the bonding surface of the substrate; And A package body formed by filling the first and second cavities with a predetermined filler, wherein a distance from the chip mounting surface to an upper surface of the package body and a distance from the chip mounting surface to the terminal surface are substantially the same. Chip stacked ceramic package device comprising a package body. It has a terminal surface with a plurality of terminals for input / output functions on both sides of the upper and lower parts, a sealing surface on which a device for sealing a package is formed, a bonding surface on which bonding pads are formed for wire bonding, and a chip mounting surface on which chips are attached. A substrate comprising: a substrate in which the terminal surface, the sealing surface, the bonding surface, and the chip mounting surface are formed in a stepped manner such that the height is gradually decreased in this order; Upper and lower semiconductor chips respectively attached to upper and lower mounting surfaces of the substrate through an adhesive layer; Bonding wires electrically connecting the electrode pads of the upper and lower semiconductor chips to the bonding pads of the bonding surface of the substrate; And A metal cap formed on the sealing surface, wherein a distance from the chip mounting surface to the top surface of the metal cap and a distance from the chip mounting surface to the terminal surface include substantially the same metal cap. A chip laminated ceramic package element. The chip stacked ceramic package device of claim 1, wherein the upper and lower semiconductor chips are formed at the same height as the bonding surface. The chip stack ceramic package device of claim 1, wherein the package body is formed using a polyimide-based potting material. The chip stack ceramic package device of claim 2, wherein the upper and lower semiconductor chips are formed at a height lower than the bonding surface. The chip stacked ceramic package device of claim 1 or 2, wherein the substrate is a multilayer ceramic substrate. The package laminated element comprised by laminating | stacking the several chip laminated ceramic package element of Claim 1 or 2. 8. The package stack device of claim 7, wherein the terminals of the substrate are soldered using a lead-free solder.