KR20020043647A - Low profile, high density memory system - Google Patents

Abstract

The present invention provides a low profile, high density electronic package 50 for a high speed, high performance semiconductor such as the memory elements 28. To maintain electrical high performance, the present invention includes a plurality of modules having high speed impedance controllable transmission line buses, short interconnections between modules and optionally driveline terminators installed in one of the modules.

Preferred applications include microprocessor data buses and memory buses such as RAMBUS and DDR. The modules are formed on conventional printed circuit cards with memory chips packaged or unpacked directly attached to the memory module. Thermal control structures can be included to keep the high density module within the reliability range of operating temperatures.

Description

Low profile, high density memory system

The current design trend of electronic packages used in high-speed electronic systems is to provide high electrical performance, high density, and high reliability interconnection between the various circuit elements that form the major parts of these systems. The system may be a computer, a telecommunications network device, a personal digital assistant, medical equipment, or other electronic equipment.

High potential reliability of these connections is essential because a potential end product failure can result in fatal misconnections of these devices. The interconnections are as compact as possible, and it is very important to use the least amount of real estate on the printed board and to have minimal impact on the printed board wiring. In the case of laptop computers and portable devices, it is very important that the height of the connectors and auxiliary circuit members be as low as possible.

As system density and performance increase significantly, the specifications for interconnections become more stringent. One way of demonstrating high electrical performance is to improve signal integrity. This can be accomplished by providing interconnections with shielding to help match closer to the desired system impedance. These necessary requirements resulted in a wide variety of possible connector solutions, especially when coupled with the requirement for field separation.

In addition, to ensure effective repair, upgrade and / or replacement of various components of the system (eg, connectors, cards, chips, modules, etc.), the connections must be reworkable at the factory. Also, in some cases, these connections in the final product must be detachable from the shop floor and reconnectable. This capability is required even during manufacture, for example to facilitate experimentation.

A land grid array (LGA) having a plurality of contact points, each of which is connected in a linear or two-dimensional arrangement, of two primary parallel circuit elements to be connected is an example of such a connection. An array of interconnect elements, known as interposers, is located between the two arrays to which they are to be connected and provides electrical connection between the contacts or pads. Even for higher density interconnects, additional parallel circuit elements are stacked and electrically connected through additional LGA connectors to form a three dimensional package. In either case, since the holding force is not inherent as in pin-and-socket interconnects, the clamp mechanism is compressed to an appropriate amount while each contact member is engaged so that the necessary interconnects for the circuit elements It is necessary to make the force necessary to ensure that it forms. LGA intermediaries are implemented in many different ways, but the most interesting implementations are those described in the concurrent US applications mentioned above.

In applications such as high speed memory buses in use today, high speed digital computers and the complex software running on them require large amounts of random access memory (RAM) each time the bus and clock speeds are increased. do. To ensure fast memory cycle times, an extremely short and fast rising pulse is used. The electrical driving requirements for driving a large number of memory devices are much stricter than when low speed memory was used.

The maximum operating speed of a memory system is largely determined by the electrical interconnections between the memory controllers and the memory elements or buses. As the amount of data increases, the signal propagation times through the interconnects can no longer be ignored compared to the transition times of the signals. In highway buses, these interconnects function as transmission line networks. Therefore, the response characteristics of these transmission line networks determine the maximum available speed of the memory bus.

In the current generation of low profile memory packaging technology, the amount of memory physically available in the system may support the capacity of the memory elements (chips) and the number of physical electrical connections to individual cards or modules and additional memory cards. It is determined by the amount of space available. The capacity of line drivers or receivers is another limitation on the number of cards or modules that can be daisy chained.

In conventional RAM systems, the bus speed is mainly determined by the bus's signal setup time, since only a single bit may be present on the bus for a certain time interval. As a result, the highest obtainable data rate of these buses in current PC memory systems is 266 Mbits per second. Typically, impedance matching termination is not necessary or necessary for such conventional ram systems.

First, some of the devices in US Pat. No. 5,963,464 to "Dell" et al. (Stakable memory card) look similar to those of various embodiments of the present invention. However, on closer examination, significant differences emerge. The embodiments shown in Figures 1-3 of the "Dell" patent relate to stackable memory card designs. This embodiment describes a stacked memory card having connector sockets attached to the top surface of each card and connector pins attached to the bottom surface of each card. Mating sockets are included on the motherboard. This packaging technology is suitable for low speed memory bus technology, but the unshielded inductive connector pins exhibit quite a lot of electrical discontinuities that produce significant reflections and electrical noise. In addition, unused sockets on the top of the top card serve as an antenna for stray RF pickup. From a reliability / manufacture point of view, even if only one pin or socket is bent or damaged, there is a possibility of module damage in the pin and socket approach. In this case, the card must be reprocessed or discarded.

"RAMBUS "Base memory module was selected for the purpose of the disclosure, the principles taught by the present invention are not only microprocessor-based, digital signals, but also other high-speed memory modules such as DDR double data rate synchronous dynamic random access memory (SDRAM). It can also be applied to a variety of electronic package structures for many other applications requiring high speed and high performance, including process based and telecommunication based applications and subsystems.

To further increase the bus speed and at the same time increase the memory capacities more, impedance controlled buses must be employed. For example, RAMBUS technology, made by Rambus, Mountain View, California, USA, allows up to three RAMBUS Inline Memory Module (RIMM) cards, all of which are interconnected on the motherboard by a high-speed data bus. And a memory arrangement arranged. One or more termination components are located at the physical end of the bus on the motherboard.

In operation, the address / data lines leave the drive circuits on the motherboard and enter the first RIMM card of the memory chain. These same address / data lines must leave the RIMM through a second set of complete connections. This routing continues through the second and sometimes third RIMM modules before the drive lines arrive at their ends. This memory / bus configuration allows very fast transmissions to pass between the memory controller and the data storage device over relatively long busses. These buses allow multiple bits to pass through each line of the bus simultaneously, achieving an access data rate of 800 Mbits per second. More bus speeds will be possible in the future.

The most important feature of these buses is that the effective impedance of the signal propagation paths is well controlled, and that one end of the bus is the end of the bus's characteristic impedance to maintain signal fidelity and signal integrity.

In systems employing these buses, the amplitudes of the drive signals are generally much smaller than the amplitudes of conventional digital signals. This is due to the limitations on the driving strength (dv / dt) of the devices.

All of the above factors make reliable operation highly dependent on impedance control of the interconnection along the bus. Impedance mismatch along the signal transmission path will cause the signal to degrade, resulting in errors in data transmission. At the same time, maintaining accurate timing between all signal bits and clocks is also critical for reliable data transmission. For this reason, minimizing the signal-to-clock delay difference (data-to-clock skew) is another important requirement for these buses. Some of the factors contributing to skew are:

a) difference in conductor lengths,

b) deviation from the nominal impedance of printed circuit boards and / or circuit traces on printed boards,

c) the number of times a signal must pass through a connector;

d) unshielded length of the connector;

Lastly, the impedance mismatch of the connector is very important because it causes reflection, forward crosstalk, and reverse crosstalk, those that act as standing waves that contribute to timing jitter, which makes skew minimization even more difficult.

Conventional low profile memory system designs generally consist of a memory controller, clock driver and bus termination mounted on a motherboard having up to three memory slots between the controller and the termination. The data signals must pass through all modules and up to a total of six edge connectors before reaching the termination. Because of this design, current edge connectors cause crosstalk and impedance mismatches that degrade signal quality and thus limit the performance of the signal channels.

Including terminations in the memory module itself provides some form of performance improvement. Since only one set of connector pins is used (ie, it is not necessary to have bus outlets on a terminated module), the additional connector pin capacity concentrates on the addressability of a larger amount of memory on a single card or module. May be This allows the memory of two channels integrated into the memory package to increase bandwidth and double the memory capacity. Also, by eliminating approximately half of the required connector pins, the saved real estate allows more chips to be packaged in one module.

Since more memory can be placed on a single card that is physically closer to the drive circuits than ever possible, the overall buspath length is significantly reduced. Further improvement is obtained because the extra path of signals passing through the exit contacts is eliminated. Also, part of the bus path between the memory module and external terminator resistors in the prior art is eliminated.

If all memory modules must be identical (eg, all have no terminations), then a separate module can be made for the terminations only. This case is shown in the later examples. In this case or for the on-module termination introduced above, the design of the present invention reduces the design complexity and production cost of both the memory modules and the motherboard. For a memory system having one to three memory modules, the use of a termination module, which is a terminated module or a final module, helps to achieve the best system performance.

When the low profile, optionally self-terminating memory modules of the present invention are combined with the innovative LGA interconnect technology, the densities are much higher than previously possible. This allows much more memory to be packaged in height-constrained applications. More memory capacity is placed near the line drivers / receivers, reducing path lengths, especially when the memory module is self-terminated. Thermal management structures are included to reduce temperature and increase reliability.

Therefore, it is an object of the present invention to provide a low profile, high density memory package.

It is an additional object of the present invention to provide a low profile, high density memory package using the novel high density connector technology.

Another object of the present invention is to provide a low profile, high density memory module having bus terminations selectively provided in the memory module itself.

It is yet another object of the present invention to provide a low profile, high density memory package that effectively reduces data path lengths to mitigate the electrical requirements of the driver in high speed digital computers and the like.

It is another object of the present invention to provide a low profile, high density memory package that supports both signal and dual bus channels.

This application is incorporated by reference in U.S. Patent No. 6,172,859 to "Broun" et al., High capacity memory module with built-in high speed bus terminations, and U.S. patent application Ser. US Patent Application Nos. 09 / 461,065 (filed December 14, 1999), US Patent Applications Nos. 09 / 645,860, 60 / 227,689, 09 / 645,859, 09 / 645,858, all filed on August 24, 2000 and co-pending US patent application Ser. No. 09 / 772,641, filed on January 31, 2001, all of which are incorporated herein by reference.

The present invention relates to high density, low profile electronic packages, and more particularly to high density, high performance, high density memory modules having impedance control transmission line buses and optionally drive line terminators installed within the module to maintain high electrical performance. , Low profile packaging.

BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be fully understood by the detailed description thereof with reference to the accompanying drawings.

1A is a schematic representation of a prior art multi-card memory array having a bus termination on a motherboard,

FIG. 1B is an enlarged cross-sectional view of a vertically plated through hole to which the conventional connector and memory card of FIG. 1A are attached,

Figure 1c is an enlarged cross-sectional view of a low profile connector and a memory card of the prior art shown in Figure 1a,

FIG. 2A is a diagram schematically showing a low profile multi-card memory arrangement of a first embodiment of the present invention having a bus termination on a motherboard,

Figure 2b is an enlarged cross-sectional view of the low profile memory package of the present invention shown in Figure 2a,

3A is a diagram schematically showing a low profile memory arrangement of a second embodiment of the present invention having a bus termination on a final memory card,

FIG. 3b is an enlarged cross-sectional view of the low profile memory package of the present invention shown in FIG.

4A is a diagram schematically showing a low profile memory arrangement of a third embodiment of the present invention having a bus termination on a separate termination card,

Figure 4b is an enlarged cross-sectional view of the low profile memory package of the present invention shown in Figure 4a,

FIG. 5A is a view showing memory elements, contact pads and wiring between them on a RIMM card of the prior art; and

FIG. 5B illustrates a technique for enhancing electrical performance inherent in the disclosed embodiments of the present invention as opposed to the prior art shown in FIG. 5A.

The present invention provides a low profile, high density electronic package for high speed, high performance semiconductors such as memory devices. To maintain electrical high performance, the present invention includes a plurality of modules having high speed impedance controllable transmission line buses, short interconnections between modules and optionally driveline terminators embedded in one of the modules. It is desirable to include but not limited to microprocessor databuses and memorybuses such as RAMBUS and DDR. The modules are formed on conventional printed circuit cards with memory chips packaged or unpacked directly attached to the memory module. The use of memory modules with bus terminations mounted directly on the module enhances the performance of the systems by improving signal characteristics and integrity. This design also eliminates the need for bus exit connections, allowing the free connection capacity to be used to specify the additional memory capacity of the module. Thermal control structures are included to maintain high density modules at operating temperatures within the reliability range.

Generally speaking, the present invention is a low profile, high density electronic package for high speed, high performance semiconductors such as bare memory chips or memory devices made from conventional memory chip packages. It has a plurality of modules with high speed impedance controlled transmission line buses, short LGA interconnect between the module and the motherboard, and optionally drive line terminators embedded in one of the modules, in order to maintain electrical high performance. Thermal control structures are included to maintain high density modules at operating temperatures within the reliability range.

Referring first to FIG. 1A, a schematic diagram of a prior art multi-card (2-card) memory system 10 is shown. Conventional two-slot and three-slotboards require terminations on motherboard 12, which are required even when all slots are not used. Signal quality is degraded proportionally by standard card-mount board connectors 22 and 36 with electrical noise providing signal paths between RIMM cards 24 and 38 and circuitry on motherboard 12. .

Although RAMBUS-based memory subsystems have been selected for the purpose of disclosure, the principles taught by the present invention include microprocessor-based, digital signal processing-based and telecommunication-based applications, as well as high-speed memory modules such as DDR SDRAM and the like. Apparently, it can be applied to many different electronic package structures for many other applications requiring high speed and high performance, including subsystems.

Part of the motherboard 12 is equipped with support circuitry for implementing a RAMBUS memory system. A master device 16 including a direct RAMBUS clock generator (DRCG) circuit 14 and a direct RAMBUS ASIC cell (DRAC) 18 is embodied on the motherboard 12. The RAMBUS channel unit 20 connects the DRAC 18 to the first connector 22 that is physically connected to the motherboard 12. Connections of the RAMBUS channel section 20 are generally made by internal print wiring traces (not shown). The first connector 22 generally has a plurality of spring load contacts designed to engage the mating contact pads on the first RIMM card 24.

In the RAMBUS architecture, 184 contacts are typically provided on each memory module. The RAMBUS channel section 20 enters the first RIMM card 24 in the bus entry area 26 and through a plurality of individual memory devices 28 attached to the RIMM card 24 through the element connecting sections 30. Connected. The RAMBUS channel then exits the RIMM card 24 through the RAMBUS channel exit area 32 and passes from behind the first RIMM card 24 to the motherboard 12. The additional printed wiring traces extend the RAMBUS channel portion 34 to the second connector 36 on the motherboard 12. The second connector 36 supports the second RIMM card 38.

The RAMBUS channel entry section 40, the series of memory elements 28, the series of device connection sections 42 and the RAMBUS channel exit section 44 constitute a second RIMM card 38. The RAMBUS channel section 46 finally reaches the terminations 48 at the end of the bypass routing of the bus after passing through the printed circuit traces.

Termination components, such as resistors, blocking capacitors and / or decoupling capacitors 48, are also disposed on the motherboard 12. All RAMBUS channel signals must pass through two connectors 22, 36 and cross two RIMM cards 24, 38 before reaching the terminations 48. Signal degradation occurs along the path of the RAMBUS channel, in particular the connectors 22 and 36. In addition, useful "real estate" is consumed on the motherboard 12 itself.

RIMM cards 24 and 38 are typical printed circuit structures that include epoxy-glass based materials (ie FR4) and have one or more conductive layers therein (ie, signal, power and / or ground). Due to strict electrical specifications, signal traces must match within 10% of the system impedance.

The connectors shown in FIGS. 1B and 1C are the vertical and horizontal physical forms of the schematic connectors 22, 36 of FIG. 1A, respectively. Since connectors 22 and 36 are generally the same, only connector 22 will be described in FIGS. 1B and 1C.

Referring now to FIG. 1B, it is an enlarged cross-sectional view of the vertically plated through hole to which the conventional connector and memory card shown in FIG. 1A are attached. The spring load contacts 23 'of the connector 22' provide an electrical connection between the motherboard 12 and the contact pads 29 of the RIMM card 24. The connectors 22 'of this type can be plated through hole attachment or surface mount attachment to a structure such as motherboard 12 (FIG. 1A), while plated through hole attachment is electrically inferior. Generally used. In either case, the spring load contacts 23 'of the connector 22' exhibit significant electrical discontinuity, especially at today's high bus speeds. This impedance discontinuity appears as an increase in electrical noise and time delay due to reflection. Also, this vertical connector cannot be used in low profile applications.

Referring now to FIG. 1C, an enlarged cross-sectional view of the prior art low profile connector and memory card shown in FIG. 1A is shown. The spring load contacts 23 "of the connector 22" provide an electrical connection between the motherboard 12 and the contact pads 29 of the RIMM card 24. The connectors 22 'of this type are mainly surface mounted to a structure such as the motherboard 12 or the like (FIG. 1A). Spring-loaded contacts 23 "exhibit a significant electrical discontinuity, especially at today's high bus speeds. This horizontal connector 22" has a significantly lower profile but can be used in low profile applications, but in multicard applications. Needs more motherboard real estate. Although a two-level stacked type of this connector can be used, the connection to these spring contacts also becomes long, so that electrical discontinuity and thus electrical noise are worsened.

The specific arrangement and location of the memory elements 28 on the modules 24 and 38 may vary depending on the particular application and have little effect on the present invention as described in the prior art or the following, but the amount of memory elements is the RAMBUS specifications. And restrictions.

Three implementations of low profile memory arrays are disclosed below in accordance with other embodiments of the present invention, the main difference being that the bus termination 48 is on motherboard 12 in the examples of FIGS. 2A and 2B, and FIG. 3A. And in the example of 3b there is a bus termination 48 on the last card 82, and in the example of FIGS. 4A and 4B there is a bus termination 48 on a separate termination card 92.

Referring now to FIG. 2A, a schematic diagram of a low profile memory card system 50 of the present invention is shown. Part of the motherboard 12 has support circuitry necessary to implement a RAMBUS memory system. The master device 16, which includes the DRCG circuit 14 and the DRAC circuit 18, is implemented on the motherboard 12 in the same manner as the memory card implementation of the prior art discussed above and shown in FIG. 1A.

The RAMBUS channel section 20 connects the DRAC 18 to the LGA connector 52. Again, the RAMBUS channel portion 20 connections are generally made by printed wiring traces (not shown) on one or more layers (not shown) of the motherboard 12. The LGA connector 52 is disposed between the motherboard 12 and the first card 54, providing an electrical interconnect therebetween. The LGA connectors 52 and 64 generally engage the mating contact pads 51 on the motherboard 12 and the first card 54 and alternate from the first card 54 to the second card 66. It has a plurality of short elastic contact members 53 designed to engage the contact pads 51 (FIG. 2B). The housing / carrier 49 of the LGA connectors 52 and 64 preferably has a coefficient of thermal expansion approximately equal to the coefficient of thermal expansion CTE of the peripheral cards 54 and 66.

The contact members 53 are as taught in one of the referenced concurrent US patent applications, preferably with an electrically mechanically improved configuration and composition by teaching two other concurrent US patent applications. Do. Compared to the pin-and-socket LGA connectors of the prior art, the connectors 52 and 64 of the present invention provide a CTE that is better matched with improved performance, increased density, lower height and peripheral structures. Also, because the force per contact required by the connectors 52, 64 is smaller, the number of contacts considering the amount of holding force given increases significantly.

The RAMBUS channel portion 20 enters the first card 54 in the bus entry area 56 and is connected to a plurality of individual memory elements 28 attached to the card 54 through the element connecting portions 58. Next, the RAMBUS channel exits the card 54 through the RAMBUS channel exit area 60, and the RAMBUS channel portion 62 passes through the LGA connector 64 instead of the rear surface of the motherboard 12 to the first card 54. From directly through to the second card (66).

The RAMBUS channel entry portion 68, the series of memory elements 28, the series of element connection portions 70 and the RAMBUS channel exit portion 72 constitute a second card 66. The RAMBUS channel portion 74 reaches the terminations 48 after passing through the other contact members 53 of the connectors 64 and 52 at the shortest distance. As in the case of the prior art, termination elements such as resistors, blocking capacitors and / or decoupling capacitors 48 and the like are also disposed on the motherboard 12.

Cards 54 and 66 are typically printed circuit structures that include epoxy-glass based materials (ie, FR4) and have one or more conductive (ie, signal, power, and / or ground) layers therein ( 2b). Epoxy-glass based materials are cost effective and motherboard 12 and LGA connectors 52, although other materials may be used for various reasons, including electrical performance, wirability and thermal performance. And a CTE that matches the CTE of 64). In addition, due to stringent RAMBUS electrical specifications, the signal traces must match within 10% of the system impedance.

Referring now to FIGS. 3A and 3B, there are shown diagrams schematically showing the low profile memory card system 80 of the present invention. Part of the motherboard 12 has support circuitry required for the implementation of the RAMBUS memory system. The master device 16 including the DRCG circuit 14 and the DRAC circuit 18 is implemented on the motherboard 12 in the same manner as the embodiment discussed above and shown in FIG. 2A. The first card 54 does not change either. The second card 82 includes a RAMBUS channel entry 84, a series of memory elements 28, and a series of device connections 86. However, unlike the embodiment of Figures 2A and 2B, the terminations 48 are mounted directly to the card 82, thus eliminating the need for a RAMBUS channel outlet 72 (FIG. 2A) and a RAMBUS channel portion 74. This eliminates the complete additional set of contacts, which can be used to adjust additional memory capacity, etc., simplifying the card 82 and reducing costs. In one example, the printed board is reduced from eight layers to six layers. Another advantage of placing the termination on the card 82 is that the noise connected to the motherboard 12 can be reduced and the performance of the overall system can be improved.

Referring now to FIGS. 4A and 4B, schematic views are shown of a low profile memory card system 90 of the present invention. Part of the motherboard 12 has support circuitry needed to form a RAMBUS memory system. The master device 16 comprising the DRCG circuit 14 and the DRAC circuit 18 is implemented on the motherboard 12 in the same manner as the embodiments discussed above and shown in FIGS. 2A and 3A. However, in order to best manipulate certain applications, this embodiment borrows the previous two embodiments. The advantages of termination on the card are well understood and highly preferred for the above reasons, but from a manufacturing and symbolic point of view, it is desired that essentially the same memory cards be used. Thus, one way to accomplish this is to start with the two cards 54 and 66 of FIGS. 2A and 2B but with terminations 48 mounted on a separate termination card 92. The termination card 92 also includes a RAMBUS channel entry 94 and is connected via a connector 96.

In the present invention, since the holding force is not inherent as in pin-and-socket interconnects, each contact member 53 of the connectors 52, 64, 96 is compressed to an appropriate amount during fastening so that the interconnectors need to be interconnected. The clamp mechanism creates the force necessary to ensure that the connections are made. The clamping mechanism does not require any mounting holes in the motherboard 12, adjusts over the arrangement of the connection members 53 and provides a uniform force movement, avoiding problems due to CTE mismatch, and in the field It is desirable to be removable to facilitate repair and upgrade by the end user.

Means for aligning cards 54, 66, 82 to motherboard 12 have not been specifically described in this embodiment, but various methods that can be implemented will already be apparent to those skilled in the art.

Low profile due to the lack of heat transfer medium that effectively transfers heat from the package or frame of the memory elements 28 to the atmosphere and the lack of short air channels in the airflow direction (i.e., parallel to the motherboard 12). The natural cooling efficiency of the memory card system 50, 80, 90 is low. This cooling efficiency is deteriorated in these high density packages because memory elements 28 are relatively large in size and close to other heating memory elements 28 nowadays. Thermal management structures (not shown) may be included in the systems of the present invention to optimize both thermal conduction and radiation to enable the highest circuit density without heat accumulation that degrades the performance and reliability of the memory elements 28.

Thermal management structures are intended to dissipate heat from memory elements 28 and may be implemented in a variety of ways. This thermal management structure may be as simple as a layer of heat transfer material such as aluminum that is attached or held to the memory elements 28 by thermal enhancement elements or clamps. These structures may be more complex and may include devices such as fins that increase cooling. Alternative methods may include the use of conformal bags, thin heat pipes and thermoelectric elements of the liquid heat transfer material. Other methods of solving the heat release will be apparent to those skilled in the art.

Although the three implementations disclosed above have been described as two cards of memory elements for the purpose of disclosure, parameters such as the number of cards, the specific shape, dimensions, and materials, and the number and packaging of memory elements vary according to specific requirements. It will be apparent to those skilled in the art. These variations are within the scope of the present invention.

The following are the advantages and advantages that exist in all embodiments of the present invention.

Compared to the prior art RIMM cards 24 and 38 where all contacts must be located along one edge, all of the cards 54, 66 and 82 have contact pads which can be optimally positioned in various ways so that the contacts Improve parameters such as density, wiring, reliability and electrical and mechanical performance. This can also optimize the motherboard 12.

An example of how the present invention provides a method of optimizing the electrical properties of the signal connections of the cards 54, 66, 82 compared to the prior art (FIG. 5A) is shown through the bottom view of FIG. 5B. 5A shows a typical wiring of memory device 28 to contact pads 29 of RIMMs 24 and 38. Since all signals enter and exit the RIMM cards 24 and 38 through the same edge 31, the length of the signal connections 25 connecting to the element contact pads 27 of the memory elements 28 is at least at least. The length "L" of the memory element 28 changes. This causes a difference in connection noise and time delay for each of the signal connections. In the present invention (FIG. 5B), the proper placement of the contact pads 55 on the cards 54, 66, 82 allows for minimization and equalization of the lengths, so that all of the cards 54, 66, 82 can be identified. The electrical performance of the signal contacts 57 may be optimized.

Another benefit of the optimization method shown in FIG. 5B is the huge amount of real estate saved. In some cases, the size and / or complexity of the cards 54, 66, 82 (FIGS. 2B, 3B) may be reduced. In other cases, additional real estate can be used to improve the electrical performance of low profile memory card systems 50, 80, 90, Figs. 2B, 3B, 4B. As an example, the electrical performance of critical nets such as clock lines can be improved by separating / isolating these networks / lines from more noisy networks.

Signal degradation occurs along the path of all RAMBUS channels, in particular along the RAMBUS channel path at the connectors. Compared with the conventional RAMBUS based memory subsystems shown in FIGS. 1A-1C, it can be seen that the total bus length and thus the total time delay of the memory system of the present invention is significantly reduced. Reducing the bus length facilitates driving requirements for devices on the bus, reducing costs and improving reliability.

In general, high memory access speeds can be achieved by improving the quality of the RAMBUS channel (ie, reducing its length, channel delay, crosstalk, etc.). The removal of connectors between memory cards and terminations as well as the reduced path length improves electrical integrity. As an example, the electrically unshielded spring load contacts 23 ', 23 "of conventional connectors 22', 22" are 0.150 inches long, whereas in the present invention, connectors 52, 64 The contact members 53 are only 0.060 inches in length. If the contact members 53 are packaged in a shielded housing as taught in one of the referenced concurrent US patent applications, the electrical discontinuity is minimized. In the case of the signal crossing from the first card 54 to the second card 66, 82 of the present invention, two long, unshielded and electrically noisy connectors 22, 36 and RAMBUS channel section 34 degrees Signal degradation caused by passing through 1a) is eliminated. This also simplifies the wiring of the motherboard 12 and / or reduces the cost of the motherboard 12.

Elimination or shortening of the connectors improves electromagnetic susceptibility (EMI) susceptibility and reduces the emission of RF from the motherboard 12 and the cards 54, 66, 82.

Compared to the circuit of the conventional RIMM cards 24, 38 (FIGS. 1A and 1B), in which only a certain number (e.g., 8 or 16) of the memory elements 28 is allowed, the present invention provides the memory elements 28 as shown in FIG. By allowing another division of), all real estate that can not be used without dividing on cards 54, 66, 82 with the highest density can be used.

Since other variations and modifications that have been made to satisfy particular operating requirements and environments are apparent to those skilled in the art, the present invention is not limited to the examples selected for the purpose of disclosure, and the true spirit and scope of the present invention. It includes all modifications and changes without departing from.

In the invention thus described, what is intended to be protected by this patent is subsequently expressed in the appended claims.

Claims (54)

In the electronic package for high frequency semiconductor devices, A plurality of circuit members each having a first surface and a second surface, the plurality of contact pads being disposed on the first surface, wherein at least one of the contact pads is connected to an external data bus; A first electrical connection comprising a contact member operatively connected to at least one of the conductive pads on the first surface of at least one of the circuit members forming an extension of the external data bus to provide an electrical interconnection Way; At least one semiconductor device positioned on at least one of the surfaces of the plurality of circuit members and selectively connected to the data bus extension; A plurality of contact pads disposed on the second surface of at least one of the circuit members, at least one of which further extends the external data bus; Clamping means attached to at least one of the circuit members to press the contact member of the first electrical connection means; And An electronic package for a high frequency semiconductor device comprising a bus termination means operatively connected to the data bus extension. The electronic package of claim 1, wherein the external data bus includes a characteristic impedance and the bus terminating means exhibits an impedance substantially matching the characteristic impedance. The electronic package of claim 1, further comprising alignment means operatively connected to at least one of the circuit members to align the first electrical connection means thereto. 2. The device of claim 1, disposed between two of the circuit members and operating on at least one conductive pad on the first surface of at least one of the circuit members and on at least one conductive pad on the second surface. An electronic package for a high frequency semiconductor device further comprising a second electrical connection means connected to. 5. The electronic package of claim 4, further comprising alignment means operatively connected to at least one of the circuit members to align the first electrical connection means thereto. 3. The electronic package of claim 2, wherein the bus terminating means comprises at least one electric element selected from the group consisting of resistors, capacitors and inductors. The electronic package of claim 6, wherein the resistors include individual resistors. The electronic package of claim 6, wherein the resistors comprise a resistor pack. 7. The electronic package of claim 6, wherein the resistors comprise a solid resistance element. 3. The electronic package of claim 2, wherein the bus terminating means is located outside the electronic package. 3. The electronic package of claim 2, wherein the bus terminating means is located at one of the circuit members. The electronic package of claim 2, further comprising a termination module, wherein the bus termination means is located in the termination module. The electronic package of claim 1, wherein the first electrical connection means is a land grid array (LGA) connector. The electronic package of claim 13, wherein the LGA connector is a Superbutton ^TM based connector provided by High Connection Density Inc. The electronic package of claim 1, wherein at least one of the semiconductor devices is a memory device. The electronic package of claim 1, wherein the circuit members include wiring means for connecting at least one of the contact pads on the first surface to at least one of the contact pads on the second surface. The electronic package of claim 1, wherein the circuit members comprise a multilayer printed circuit card. The semiconductor device of claim 1, wherein at least one of the semiconductor devices is formed from a group consisting of bare chips, thin, small-outline packages (TSOPs), chip scale packages (CSPs), and chip on boards (COBs). An electronic package for a high frequency semiconductor device including at least one selected. The electronic package of claim 1, wherein the plurality of circuit members are parallel to each other to be operated. 20. The electronic package of claim 19, further comprising an external printed circuit structure, wherein the plurality of circuit members are parallel to operate with the external printed circuit structure. The electronic package of claim 1, further comprising thermal management structures. 22. The electronic package of claim 21, wherein the thermal management structures comprise thermally conductive pins in thermal contact with the at least one semiconductor device. 2. The system of claim 1, wherein: the external data bus comprises at least two external data buses; The extension of the external data bus includes at least two extensions of the two data buses; The semiconductor device includes two groups of at least one semiconductor device, each of which is independently connected to at least one of two data bus extension portions. The electronic package of claim 1, wherein the at least one semiconductor device comprises a pattern of contact pads on a first surface of the at least one semiconductor device. 25. The device of claim 24, wherein at least some of the plurality of contact pads on one side of the plurality of circuit members are operatively identical to the pattern of contact pads on the first side of the at least one semiconductor device. Electronic package for high frequency semiconductor devices arranged in the. 27. The electronic package of claim 25, further comprising interconnections between the pattern of contact pads in the plurality of circuit members and the pattern of contact pads in the at least one semiconductor device. 27. The electronic package of claim 26, wherein the interconnections are approximately equal in length, the length is shortened, and length adjustment to match the length of the interconnections is minimized. 28. The electronic package of claim 27, wherein the interconnections have approximately equal propagation delays, the propagation delays are shortened, and propagation delay adjustment to match the propagation delays of the interconnections is minimized. In the electronic package for high frequency semiconductor devices, A plurality of circuit members each having a first surface and a second surface, the plurality of contact pads being disposed on the first surface, wherein at least one of the contact pads is connected to an external data bus; A first electrical connection comprising a contact member operatively connected to at least one of the conductive pads on the first surface of at least one of the circuit members forming an extension of the external data bus to provide an electrical interconnection Means; At least one semiconductor device positioned on at least one of said surfaces of said plurality of circuit members and optionally connected to said data bus extension, at least one semiconductor comprising a first pattern of contact pads on said first surface device; A plurality of contact pads disposed on the second surface of at least one of the circuit members, at least one of which further extends the external data bus; Clamping means attached to at least one of the circuit members to press the contact member of the first electrical connection means; And Bus termination means operatively connected to the data bus extension; At least some of the plurality of contact pads on one surface of the plurality of circuit members may be in a second pattern that is identical to the first pattern of contact pads on the first surface of the at least one semiconductor device. Electronic package for high frequency semiconductor devices. 30. The system of claim 29, wherein at least one of the plurality of circuit members comprises: a plurality of interlocking pads; And And an interconnection extending from said first pattern of contact pads in said at least one semiconductor device to said second pattern of contact pads in said plurality of circuit members. 31. The electronic package of claim 30, wherein the interconnections are approximately equal in length, the length is shortened, and length adjustment to match the length of the interconnections is minimized. 32. The electronic package of claim 31, wherein the interconnections have approximately equal propagation delays, the propagation delays are shortened, and propagation delay adjustment to match the propagation delays of the interconnections is minimized. 30. The electronic package of claim 29, wherein the external data bus includes a characteristic impedance and the bus terminating means exhibits an impedance that is operatively matched with the characteristic impedance. 30. The electronic package of claim 29, further comprising alignment means operatively connected to at least one of the circuit members to align the first electrical connection means thereto. 30. The device of claim 29, disposed between two circuit members and operated to at least one conductive pad on the first surface and at least one conductive pad on the second surface on at least one of the circuit members. An electronic package for a high frequency semiconductor device further comprising a second electrical connection means connected. 36. The electronic package of claim 35, further comprising alignment means operatively connected to at least one of the circuit members to align the first electrical connection means therewith. 34. The electronic package of claim 33, wherein the bus terminating means comprises at least one electrical element selected from the group consisting of resistors, capacitors and inductors. 38. The electronic package of claim 37, wherein the resistors comprise individual resistors. 38. The electronic package of claim 37, wherein the resistors comprise a resistor pack. 38. The electronic package of claim 37, wherein the resistors comprise a solid resistance element. 34. The electronic package of claim 33, wherein the bus terminating means is disposed outside the electronic package. 34. The electronic package of claim 33, wherein the bus terminating means is located in one of the circuit members. 34. The electronic package of claim 33, further comprising a termination module, wherein the bus termination means is located in the termination module. 30. The electronic package of claim 29, wherein the first electrical connection means is a LGA connector. 45. The electronic package of claim 44, wherein the LGA connector is a Superbutton ^TM based connector provided by HighConnection Density Inc. 30. The electronic package of claim 29, wherein at least one of the semiconductor devices is a memory element. 30. The electronic package of claim 29, wherein the circuit members comprise wiring means for connecting at least one of the contact pads on the first surface to at least one of the contact pads on the first surface. 30. The electronic package of claim 29, wherein the circuit members comprise a multilayer printed circuit card. 30. The electronic package of claim 29, wherein at least one of the semiconductor devices comprises at least one selected from the group consisting of bare chips, TSOPs, CSPs, and COBs. 30. The electronic package of claim 29, wherein the plurality of circuit members are parallel to each other to be operated. 51. The electronic package of claim 50, further comprising an external printed circuit structure, wherein the plurality of circuit members are parallel to operate with the external printed circuit structure. 30. The electronic package of claim 29, further comprising thermal management structures. 53. The electronic package of claim 52 wherein the thermal management structures comprise thermally conductive pins in thermal contact with the at least one semiconductor device. 30. The system of claim 29, wherein: the external data bus comprises at least two external data buses; The extension of the external data bus includes at least two extensions of the two data buses; The semiconductor device includes two groups of at least one semiconductor device, each of which is independently connected to at least one of two data bus extension portions.