KR20020019139A - Semiconductor devices and manufacturing method thereof - Google Patents

Abstract

In order to effectively prevent the leakage current due to the short channel effect caused by the miniaturization of the semiconductor device CD, a metal floating gate is formed on the sidewall of the gate electrode to deplete the semiconductor substrate under the metal floating gate during operation of the semiconductor device. The induction region is formed to act as an LDD structure of the conventional semiconductor device. Since the depletion induction region corresponding to the LDD structure is not affected by the drain voltage during the operation of the semiconductor device, leakage current due to a short channel effect can be effectively prevented. have.

Description

Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICES AND MANUFACTURING METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same. More particularly, the present invention relates to a semiconductor device capable of effectively preventing short channel effects caused by a decrease in the gate CD of the semiconductor device. The manufacturing method is related.

In general, a metal oxide semiconductor (MOS) transistor is a type of field effect transistor (FET), and includes a source and a drain region formed on a semiconductor substrate, a gate oxide film and a gate oxide film formed on the semiconductor substrate on which the source and drain regions are formed. It has a structure in which a gate electrode is formed.

In addition, in order to prevent short channel effects due to miniaturization of semiconductor devices, MOS transistors having a lightly doped drain (LDD) region having a low impurity concentration inside the source and drain regions are mainly used.

Such MOS transistors can be divided into N-channel MOS transistors and P-channel MOS transistors according to the type of channel. When MOS transistors of N-channel and P-channel are formed on a single semiconductor substrate, these MOS transistors are called complementary metal oxide semiconductor (CMOS) transistors. do.

Next, a structure of a conventional general MOS transistor will be described with reference to FIG. 1.

As can be seen in FIG. 1, in the conventional MOS transistor, a field oxide film 2 for element isolation is selectively formed on a P-type or N-type semiconductor substrate 1 to form an active area where a semiconductor device is to be formed. It is defined. A gate oxide film 3 and a gate electrode 4 are formed on a part of the active region of the semiconductor substrate 1 defined by the field oxide film 2, and a spacer formed of an insulating film on the sidewall of the gate electrode. (7) is formed.

In the active region of the semiconductor substrate 1 between the outer edge of the spacer 7 and the field oxide film 2, a source / drain region 8 having a high concentration of impurities of opposite conductivity type as the semiconductor substrate 1 is formed. The source / drain region 8 may be formed in the semiconductor substrate 1 under the spacer 7, which is inside the source / drain region 8, that is, between the end of the gate electrode 4 and the source / drain region 8. An LDD region 6 in which impurities of the same conductivity type as that are embedded in a low concentration is formed.

In addition, a poly oxide film 5 may be formed between the gate electrode 4 and the spacer 7.

In the conventional MOS transistor having such a structure, as shown in FIG. 2, the voltage (V _G = 3.3 V, V _D = 3.3) is applied to the gate electrode G and the drain electrode D to operate the device in the N MOS transistor. When V) is applied, the equipotential lines (V ₀ = 3.3V) formed in the drain electrode (D) region under the influence of the drain voltage (V _D ) are formed outside the drain electrode (D) region, especially in the LDD region. An equipotential line (V ₀ = 3.3V) is formed inside the gate electrode (G).

At this time, since the equipotential line V ₀ = 3.3V is formed inside the gate electrode G in the LDD region of the drain electrode D, a leakage current is generated due to a short channel effect, and the semiconductor device is miniaturized. Therefore, as the gate CD decreases, the leakage current due to the short channel effect in the LDD region increases.

Therefore, in the conventional semiconductor device, the LDD structure has a disadvantage of being very vulnerable to the leakage current caused by the short channel effect.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object thereof is to provide a semiconductor device and a method of manufacturing the same, which can effectively prevent leakage current due to a short channel effect generated as the gate CD becomes smaller due to miniaturization of the semiconductor device. To provide.

1 is a cross-sectional view schematically showing a structure of a conventional semiconductor device,

2 is a cross-sectional view schematically showing an equipotential line of a drain region according to device operation in a conventional semiconductor device,

3 is a cross-sectional view schematically showing a structure of a semiconductor device according to an embodiment of the present invention;

4 is a cross-sectional view schematically showing an equipotential line of a drain region according to device operation in a semiconductor device according to an embodiment of the present invention;

5A and 5B are cross-sectional views schematically illustrating a band gap arrangement and a depletion layer forming state in an N MOS transistor and a P MOS transistor by a metal floating gate in a semiconductor device according to an embodiment of the present invention;

6A through 6E are process diagrams schematically illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

In order to achieve the above object, the present invention is a gate oxide film formed on a portion of the active region of the semiconductor substrate, a gate poly formed on the upper portion of the gate oxide film, a poly oxide film formed on the side of the gate poly, A metal floating gate formed on a sidewall of the poly oxide film, a spacer formed on a sidewall of the poly oxide film including the metal floating gate, and a source / drain region in which impurities are embedded in a junction region of the semiconductor substrate at a lower end of the metal floating gate. Characterized in that it comprises a.

In addition, the present invention is to form a field oxide film for defining the active region of the semiconductor substrate, thermal oxidation to grow a gate oxide film in the active region of the semiconductor substrate, and after depositing polysilicon on the upper surface of the semiconductor substrate Forming a gate poly on a portion of the gate oxide layer by patterning and thermally oxidizing a poly oxide layer, depositing a barrier metal layer and a metal layer on the entire upper surface of the semiconductor substrate, and isotropically etching the metal layer Forming a metal floating gate on sidewalls of the poly oxide film, isotropically etching and removing the exposed barrier metal film, the poly oxide film on the gate poly, and the gate oxide film on the semiconductor substrate other than the floating gate; Doping impurities on the exposed semiconductor substrate Forming a source / drain region and depositing an insulating film over the entire surface of the semiconductor substrate and isotropically etching to form a spacer on a side of the poly oxide film including the metal floating gate.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

3 is a cross-sectional view schematically illustrating a structure of a semiconductor device according to an embodiment of the present invention.

As can be seen in FIG. 3, in the semiconductor device according to the exemplary embodiment, a field oxide film 12 is formed in an isolation region of a P-type or N-type semiconductor substrate 11 to form a semiconductor device. Is defined. At this time, a P well or an N well is formed in the semiconductor substrate 11 in the active region defined by the field oxide film 12 to form an N-type semiconductor device or a P-type semiconductor device to form an N-type semiconductor device. It is also possible to form a mold region.

A gate oxide film 13 is formed over a portion of the active region of the semiconductor substrate 11 defined by the field oxide film 12, and a gate poly 14a is formed over a predetermined region of the gate oxide film 13. It is. A metal floating gate 17a is formed on the gate oxide layer 13 on the side of the gate poly 14a, and an insulating film, preferably on the side of the gate poly 14a including the metal floating gate 17a. The spacer 19a formed of the nitride film is formed. At this time, the height of the metal floating gate 17a is preferably equal to or less than the height of the gate poly 14a, and the metal floating gate 17a is preferably formed of tungsten.

A poly oxide film 15 is formed on the junction surface of the gate poly 14a, the metal floating gate 17a, and the spacer 19a, and the metal floating gate 17a, the poly oxide film 15, and the gate oxide film 13 are formed. ), A barrier metal film 16 is formed. At this time, the barrier metal film 16 is preferably formed of TiN.

In the junction region of the semiconductor substrate 11 that extends from the lower end of the metal floating gate 17a to the field oxide film 12, a source / drain region in which impurities of a conductivity type opposite to the semiconductor substrate 11 or the well are embedded ( 18) is formed.

In the MOS transistor according to the exemplary embodiment of the present invention having the structure as described above, as shown in FIG. 4, the voltage (V _G = 3.3 V) is applied to the gate electrode G and the drain electrode D to operate the device in the MOS transistor. , V _D = 3.3 V), the equipotential lines V ₀ = 3.3 V formed in the drain electrode D region under the influence of the drain voltage V _D are formed outside the drain electrode D region. A depletion induced channel d is formed below the metal floating gate 17a.

At this time, in the depletion induction channel d formed under the metal floating gate 17a, holes are depleted in the N MOS transistor P well to form the electron channel e as shown in FIG. 5A. As in 5b, in the P MOS transistor N well, electrons are depleted to form the hole channel h. The depletion induction channel d under the metal floating gate 17a thus formed serves as an LDD of a conventional semiconductor device.

Therefore, in the case of using the depletion induction channel d formed by the metal floating gate 17a according to the present invention instead of the LDD structure, since the depletion induction channel d is not affected by the drain voltage V _D , the conventional LDD structure In comparison with this, leakage current due to short channel effects can be effectively prevented.

In addition, a CMOS transistor may be formed by simultaneously forming an N MOS transistor and a P MOS transistor having such a structure on one semiconductor substrate.

Next, a method of manufacturing a semiconductor device according to an embodiment of the present invention having such a structure will be described in detail with reference to FIGS. 6A to 6E.

First, as shown in FIG. 6A, a field oxide film 12 is formed in an isolation region of a P-type or N-type semiconductor substrate 11 to define an active region in which a semiconductor element is to be formed. At this time, a P well or an N well is formed in the active region of the semiconductor substrate 11 defined by the field oxide film 12 through ion implantation to form an N-type active region or an N-type semiconductor element in which a P-type semiconductor element is to be formed. It can also form a P-type active region to be. The semiconductor substrate 11 is thermally oxidized to grow a gate oxide film 13 on the active region surface of the semiconductor substrate 11 defined by the field oxide film 12, and the semiconductor substrate 11 including the gate oxide film 13. A polysilicon 14 to be used as a gate electrode is deposited on the upper front side. Thereafter, a gate pattern M for gate electrode patterning is formed in an appropriate region on the polysilicon 14. In this case, for example, the gate pattern M may be formed by applying a photoresist film on the entire upper surface of the polysilicon 14 and then exposing the photoresist with a mask on which the gate pattern is formed, and developing the exposed photoresist film to form a photoresist pattern.

Next, as shown in FIG. 6B, the polysilicon 14 exposed as the mask of the gate pattern M is etched to form a gate poly 14a, and the gate pattern M on the gate poly 14a is removed. do. At this time, the etching of the polysilicon 14 is preferably performed by a reactive ion etch (RIE) process.

Then, as illustrated in FIG. 6C, the poly oxide film 15 is formed on the outer wall of the gate poly 14 a by thermally oxidizing the gate poly 14 a, and then the barrier metal layer 16 is formed on the entire upper surface of the semiconductor substrate 11. Deposit. At this time, the barrier metal film 16 is preferably formed of TiN, and the deposition of the barrier metal film 16 is preferably performed by a chemical vapor deposition process. The metal film 17 is deposited on the barrier metal film 16. At this time, it is preferable to use a metal film such as tungsten having a high melting point as the metal film 17, and the deposition of the metal film 17 is preferably performed by a chemical vapor deposition process.

6D, the metal film 17 is isotropically etched to form the metal floating gate 17a on the sidewall of the gate poly 14a. At this time, the isotropic etching of the metal film 17 is performed by a reactive ion etching process, and the etching selectivity of the metal film 17 and the barrier metal film 16 during the reactive ion etching is about 20: 1 to 30: 1. It is preferable to use SF ₆ gas as an etching gas for reactive ion etching. In addition, the height of the metal floating gate 17a formed on the sidewall of the gate poly 14a by isotropic etching is preferably equal to or less than the height of the gate poly 14a.

6E, the barrier metal film 16 exposed by the isotropic etching, the poly oxide film 15 on the gate poly 14a, and the gate oxide film 13 on the semiconductor substrate 11 are removed. In this case, isotropic etching is performed by reactive ion etching, and the etching selectivity of the barrier metal film 16 and the oxide films 15 and 13 according to the reactive ion etching is preferably about 5: 1 to 10: 1. Then, the barrier metal film 16 exposed on the gate poly 14a and the semiconductor substrate 11 by the reactive ion etching is etched away to form the poly oxide film 15 on the gate poly 14a and the gate on the semiconductor substrate 11. The oxide film 13 is exposed and the semiconductor substrate 11 and the exposed poly oxide film 15 over the gate poly 14a are etched during etching of the exposed barrier metal film 16 on the sidewall of the gate poly 14a by continuous reactive ion etching. The exposed gate oxide film 13 on etch is etched away. Thereafter, an impurity is doped in the exposed device region of the semiconductor substrate 11 to form the source / drain region 18 of the semiconductor device. In this case, as an example for forming the source / drain regions 18 by impurity doping, impurities are implanted into the device region of the semiconductor substrate 11 exposed by the gate poly 14a and the metal floating gate 17a as a mask. It is preferable to anneal to form the source / drain regions 18, and the annealing barrier metal film 16 and the metal floating gate 17a are safe because they use a high melting point. The doped impurities are P-type impurities in P-type MOS transistors, N-type impurities in N-type MOS transistors, and P-type impurities and N-type impurities in CMOS transistors. ) And an N-type MOS transistor (P well region). Thereafter, an insulating film 19 such as a nitride film is deposited on the entire upper surface of the semiconductor substrate 11.

Next, the semiconductor device is completed by isotropic etching of the insulating film 19, preferably reactive ion etching to form the spacer 19a on the sidewall of the gate poly 14a including the metal floating gate 17a as shown in FIG. do.

As described above, the present invention forms a metal floating gate on the sidewall of the gate electrode so that the depletion induction region is formed on the semiconductor substrate under the metal floating gate during the operation of the semiconductor device, thereby acting as an LDD structure of the conventional semiconductor device. Since the depletion induction region corresponding to the structure is not affected by the drain voltage, leakage current due to the short channel effect can be effectively prevented.

Claims (14)

A gate oxide film formed over a portion of the active region of the semiconductor substrate; A gate poly formed on an upper portion of the gate oxide layer; A poly oxide film formed on a side of the gate poly; A metal floating gate formed on sidewalls of the poly oxide film; A spacer formed on a sidewall of the poly oxide film including the metal floating gate; And a source / drain region in which impurities are embedded in a junction region of the semiconductor substrate at a lower end of the metal floating gate. In a CMOS transistor in which a P MOS transistor and an N MOS transistor are simultaneously formed on a semiconductor substrate, the P MOS transistor and the N MOS transistor are respectively: A gate oxide film formed over a portion of the active region of the semiconductor substrate having the field oxide film formed in the device isolation region; A gate poly formed on an upper portion of the gate oxide layer; A poly oxide film formed on a side of the gate poly; A metal floating gate formed on sidewalls of the poly oxide film; A spacer formed on a sidewall of the poly oxide film including the metal floating gate; And a source / drain region in which impurities are embedded in a junction region of the semiconductor substrate from the lower end of the metal floating gate to the field oxide layer. The semiconductor device according to claim 1 or 2, further comprising a barrier metal film formed on a bonding surface of the metal floating gate, the poly oxide film, and the gate oxide film. The semiconductor device according to claim 1 or 2, wherein a height of the metal floating gate is equal to or less than a height of the gate poly. The semiconductor device according to claim 1 or 2, wherein the metal floating gate is formed of tungsten. The semiconductor device according to claim 3, wherein the barrier metal film is formed of TiN. Forming a field oxide film for defining an active region of the semiconductor substrate, and thermally oxidizing the gate oxide film to grow in the active region of the semiconductor substrate; Depositing polysilicon on the entire upper surface of the semiconductor substrate, and then patterning to form a gate poly on a portion of the gate oxide layer, and thermally oxidizing to form a poly oxide film; Depositing a barrier metal film and a metal film on the entire upper surface of the semiconductor substrate; Isotropically etching the metal film to form a metal floating gate on sidewalls of the poly oxide film; Isotropically etching and removing the exposed barrier metal film, the poly oxide film over the gate poly, and the gate oxide film over the semiconductor substrate other than the floating gate; Doping impurities on the exposed semiconductor substrate to form source / drain regions; And depositing an insulating film on the entire upper surface of the semiconductor substrate and isotropic etching to form a spacer on a side of the poly oxide film including the metal floating gate. In the method of manufacturing a CMOS transistor in which a P MOS transistor and an N MOS transistor are simultaneously formed on one semiconductor substrate, Forming a field oxide film for defining an active region of the semiconductor substrate, and forming a P-type region and an N-type region in each active region of the defined semiconductor substrate; Thermally oxidizing the semiconductor substrate to grow a gate oxide film in each active region; Depositing polysilicon on the entire upper surface of the semiconductor substrate, and then patterning the gate poly to form a gate poly on a portion of the gate oxide layer, and thermally oxidizing to form a poly oxide film; Depositing a barrier metal film and a metal film on the entire upper surface of the semiconductor substrate; Isotropically etching the metal film to form metal floating gates on sidewalls of the poly oxide film; Isotropically etching and removing the exposed barrier metal film, the poly oxide film over the gate poly, and the gate oxide film over the semiconductor substrate other than the floating gate; Selectively doping impurities into the exposed active regions of the semiconductor substrate to form source / drain regions; And depositing an insulating film on the entire upper surface of the semiconductor substrate and isotropic etching to form spacers on each side of the poly oxide film including the metal floating gate. The method of claim 7 or 8, wherein the isotropic etching of the metal film for forming the metal floating gate is performed by reactive ion etching. The method of claim 8, wherein the reactive ion etching is performed such that an etching selectivity between the metal layer and the barrier metal layer is 20: 1 to 30: 1. The method of claim 7 or 8, wherein the isotropic etching for removing the exposed barrier metal film, the poly oxide film over the gate poly, and the gate oxide film over the semiconductor substrate other than the floating gate is performed by reactive ion etching. A semiconductor device manufacturing method, characterized in that. The method of claim 11, wherein the reactive ion etching is performed such that an etching selectivity of the barrier metal layer and the oxide layer is 5: 1 to 10: 1. The method of claim 7 or 8, wherein in the isotropic etching of the metal film to form a metal floating gate on the sidewall of the poly oxide film, the height of the metal floating gate formed on the sidewall of the poly oxide film is the height of the gate poly. Etching so that it will be the following. The method of claim 7, wherein the metal film uses tungsten and the barrier metal film uses TiN.