KR20020002671A - Column gate circuit of semiconductor memory device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a column gate circuit of a semiconductor memory device, which can quickly equalize a bit line after a read operation by preventing bit lines of unselected columns from opening during data read.

The column gate circuit of the semiconductor memory device of the present invention includes a plurality of memory cells that store data or export the stored data to the true bit line and the complement bit line, and the authentic bit line and the complement bit line are freed by an equalizing signal. A semiconductor memory device comprising precharge and equalization means for precharging and equalizing at a charge voltage, comprising: column switching means for connecting the true bit line and the complement bit line to a data line and a data bar line, respectively; And control means for controlling the operation of the two adjacent column switching means such that two adjacent pairs of bit lines are equalized when the rise signal is active and the chip select signal has the disabled state.

Description

COLUMN GATE CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a column gate circuit of a semiconductor memory device. In particular, it is possible to quickly equalize a bit line after a read operation by preventing bit lines of unselected columns from spreading during data read. It relates to a column gate circuit.

In general, when a data stored in a cell of a semiconductor memory is read out, first, when a row address is input, a word line corresponding to the address is activated, and a bit line sense amplifier operates after a predetermined time so that the cell of the active word line is activated. Latch the data (this is the row active time (tRCD)). Then, when the column address is input, the information of the selected bit line sense amplifier is sent to the data line sense amplifier through the data line, amplified, and transmitted to the data output buffer. Next, an operation and a problem of the memory cell of the SRAM will be described with reference to the accompanying drawings.

1 is a circuit diagram illustrating a column gate circuit of a conventional semiconductor memory device.

As illustrated, the bit line BL0 and the bit line bar BBL0 are precharged by a plurality of memory cells 1 to n that store data, and a control signal EQ that is enabled in the standby mode. Equalizing transistor P3 for equalizing the bit line BL1 and bit line bar BBL0 with each other by precharge transistors P1 and P2 precharged to Vcc and the control signal EQ. Read-out data stored in the memory cells 1 to n to the data lines DL0 and DBL0 by the precharge and equalization circuit unit 2n and column select signals CS0 and CSB0. A column gate circuit unit for switching the bit lines BL0 and BBL0 and the data lines DL0 and DBL0 to write the write data loaded on the data lines DL0 and DBL0 to the memory cells 1 to n. 3n).

The operation by the above configuration will now be described with reference to the operation timing shown in FIG.

If one word line is selected among the word lines WL0 to WLn, the data of the cell that is positioned on the word line WL is transferred to the bit lines BL0 and BBL0, and the data of the bit line in which the column is selected among the data lines is selected. DL0, DBL0).

A sense amplifier is connected to the data lines DL0 and DBL0 to amplify the signal output from the cell and transfer the signal to the data output buffer (not shown).

Therefore, since the loading of the signal from the cell in which the column is selected is only loading of the bit line, the potential difference between the bit lines BL0 and BBL0 of the cell in which the column is not selected is the bit line (BL0, BBL0) of the cell in which the column is selected. There is a problem that the equalization and precharge operation becomes difficult to perform after the read operation is performed more than the potential difference of.

Accordingly, an object of the present invention is to solve the above problem, and an object of the present invention is to prevent a bit line of an unselected column from opening during data read so that a column gate circuit can be equalized quickly after a read operation. To provide.

In order to achieve the above object, the column gate circuit of the present invention,

A plurality of memory cells that store data or export stored data to authentic bit lines and complement bit lines, and precharge and equalize precharge and equalize the authentic bit lines and complement bit lines to a precharge voltage by an equalizing signal In a semiconductor memory device having a rise means,

Column switching means for connecting the true bit line and the complement bit line to a data line and a data bar line, respectively;

And control means for controlling the operation of the two adjacent column switching means such that two adjacent bit line pairs are equalized when the equalized signal is active and the chip select signal has a disabled state. .

In the column gate circuit of the present invention, the column switching means is composed of a MOS transistor.

In the column gate circuit of the present invention, the column switching means is configured as a transfer gate.

In the column gate circuit of the present invention, the control means is an AND logic gate for inputting the equalization signal and the chip select signal.

1 is a circuit diagram illustrating a column gate circuit of a conventional semiconductor memory device.

2 is an operation timing diagram of FIG. 1.

3 is a circuit diagram showing a column gate circuit of the semiconductor memory device of the present invention.

4 is an operation timing diagram of FIG. 1.

Explanation of symbols on the main parts of the drawings

1 to n, 10 to 10n: memory cell

2 to 2n, 20 to 20n: precharge and equalization circuit

3 to 3n, 30 to 30n: column gate circuit section

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In addition, in all the drawings for demonstrating an embodiment, the thing with the same function uses the same code | symbol, and the repeated description is abbreviate | omitted.

3 is a configuration diagram of a column gate circuit of a semiconductor memory device according to the present invention.

As shown, a plurality of memory cells 10n that store data or export stored data to the authenticity bit line BL0 and the complement bit line BBL0, and the authenticity bit line BL0 and the complement bit line BBL0. The precharge and equalization circuit unit 20n for precharging and equalizing the precharge voltage to the precharge voltage by the equalizing signal EQ, and the true bit line BL0 and the complement bit line BBL0 are connected to the data line DL0. And two adjacent gates when the equalization signal EQ is active and the chip select signals CS0 and CSB0 have a disabled state. Control means AND0 for controlling the operation of the two adjacent column gate circuits so that the line pairs are equalized, respectively.

The control means AND0 is an AND logic gate for inputting the equalization signal EQ and the chip select signals CS0 and CSB0.

In FIG. 3, each SRAM cell receives a word line generated by a row address and a column select signal CS0 and CSB0 generated by a column address, respectively, to receive data of the cell in read mode. To pass.

Each cell is commonly connected to the word line WLn in the horizontal direction, and commonly connected to the bit line BLn in the vertical direction. Each bit line pair BL and BBL equalizes and precharges the bit line BL to a power supply voltage Vcc level during read and write operations, thereby precharging to prevent malfunction during read and write operations. The equalizing circuit unit 20 is connected. In addition, each of the bit line pairs BL and BBL is connected to a column gate circuit 30 for selectively transferring the signal of the bit line to the data lines DL0 and DBL0.

The signal propagated to the data line is amplified by the sense amplifier and passed to the data output buffer (not shown).

The above configuration is the same as the conventional technique, but the conventional technique equalizes each equalizing transistor by receiving the equalizing signal EQ, whereas the two adjacent columns have the same in equalizing the column. AND gates (AND0 ... ANDn) output are equalized, and each AND gate (AND0 ... ANDn) receives equalization signal (EQ) and chip select signal (CS) as inputs. If both EQ) and chip select signal CS are 'low', two bit line pairs are equalized.

The operation of the column gate circuit of the present invention having the above configuration will be described with reference to the operation timing shown in FIG.

As illustrated, when the word line WL is enabled (high), each cell data in the horizontal direction connected to the word line is loaded on the bit line pair. At this time, when the chip select signal CS of the column selected from the chip select signals CS0 to CSn is enabled (CS is high and CSB is low), the data of the bit line is transferred to the data line through the two selected column gates. do. At this time, since the equalizing signal EQ becomes high, the equalizing operation of the bit line by the equalizing transistor P2 is stopped.

The conventional technique is that in this case, the loading of the selected column is a bit line + data line, whereas the loading of an unselected column is only a bit line. Although it is difficult to equalize the bit line after execution, in the present invention, even though the equalization signal Eq of the unselected column becomes high, the chip select signal CS remains low, so that the bits of the unselected column are not. The equalization operation of the equalizing transistor P2 of the line continues.

Accordingly, since the bit lines of the unselected columns are hardly opened, equalizing only as much as the bit lines of the selected columns are widened when performing equalization after the read operation, enables rapid equalization and precharge operations.

In the related art, since the equalizing signal EQ is attached to all equalizing transistors, the equalizing signal EQ is loaded. However, in the present invention, six equalizing transistors are driven through the AND gate AND0. Since fewer transistors depend on the equalizing signal EQ, the loading of the equalizing signal EQ is less, which may shorten the time for transmitting the equalizing signal EQ.

As described above, according to the column gate circuit of the semiconductor memory device of the present invention, since the equalization and precharge time can be reduced, the operation cycle time of the semiconductor memory can be shortened, thereby providing a high speed semiconductor memory. .

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, these modifications and changes should be seen as belonging to the following claims. something to do.

Claims (4)

A plurality of memory cells that store data or export stored data to authentic bit lines and complement bit lines, and precharge and equalize precharge and equalize the authentic bit lines and complement bit lines to a precharge voltage by an equalizing signal In a semiconductor memory device having a rise means, Column switching means for connecting the true bit line and the complement bit line to a data line and a data bar line, respectively; And control means for controlling the operation of the two adjacent column switching means such that two adjacent pairs of bit lines are equalized when the equalized signal is active and the chip select signal has a disabled state. Column gate circuit. The method of claim 1, wherein the column switching means, A column gate circuit comprising a MOS transistor. The method of claim 1, wherein the column switching means, A column gate circuit comprising a transfer gate. The method of claim 1, wherein the control means, And an AND logic gate for inputting the equalized signal and the chip select signal.