KR20020002498A - Surface mount ic stacking method and device - Google Patents

Abstract

Package surface mount (SMT) chips with matching top and bottom contacts are stacked. Chip characteristics are chosen to provide the desired bonding force between chip layers with easier manufacturing. In one embodiment, additional spaces and path layers are optionally provided between the layers. In other embodiments, chips are distinguished by selectively providing different conductor and / or nonvolatile cell configurations. In another embodiment, a minority of the contacts of the substrate are configured such that the substrate is aligned to form a very low capacitive signal path between the dielectric region of the spacer layer or between the stacked chips.

Description

SURFACE MOUNT IC STACKING METHOD AND DEVICE

For many years, manufacturers of electronic and electromechanical systems have recognized that IC stacking methods and stacking devices sometimes allow mounting of many components in a given area of the substrate. For example, US Patent 5,612, 570 (filed April 13, 1995 by Eide et al.) Discloses a configuration for stacking one chip on each of a plurality of frames and stacking the frames. The signal path between the chip lead and the frame is provided by a trace routed through the frame.

While many known lamination methods can provide the desired PCB distribution density, the first problem that is still not properly addressed is the path where at least vertically aligned groups of identical (or very similar) chips contain multiple interfaces as chip layers. (Ie, offset vertical conductors horizontally). Each alternation between the chip layer and the interface structure adds to the cost of the processing device required to assemble the stack.

US Patent 4,956,694 (filed Nov. 4, 1988 by Eide et al.) Discloses a configuration for stacking slightly different LCC chips on a small substrate that can be laterally mounted on a large substrate. These stacked devices rely on slight differences between the dies for their functionality, because exactly the same IC dies that are correctly connected in parallel will not be able to perform their individual logic functions. A second problem, which is still technically not properly handled, is that this type of stacking device configuration requires that the die be manufactured using different masks and maintained in a separate inventory. There is a need for a stacking device that can be made identically and made up of dies that consist of individual chips in subsequent manufacturing steps.

A third problem that exists in technology is that the capacitance of conduits provided between internal circuit elements on different dies is long and very high. Incidentally, some conventional stacking configurations have reduced the length and capacity of the conduits compared to the electrical paths comprising the internal traces of the substrate, but all known configurations suffer from manufacturing difficulties or relatively low performance. .

FIELD OF THE INVENTION The present invention relates to a method and apparatus for increasing the density of integrated circuits (ICs) located on a substrate, such as a printed circuit board (PCB), and in particular, a method of stacking chips comprising surface mount technology (SMT) chip packages And to an apparatus.

1 illustrates a prior art package memory chip and path layer.

FIG. 2 shows a known stacking device including the chip of FIG. 1. FIG.

3 illustrates a conventional electromechanical system having a complex controller board of the general type that may be useful by the present invention.

4 shows a complex controller board of the present invention wherein the system of FIG. 3 has been modulated due to the replacement of the stacking device of the present invention.

5 is a cross-sectional view of the lamination apparatus of the present invention as a continuation of the manufacturing stage.

6 illustrates a detailed method of the present invention, compatible with FIG.

7 is an enlarged view of the stacking device of the present invention, inclined upward to reveal the underside of the chip, and the device is packaged with a bone-winged lead and heating sink.

8 is a cross-sectional view of the lamination device of FIG. 7.

9 is a cross-sectional view of the lead-on-lead lamination apparatus of the present invention.

FIG. 10 is a stack configuration showing one or more chips per layer, in the shape of a single layer path layer with a wider portion of the path outside the footprint of the chip.

11 is a partially enlarged view of a stacking device of the invention comprising three chips and two interfaces.

FIG. 12 is a detailed view of the stacked LLC inclined to show its interior (representing the shape of the invention) and the interface between the chips (generally shown).

13 is a Venn diagram for investigating the appropriate package size for a given set of chips being stacked, especially for dissimilar chips.

FIG. 14 is a Venn diagram as in FIG. 13 adjusted to combine two or more layers.

FIG. 15 shows a stacking device of the invention similar to FIG. 12, showing another shape for distinguishing approximately identical chips. FIG.

FIG. 16 shows the configuration of in-package conduits and unconnected contacts for individual signal coupling with each chip of a two-layer stacking device.

FIG. 17 illustrates another configuration of an unconnected contact for distinguishing chips of a stacking device that closely matches FIG. 15.

18 is a flow chart of the method of the present invention compatible with FIG.

FIG. 19 is another flow chart of the present invention compatible with FIGS. 15, 16 and 20. FIG.

FIG. 20 illustrates a number of unconnected contacts in a configuration of the present invention that is compatible with FIG. 19 of a three-layer stack. FIG.

A method and apparatus are provided that can solve these problems. The present invention is useful for stacking package surface mount (SMT) chips that feature conductors extending out of the package, each conductor having a top contact and bottom contact relative to a substrate on the stacking device being mounted. . The top contact of each chip of the top layer is preferably not fully connected, and the bottom contact of each chip of the bottom layer is preferably configured to engage the planar substrate surface. Preferred methods and apparatus of the present invention are simply achieved by keeping the chips, which must eventually be distinguished, remain about the same longer in the manufacturing process.

A first embodiment of the present invention provides a stacking method and apparatus characterized by a simple assembly by sandwiching any offset conductor or horizontal path between chips of the stack. This provides a mechanism for combining individual signals so that even the exact same chip can be accommodated. 4-12 shows a detailed example. These include specific devices for testing, heat sinks, singulation, and interface configurations.

A second embodiment of the present invention provides a stacking method and apparatus characterized by a chip configured to be aligned perpendicular to the stack and distinguished by providing different conductor and / or nonvolatile cell configurations. This allows the commonality between all dies and packages to be at least maintained until at least the conductors are mounted. A detailed example is shown in FIGS. 12-20. These include specific devices for controlling substrate bonding, accommodating dissimilar chips, accommodating the same chip, distinguishing the same device before and after stacking chips, and modulating the chip using electrical, mechanical, or optical means. Include.

A third embodiment of the present invention provides a stacking method and apparatus characterized by the contact of a few chips configured to align with a dielectric region of a space layer or substrate space. This is a very easily manufacturable configuration that allows for very short, low capacitance signal paths between stacked chips. Detailed examples are shown in FIGS. 5, 12, 15 and 17. This includes assembly, limited horizontal paths on the substrate surface, and specific devices for internal chip paths.

Each of the plurality of embodiments is described in sufficient detail to enable those skilled in the art to practice the invention, and the main problem contemplated as the invention is broader in scope than any one embodiment. The scope of the invention is clearly defined in the claims at the end of this specification. The definitions of various terms used in the present specification are used consistently in technology but have more specificity.

The lamination apparatus of the present invention is configured to be coupled with a substrate. As used herein, "top", "bottom", "upper" and the like are either "below" the lamination device, or an arbitrarily selected "bottom" of the lamination device in which the lamination is laterally mounted. It is described with reference to the substrate in "part."

A "conductor" is a continuous structure or material that has about the same electrical conductivity as a metal. A "contact" is a conductor surface configured to contact a portion of another conductor to simultaneously form a physical and electrical connection. As used herein, a "contact" of an IC die is considered to be a contact external to the die.

“Internal circuitry” on an IC chip includes resistors and active devices, but excludes the usual signal traces and availability links connected near the die contacts.

As used herein, "coupled directly" means that the object is in physical contact. When two items are directly bonded to a third item or binder, they are said to be physically "indirect". Regardless of the physical coupling, when there is a continuous conductive path between the two conductors, the two conductors are “electrically coupled”. The two conductors are electrically "internally" coupled when two conductors extend both sides in the same object as the IC package and there is a continuous conductive path between the two conductors in the object.

As used herein, an IC “package” is a surface mount technology (SMT) package with a dielectric body having a cavity large enough to accommodate the die (s) for the intended package. In addition, a body for electrical coupling with the die (s) is contacted therein and a body electrically coupled with the inner contact is externally contacted. The package used herein has a plurality of conductors each configured to facilitate chip stacking and having matched "top" and "bottom" contacts, respectively. "Matched" contact pairs present on opposite surfaces of the package are not in contact with each other.

The IC package of the present invention includes a conventional ceramic or plastic package for using an IC die. As used herein, the term "package" generally refers to components added within a package (e.g., bare die, tape-based die carriers and bond wires such as TAB components), and epoxy-coated dies But includes package leads and contact conductors. Each conductor typically includes internal contacts configured to be electrically coupled to an IC die and one or more external contacts electrically coupled to a socket, PCB pad, jumper, or other conductor. The outer contact may include, for example, a portion of the top and a portion of the gull-wing or flat pack.

Each conventional IC package includes a dielectric body having a cavity sufficient to receive the die (s) for the intended package. It is also in external contact with the body in electrical contact with the interior of the body for electrical coupling with the die (s). The surface mount IC package used in the present invention is matched with "top" and "bottom" external contacts that do not overlap to facilitate chip stacking. Conventional packages generally have a simple body shape, such as a rectangular solid, on the outside of a lead that can protrude. The two IC packages are said to be "internally identical" if the externally protruding leads are the same or not the same, if the parts inside the package are identical.

As used herein, the term "internally bondable" means that the conductor and conductive contacts are configured to be easily coupled to provide internal electrical coupling. As used herein, the term "unconnected" means that the article is configured to be internally connectable with the target conductor (ie, an IC die and / or package), but is separated from the target by a dielectric. The term "no-connect" is another technically known term for describing bifurcated conductors and their contacts. Except for the preceding sentence, the term "conductor" as used throughout this specification means a continuous conductor.

As used herein, the term "chip" refers to a package that includes at least one die, the package comprising an external contact that is electrically coupled with at least a portion of the electrically operated contacts of the at least one die. Have

The term "footprint" as used herein refers to the protruding areas of a device in a given plane, such as a two-dimensional plane, a layout, or a mounting layout of a chip.

The term " similar " die as used herein is a die having the same manufactured die and a contact that is almost all electrically operated in common, many of which are identical based on the exact same sequence and each internal circuit. Means nominal position. As used herein, the term "almost all" means at least about 90%. Thus, a package that can accommodate a complex die is in fact "similar" but can accommodate a simple die. As used herein, the term "dissimilar" is used for chips that do not follow this meaning, or for chips that include dissimilar dies.

As used herein, the term "substantially identical" means that one of the dies has all electrically operable contacts in the same nominal position relative to the internal circuitry as the other dies. The die may be composed of masks formed from the same data file, or "almost the same", all having the same structure in the same nominal arrangement. Different dies in contact or by two are considered "almost the same" if the die can perform the intended application of another die and there is a difference such that the number of product requirements assigned to a given manufacturer does not change. In the case of a single product, many calibration water is common in the IC industry.

As used herein, the term " idnetical " means a die in which all electrically operable contacts are identically configured. Manufacturing differences due to process variations or differences between identically manufactured masks do not prevent two dies from becoming identical, so that one of them is provided to function for the other intended purpose. The term "different" as used herein means that the die does not meet the term "same" (even though the die is "almost the same") with the modulated electrical properties.

Two packages are considered "identical" in this specification if one of them can function for another intended purpose. The two packages are "internally" identical if they are identical except for the shape of the leads protruding from the package body. The package may be internally identical even if the contents of the cavity are different from each other. The two packages may be "almost" identical even if their contacts are different by the contacts or the two, and they are "similar" if almost all of the electrically operable contacts have the same general arrangement for their intended application. Do".

As used herein, the term package “interior” refers to the body of the package and the contents of the package cavity. This content generally includes internal contacts connected with the die contacts by " conduit construction ". As used herein, the term "conduit configuration" refers to the number of conduits located in a package, the choice of die and package internal contacts electrically coupled by the conduits, and the appropriate location of these contacts being defined within the die or package. It is a standard. Thus, a "bond map" containing the die and package description information required by the wire bonding machine is an example of a sufficiently complete "conduit configuration" even if the description information for the loop height is lacking.

As used herein, the term "interface" refers to a set given with a structural member comprising a contact in each of the two entries and two entries outside the conductor and the middle conductor coupled to the contacts. As used herein, die interfaces each include at least two IC packages. As used herein, the chip interface may not include anything other than a soldering pattern.

1 shows a prior art package memory chip 616 and path layer 606. Package chip 616 includes eighteen goal wing leads 699, each comprising a bottom contact 691 positioned relative to corresponding inner contact 696 on path layer 606. Path layer 606 insulates inner contacts 696 from each other and provides an inner conductive path to several outer contacts 697. Each outer contact 697 is also electrically connected to a bottom contact 698 on the bottom of the path layer 606. Most of the outer contact 697 is connected via an "ordinary" vertical conductor 693, while some of the outer contact 697 is connected via an "offset" vertical conductor 694.

2 shows a known lamination apparatus 600 mounted to a substrate 605 as disclosed in US Pat. No. 5,612,570. The device 600 is formed of several identical path layers 606, 607, 608 and has corresponding package chips 616, 617, 618, respectively. Each of the outer contacts 697 of the bottom path layer 606 is directly connected to a corresponding bottom contact 698 on the bottom of the second path layer 607. Similarly, bottom contact 698 on the bottom of bottom path layer 606 is directly connected with a contact (not shown) on substrate 605.

By a known surface mount mounting interface configuration combining the offset conductor 694 and the vertical conductor 693, each of the package chips 616, 617, 618 is " individual signal coupling ", ie, the stacking device 600. Has one or more signal paths that are electrically isolated from other package chips in the array. This allows each of the package chips 606, 607, 608 to be addressed alone, even if the same package chip is used.

Figure 3 shows an enlarged form of Seagate's Cheetah 18LP disc drive sold before recording. As will be described below, such an electromechanical system requires a stacked IC device that follows its formation factor description. In short, the disk drive 10 includes a housing base 42 and a top cover 490 and engages the gasket 495 to form a sealed housing that maintains a cleaning environment inside the disk drive 10. Multiple disks 46 are mounted for rotation on the spindle motor hub 44. Multiple transducer heads 60 are mounted to the actuator body 56. The actuator body 56 is below the voice coil motor (VCM) comprising the voice coil 54 and the magnet 50 to controllably move the head 60 along the arcuate path 62 to the desired track 48. Is adjusted for the pivoting operation. The signals used to control the VCM and the head 60 are passed to and from the electrical circuits on the controller board 500 via the flexible circuit 64 and the connector 68. As shown, the controller board 500 includes a fiber channel interface 550, a serial port connector 560, and a spindle connector 570. In fact, the board 500 is very complicated.

4 shows a controller board 501 modulated from the board 500 of FIG. 3 by replacement of the stacking devices 580, 581 of the present invention. All of the top outer contacts of one lamination device 580 are fully exposed to air, which forms a space layer segment 584 under the outer leads and the visually marked leads. All of the top outer contacts of another lamination device 581 are completely coated with a protective (solid) dielectric 585, such as a deposition epoxy. All chips shown are preferably coupled to the board 501 by a single reflow operation.

5 is a cross-sectional view of various manufacturing steps of the lamination apparatus of the present invention. The spacer layer 880, such as a printed circuit board, is provided with solder paste in the contacts 891, 892 on its opposite surface. After preparing the layer, at least one chip 270 is positioned on the working surface 83. An assembly component comprising a space layer 880 is positioned in contact with the leads of each chip 270. At least one chip layer 170 is provided such that a portion of the contact is directly connected with a contact 892 on the space layer 880 with solder 87. Electrical probes 86 are used to test the functional stacking devices 580, 581. Clamping surfaces 88 are used to secure the device while separating it into individual units (unified) using a cutting device 79 such as a luther. The unitized device is removed from the assembly fixtures 83, 88. These may be connected to the substrate 503 having the inner conductor 568 by soldering at the contacts 592. In one embodiment, at least one bottom contact of the stacking device is coupled to only the dielectric region of the substrate and all of the top contacts of the top chip 270 in the stack are coated with a dielectric 585. Optionally, at least one substrate contact 592 coupled to the stacking device 580 is electrically insulated from any inner conductor 568 of the substrate.

FIG. 6 illustrates in detail the method of the present invention compatible with FIG. The printed circuit board (s) are inspected (1220), prepared (1225) and screen printed (1230) with solder paste in a known manner. Chips are selected and placed first on reflow pallets 1245, 1250 (1240), and additional board (s) and chips are located on reflow pallets 1245, 1250. The top cover of the reflow pallet is positioned (1255) and the reflow is performed in a known manner (1265). An electrical test of the device is performed (1270). In a preferred embodiment, step 1270 includes modulating the electrical properties of each, or both, or one of the chips, particularly aligned perpendicular to the stack. The steps are characterized (1280) and inspected (1285) and any necessary rework is performed before mounting on the substrate (1290).

7 is an enlarged view of the stacking apparatus 582 of the present invention, and is inclined upwardly so that the bottom surfaces 171 and 271 of the chips 180 and 280 are exposed in the stacking portion. The bottom chip 180 is a package device including eighteen conductors 101-118 having valley-wing leads projecting downward and upward. As shown, each of conductors 101-118 may be configured for direct contact with a top contact 192 and a first PCB (not shown) configured for direct contact with two component spatial layers 880. The bottommost contact 191.

The heater sink 780 is provided in capital letter "I" shape in two narrow segments connected by vertical segments. Optionally, it is in direct contact with the bottom chip 180 and bonded with a high temperature silicone adhesive. Although heater sinks are generally used only in large chips, heater sinks 780 are shown as small chips 180 and 280 as opposed to typical for the sake of illustration. The interface 199 includes the illustrated spatial layer 880 and the offset conductor path layer 980. In accordance with a preferred embodiment of the present invention, a stack having an L chip layer only requires an interface (L-1) for the proper signal path. Space layer 880 and path layer 980 are preferably secured to each other prior to assembly to chips 180 and 280. Most of the conductors 801-818, 901-918 of these layers 880, 890 include contacts configured for direct connection with contacts in other layers, so that the fixation is properly performed using solder paste.

As shown, the trace 168 on the bottom 971 of the path layer 980 connects the conductor 901 and the conductor 913 so that the four package conductors 101, 113, 201, 213 are connected. . If the chips 180, 280 of the stack are the same, these traces may not achieve individual signal coupling with the package conductors 101, 113, 201, 213. Nevertheless, the trace on the path layer with the conductors adjusted for coupling with the conductors on two or more sides of the stacked IC package 180 may be a two-part spatial layer 880 or a single frame 606 of FIG. 1. Provide a new latitude above). That is, the illustrated path layer 980 is not explicitly added to the footprint of the stacking device 582 even if the heat sink 780 is omitted.

As shown, the path board 980 is another shape that provides separate signal coupling. Unlike other conductors 901-911, 913-918 that include contacts of the path layer 980, the conductor 912, as shown, only contacts the contacts 991, 992 over one of its surfaces 971, 972. Include. Preferred embodiments of the invention feature a path layer featuring at least one offset conductor 169 constructed by methods known to those skilled in the art. In a preferred embodiment of the present invention, the conductors 114 and 214 are not connected (ie, package contacts comprising contacts not internally connected to the chip's internal circuits) and the chips 180 and 280 are identical. Thus, as shown, the conductor 112 is electrically connected to exactly one chip 180 and the conductor 114 is electrically connected to exactly one chip 280 to facilitate the implementation of individual signal combinations.

Also in connection with FIG. 7, the top surface of the heat sink 780 is preferably coated with a dielectric coating to prevent electrical coupling with the conductor 168 on the path layer 980 between the chips 160, 260. Materials usable for the heat sink 780 are known, but most are electrically conductive. Optionally, a space layer 880 thick enough to allow clearance below the path layer 980 (shown) may be used in connection with the heat sink 780 attached away from the path layer 980.

8 is a sectional view of the lamination device 582 of FIG. 7. The conductor 168 on the bottom of the path board 980 is electrically insulated from the heat sink 780 by the dielectric 195 between the board 980 and the heat sink. When the heat sink is attached to the bottom chip 180, the dielectric 195 may be an air gap. Otherwise, dielectric 195 may include a coating on the surface of heat sink or board 980. As shown, in a planar configuration with an externally identical package, the spatial segment 584 preferably has a thickness 881 thicker than the thickness of one chip 180 plus one heat sink 780. As shown in FIGS. 7 and 8, each spatial segment 584 has no horizontal trace path and has a large thickness 881 such as approximately a width 882.

In another embodiment, as shown in FIG. 8, the body of the bottommost chip 180 extends below the bottom of the lid 179. The first board can accommodate such a chip by providing a recess large enough to accommodate the body of the bottommost chip, which is desirable for example to accommodate flat package leads (see FIG. 11).

9 shows a cross-sectional view of a stacking device 583 that includes a top chip 280 with a package lead 279 longer than the lead 179 of the bottom chip 180. The conductors of the top package 280 include leads 279 having a top side 268 and a bottom side 267, respectively. As shown, the bottom side surface of each lead is the bottom outer contact 191, 291. Deformation of the form of the outer lead is known. Instead of the path or space layer in the form of FIG. 9, the bottom outer contact 291 of the long lead 279 is directly connected with the top outer contact 192 of the conductor contact of the bottom package 180. Large heat sink 780 is shown to accommodate large chips (and / or leads on four sides) with high current. Internally different lead shapes for the same package are optionally used in connection with the embodiment shown in FIGS. 5-8 and 12-20.

FIG. 10 shows a stacked form with three important properties different from that shown in FIG. 7. First, the interface 199 includes a single component path layer 980 that provides a space between each bottom conductor 101-118 and the individual top conductors 201-218. The path layer includes at least one recess 994 in the protruding at least one chip 180. The recess 994 may be shaped as a placement tube for the chip 180 with terminals on four sides. Secondly, each of the chip layers 180, 280 includes a plurality of chips. This is a useful space saving feature that is incompatible with some chip stacking systems. Third, the described path layer 980 provides traces 968 that extend out of the footprint of any stacked chip 180, 280 with a minimum increase in stack device footprint size (ie, about 5% or less). It includes a wide portion 996 that is wide enough to allow. As shown, the wide portion 996 allows at least one trace 968 to be repositioned outside of layer 980 (ie, outside the footprint of the nearest chip). In turn, this allows the top surface trace 968 to be used instead of each bottom surface trace 168 of FIG. 7, eliminating the need for insulators between the path layer 980 and the heat sink 780. With minimal variation, one skilled in the art can arbitrarily adjust these three characteristics to use the embodiments shown in FIGS. 5-7 or 10-13 described herein.

11 shows a portion of a stacking device comprising two interfaces 199 and 299 and three chips 180, 280, and 380, respectively, comprising a frame-shaped space layer 880 completely filled with vertical conductors (not shown). It is an enlarged view. The spatial layer 880 of the top interface includes an assembly tab 888 with a tapered end 889. The space layer comprises a number of individual layers 880 joined at their tapered ends, and is preferably made in a sheet having a reflow paste screen printed on each contact prior to the lamination assembly. A number of bottom chips 180 may be arranged into the grid by robotic assembly devices in each of the recesses 82 of the work surface, such as the reflow pallet 81. During reflow, the stack is preferably fixed and compressed by downward force applied by flange plungers 85 or the like. After reflow, the stacking device can be unified by blocking the spacer layer at their tapered ends.

12 shows a detailed view of a lamination apparatus mounted on a first board 502 in accordance with the present invention. In this embodiment, the IC dies are packaged in "leadless" chip carrier (LCC) packages 160 and 260, with their conductors 101-158, 182, 191 and 192 of the body of the package. It is so called because it does not protrude significantly outside the basic shape. In FIG. 12, the bottom LCC package 160 is inclined downward so that their upper side 172 is visible. The high, stacked LCC package 1160 is inclined upwardly such that its bottom side 1171 appears to be half of the 58 outer lines 198 ("outer" lines in the half package shown schematically).

In FIG. 12, interface 199 may simply include solder between conductor 101 and conductor 1101 and between each of the 57 matched pairs of conductors in the two bottom packages. Optionally, it may include a space layer and / or a heat sink as shown in FIG. 7. Optionally, the present invention includes a second stacked package 2160 identical to the bottommost packages 160, 161 with 58 opening contacts on its top surface 2172. The bottom LCC package 160 is connected by a plurality of internal lines 197 with each top contact 192 on the top surface 172 of the package and each bottom contact 191 on the bottom surface 171 of the package. It includes a die having an internal circuit. Each of these inner lines 197 includes an outer contact 181 of the first die and an inner contact 182 of the package, as well as two outer contacts 191 and 192 of the package. At least half of the lowermost outer contacts 191 are each directly connected with corresponding contacts 592 on the first board 502. However, as will be described below, the lowermost outer contact 191 of the small number of bottom LCCs is not selectively connected, as is physically connected with the dielectric 590 on the first board 502. An embodiment is shown below in conductors 130, 146, 150. As shown in the conductors 146 and 1146 of the present invention, the laminated structure of the present invention is selectively chosen between chip conductors having a very low capacitance load due to the electrical isolation from the inside of the board 502 on the mounted lamination device. It is characterized by more than one combination.

Preferably, each package 160, 1160 includes at least one unconnected contact 189, 1189 outside the internal circuits 100, 1100 of the die inside the package. Typically, as shown explicitly for package 1160, package conductor 1134 or internal circuit lines 1186 are each electrically connected to one side of unconnected contact 1149, respectively. Unconnected contacts 189 and 1189 may be part of a die (bonding pad with no bond wire attached) or part of the package (bond finger with no bond wire attached). As described below, the proper use of unconnected contacts 189 allows for enhanced performance and ease of manufacture that were not previously available.

12 shows a conductor capable of connecting various contacts 181, 182, and 189 to the interior of the package 160, as well as contacts 189 that are not electrically connected to the external contacts 191 and 192 or the internal circuit 100. Not shown. Unconnected contacts 189 and 1189 and their attached conductors are generally referred to as "no-connect".

Although some of the die contacts 181 may be unconnected contacts 189 and 289, the majority of the outer die contacts 181 in each of the packages 160 may be corresponding internal circuit 100 and corresponding package contacts 182. Is typically electrically connected to. In some conditions, it is desirable to have one or more internal lines 1185 electrically connected to two or more package contacts 1116 and 1117.

13 shows a Venn diagram for investigating the package size useful for a given set of chips being stacked, especially for less similar chips. Circles 160 and 1160 each represent a package and each "x" in the circle represents a conductor extending into the corresponding package. Thus region 21 includes conductors extending into both packages 160, 1160. Fourteen internally connected package conductors 101, 108, 111, 114, 117, 118, 119, 125, 130, 133, 138, 146, 150, 152 are respectively connected with corresponding internally connected package conductors in FIG. 12. Fourteen bonds are shown as "x" in the intersection region 21 in recalling, respectively. Similarly, thirteen other connectors are connected to the chip 160 but the chip 1160 marked "x" in the region 11 is not connected. 12 or 13, it can be seen that all 27 package conductors of the chip 160 are internally connected (with the internal circuit 100 inside the chip 160). As described above, some aspects of the invention relate to internal signal coupling that changes the conductivity of early chips 160, 1160 with blank " exclusive " regions 11, 22. FIG.

FIG. 14 shows a Venn diagram similar to FIG. 13 adjusted to combine two or more layers. As shown, FIG. 14 is modified to show how a stack of three dissimilar chips 160, 1160, 2160 can be configured in an almost non-parallel configuration consistent with FIG. As shown, three circles 2000 represent the upper chip 2160. Ten conductors in region 44 are shared with all three chips, and region 21 shared by only the bottommost chips 160, 1160 has only four "composite" conductors. In general, each circle 160, 1160, 2000 represents a die or other layer having coplanar contacts optionally provided, such as substrate 502.

FIG. 15 is a stacking device of the present invention somewhat similar to FIG. 12, illustrating a method of distinguishing chips. Techniques for examining the post-production induction chip differences disclosed herein are known. With the help of this technique, the skilled person only needs to make design choices to provide the appropriate internal circuitry to respond to these differences. IC chip 100 includes storage cell 190, which may be any known nonvolatile storage device such as a laser modulating member. More preferably, cell 190 includes an EEPROM or other read-only memory cell or fusible link. One or more light sensing components on the IC die may also be used with the clear IC package cover.

As shown, die 1100 and package 1160 are nearly identical to die 100, 160, respectively. In one embodiment, the described deposition apparatus may function because the storage cells 190 and 1190 are configured differently. In another embodiment, the unconnected contacts 189 and 1189 on one chip are missing on the different chips in the stack.

FIG. 16 shows the configuration of contacts 189 and 289 which are not connected for individual signal coupling with each chip of a two-layer stacking device (ie, a device having two layers of chips). As described above, this is almost identical to FIG. 15, but represents a set of external contacts 191, 192 rearward from the side 163 of the package 160, 260. Integrated circuit die 170 with internal circuit 100 is mounted inside bottom IC package 160. Within the bottom package 160, each of the inner lines 197 is connected between the outer contacts 191, 192 and the inner contacts 182 of the package 160, the contacts 181 on the bonds, bond wires, and dies 170. And a portion for inducing signal traces to the internal circuit 100. In FIG. 16 it can be seen that the contacts 189 that are not connected within the bottom package 160 are electrically connected to the internal circuit 100 or otherwise separated from any external contacts 191 and 192 by a large dielectric gap. Can be.

Nearly identical integrated circuit die 270 is similarly mounted within a nearly identical stacked IC package 260, but connected with different board wire shapes. In particular, unconnected contacts 289 on top die 270 are not directly connected to the top of unconnected contacts 189 of the same bottom die. Preferably, the two dies 170, 270 are assembled in the same and identical stacked packages 160, 260, one die corresponding to the first and the first corresponding to the same continuous contact 281 on another die. With a continuous contact 181, one package 160 has a corresponding inner contact of conductor 242 connected to a second contact of a second die. In other words, each of the same dies 170, 270 preferably has unconnected contacts 189, 289 offset (ie, not corresponding) from the unconnected contacts 289, 189 of the other chip. In a more preferred embodiment, the continuous contacts 181, 182 of two identical dies 170, 270 are connected to each other through inverters 541, 542 in the internal circuit of each die.

FIG. 17 is similar to FIG. 15 as described above, and illustrates another inventive configuration of contacts 189 and 289 that are not connected to distinguish chips in a stacking device. In FIG. 17, the chip interface 199 includes a space layer 880, which allows for air flow and / or heat sink structures between the packages 160, 260. The disclosed spatial layer 880 includes vertical conductors 893 that connect each of the bottom contacts 891 and the top contacts 892. At least a portion of the bottom contact 291 of the top package 260 is directly connected with the top contact 892 of the space layer 880. At least one is not connected through direct connection with the dielectric region 890 of the spacer 880. As shown, the bottom contact 191 of at least some package conductors 110, 112 is similarly configured for direct connection with the first board 502.

FIG. 17 shows blown fusible links 186, 187, 286, and 287 so that each die 170, 270 has a different configuration of fused links. In a preferred embodiment of the invention, all identically manufactured IC dies are packaged and equally electrically connected prior to blowing the link. This reduces the deformation of the parts that must be maintained in the inventory and facilitates manufacturing by delaying the time that the difference between the top and bottom package devices is created. If a link is used in a redundant manner, the two illustrated links may be blown in four arbitrary forms. Each die has at least one configuration conductor, such as the fusible links 186 and 286 of FIG. At least log ₂ L constituent conductors are used, where L is the number of layers in the stack. In FIG. 17, some package terminals 112, 212 include redundant links 187, 287 connected to them, each signal coupling being only log ₂ 2 = 1 on each die for a two layer stack. It can be considered to be achieved only with fusible links 186 and 286. Thus, one embodiment of the present invention omits extra links 187 and 287 on each die. However, since the same dies 170, 270 can be packaged and maintained in the inventory without determination whether or not to be used in a stack of two, three or four layers until the stacking device is assembled, such redundant links 187, 287).

FIG. 18 shows a flowchart of the method of the present invention compatible with FIG. 17. The stacked chips are stacked with nonvolatile component elements. This may be a cell 190 as described above with reference to FIG. 15, a fusible link 186 as described above with reference to FIG. 17, or a similar item of known technology. Preferably, the selected element is of a type that is easily modulated without mechanical action such as bending, soldering, or cutting. Many non-volatile elements responsive to the solid state programming method can be used as already described.

Internal chip characteristics are modulated (1830) and the stacking device is assembled (1840) as described above. In one embodiment, the package conductor has side contacts (as shown in FIGS. 7-12) in a stack of three or more layers of approximately identical chips.

Referring again to FIG. 17, programming conductors 111, 211 for each package 160, 260 are shown. Preferred embodiments of the present invention provide side contacts for programming conductors (the construction of such side contacts is known in the art). Side contacts may be used in place of top or bottom contacts to provide access to the programming lines at a time on only one package, or a space layer having a dielectric region 890 as in FIG. 17 may be used. For stacking a plurality of chip layers that are nearly identical, the modulating step 1830 of FIG. 18 preferably includes identifying chips in a set that are each vertically aligned using such a programming conductor.

In another embodiment, three identical chips are stacked in a space layer exactly as in FIG. 17 (the second spacer layer and the third stacked chip are not shown). The stacking device of this embodiment is preferably stacked (assembled) 1840 before the internal chip characteristics are modulated 1830. Preferably, this eliminates the need for tracking of the chip until after the stack is assembled. Bottom die 170 provides a large current between conductors 110 and 111 and is distinguished from other dies 270 and 370 by blowing link 186. Top die 370 is distinguished from other dies 170 and 270 by blowing a link connected to package conductor 312. After at least some chip differentiation 1830 and assembly 1840, the stacking device is likely to be installed on the substrate (1850).

FIG. 19 shows another flow chart of the present invention compatible with FIGS. 15, 16 and 20. FIG. The die is not distinguished and is mounted on the package (1920) using some general principles. A first conduit configuration is used (1930) to install the conduit into the first package to engage the required contacts of the first die. In order to install the conduit into the second package (1940), a second conduit configuration different from the first conduit configuration is used to distinguish the chips. After such installation, IC chips are stacked (1950).

FIG. 20 shows, in the three-layer stack, several unconnected contacts 189, 289, 389 in the inventive configuration compatible with FIG. 19, as described above. Integrated circuit dies 170, 270, and 370 are packaged within respective integrated circuit packages 160, 260, and 360. The top outer contacts 392 of the top chip 380 are both physically separated from each other by the dielectric gap 380 and the complete dielectric cover 395 such as the air or deposition coating 585 as shown in FIGS. 4 and 5. Are separated. The top outer contacts 192, 292 of the bottom chip 190, 280 are likewise separated by dielectric gaps 196, 296, but with outer lines 198, 298 displacing at least a portion of any corresponding dielectric covering. Have

All steps and structures described above will be apparent to those skilled in the art and may practice the invention without undue experimentation. While the various features and advantages of the various embodiments of the invention have been described in the foregoing description, along with a detailed description of the structure of the invention and the functionality of the various embodiments, these are merely exemplary. In the detailed description, modifications may be made in the arrangement and structure of parts, particularly within the principles of the invention as broadly indicated by the broad terms of the terms describing the appended embodiments. For example, certain elements may be modified in accordance with the particular application for the system without departing from the scope and spirit of the invention, while maintaining the same functionality. Further, while the preferred embodiments described herein relate primarily to increasing the occupancy density of PCBs and simplifying the manufacture of components for lamination devices, those skilled in the art will appreciate that the description of the invention may be modified without departing from the spirit and scope of the invention. It will be appreciated that it can be applied to improve performance.

To summarize the present invention, chip (s) layers 280 and 380 are positioned directly on the floors 81, 82, 83 of the assembly fixture. Space and / or path layers 584, 880 are located directly on the contacts 291, 292 of the chip (s), and additional chip (s) layers 180, 280 are disposed on the layers 584, 880. It is located right away. After bonding the layers by solder reflow 1265, the lamination device 580 constructed in accordance with the method is optionally tested 1270 before being removed from the fixture.

Another method includes mounting dies 170, 270 (also may be similar or identical) in packages 160, 260 (which may be similar or identical). The chips 180 and 280 constructed in this manner can be constructed by installing different configurations of conduits (e.g., bond wires 183 and non-connections 189) (1940) or otherwise modulating their electrical properties within each other. 1830 (by link 186 blowing or cell 190 programming). The installation steps 1930 and 1940 can be easily distinguished from one non-connected portion 189 horizontally offset from the other unconnected portion 289.

In another method, the substrate 503 is configured with a plurality of conductive contacts 592 and a plurality of internal traces 568. Stacking devices 580, 582 are assembled into a plurality of nearly coplanar conductive contacts 191. A portion of the device contact 191 is physically connected to a contact 592 on the substrate, but at least one of the device contacts 191 provides a dielectric region 590 coplanar with the substrate contact 592 and the device contact 191 By an alignment with at least one of them), it is electrically insulated from all internal traces 568.

Apparatus having a structure constructed or described by each of these methods is an embodiment of the invention. Such devices include top and bottom rectangular packages 160, 260, each comprising a goal wing lead projecting outwardly and downwardly from at least two sides. Means for physically connecting the leads are provided as described above and optionally include two elongated printed circuit board (PCB) segments 584 between the leads of the top and bottom packages. Means for electrically connecting the leads have been described as well, and optionally include one or more horizontal circuit traces in the PCB segment 584.

Claims (10)

A method of laminating chips by placing at least two chip layers, each containing at least one chip, into an assembly fixture comprising a floor, (a) placing the first chip layer directly on the floor; (b) positioning a first spacer layer on the first chip layer; (c) positioning at least one additional chip layer over said spacer layer; (d) combining the layers with each other; And (e) removing the bonding layer comprising at least one stacking device from the assembly fixture. A lamination apparatus manufactured by the method of claim 1. A method of stacking similar packaged first and second dies, the method comprising: (a) mounting at least one die into the first package; (b) installing a plurality of electrical conduits into the first package of a first conduit configuration; (c) mounting at least one second die into a second package; (d) installing a plurality of electrical conduits into the second package in a second conduit configuration different from the first configuration; And (e) electrically coupling the first package and the second package to form a lamination device. 4. The method of claim 3, wherein only one of the first dies is stacked with only one of the second dies, the first and second dies being substantially identical, each die being based on an internal circuit and the circuits. A nominal set of contact positions, wherein the first set of nominal positions comprises a second set of nominal positions; Each package includes an interior, each interior and each die comprising a plurality of contacts; Each conduit is bonded wire bonded with one of the inner contacts and one of the die contacts; Each of the installation steps (b) and (d) comprises directly coupling a plurality of bond wires to one of the die contacts and one of the inner contacts, respectively; The installation step (b) defines a first conduit configuration and results in a first set of contacts that are electrically coupled; The installation step (d) defines a second conduit configuration and results in a second set of contacts that are electrically coupled. It is manufactured by the method of Claim 3. The lamination apparatus characterized by the above-mentioned. A method of manufacturing a stacked device comprising at least a first integrated circuit (IC) die and a second IC die, the method comprising: (a) mounting a first IC chip with a first die in a first package; (b) mounting a second IC chip with a second die in a second package, the second die being the same as the first die, the second package being internally identical to the first package, and ; (c) sealing the package; (d) modulating electrical characteristics of at least one of the chips; (e) electrically coupling the second chip and the first chip to form a lamination device. 7. The method of claim 6, wherein modulating (d) comprises blowing at least one or more fusible links present on at least one die. A surface-mount integrated circuit device for joining a substrate, comprising: A top package package and a bottom package; A combination of an interface joining the top of the plurality of leads of the bottom package and the bottom of the plurality of leads of the top package, Said top package and bottom package each having an external configuration including an IC die and comprising a plurality of protruding leads, each lead having a top and a bottom portion, and the top of each lead of the top package is covered by an insulator, Bottom Package Part of the bottom surface mount integrated circuit device, characterized in that for coupling with the substrate. A lamination apparatus for joining substrates, At least two integrated circuit (IC) chips comprising surface mount packages; And And lamination means for mechanically and electrically coupling the IC chips to each other. 10. A disk driver comprising the electrical system of claim 9, wherein the stacking means is a set of solder contacts, wherein at least one of the surface mount packages comprises a substantially coplanar package contact, and further comprising a substrate having a contact and a dielectric region, a portion of the substrate contact. And at least one of a portion of a package contact coupled and a package contact in contact with the dielectric region.