KR20010046575A - method for manufacturing capacitors of semiconductor memory devices - Google Patents

Abstract

PURPOSE: A method for fabricating a capacitor of a semiconductor memory device is provided to improve reliability of a storage electrode by preventing the storage electrode from being damaged during formation of hemispherical grains. CONSTITUTION: In the method, a buried contact hole is formed in the first interlayer dielectric layer(20) on a substrate(10) and then filled with a conductive layer(30) for a buried contact. Next, the second interlayer dielectric layer having a window exposing the conductive layer(30) is formed on the first interlayer dielectric layer(20). Thereafter, the cylindrical storage electrode is formed in the window of the second interlayer dielectric layer. In particular, the storage electrode is formed from several conductive layers having an intermediate layer(53) with relatively higher doping concentration. Therefore, when the hemispherical grains(57) are formed on a surface of the storage electrode, the storage electrode is not damaged due to the intermediate layer(53). After that, a dielectric layer(70) and a conductive layer(80) for a plate electrode are formed thereon.

Description

Method for manufacturing capacitors of semiconductor memory devices

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a method of manufacturing a capacitor of a semiconductor memory device in which hemispherical grains (HSG) are formed on a sidewall and an outer surface of a cylindrical storage electrode to prevent the formation of through holes in the sidewall. It is about.

In general, the area of the memory cell has been reduced as the density of the memory cell is increased for higher integration of semiconductor memory devices such as DRAM. The reduction of the area of the memory cell results in the reduction of the area of the capacitor of the memory cell and furthermore, the reduction of the capacitance of the capacitor. Therefore, for high integration of DRAM, it is necessary to increase the capacitance of the capacitor as well as increase the density of the memory cell. Since the capacitance increase of the capacitor serves to improve the readability of the memory cell and to reduce the soft error rate, much research has been made on the increase of the capacitance of the capacitor. Most of them relate to the structure of the storage electrode constituting the capacitor of the memory cell, including the pin structure electrode of Fujitsu, the box structure electrode of Toshiba, and the cylindrical structure of Mitsubishi. ) Structure electrodes and the like have become mainstream. Attempts to increase the capacitance of capacitors by improving the structure of storage electrodes have been skeptical about their manufacturability due to problems such as limitations of design rules and increased error rates due to complex processes. Therefore, there is an urgent need for a method of manufacturing a capacitor of a new memory cell to overcome these problems.

Recently, memory cells having a capacitor over bitline (COB) structure in which capacitors are formed at higher positions than bit lines have attracted attention as memory cells suitable for 64 mega DRAM or 256 mega DRAM. In addition, a capacitor having a double HSG one cylinder system (DHOCS) structure in which hemispherical particles are formed in the sidewalls and the outer surface of the storage electrode has been introduced to increase the surface area without increasing the size of the storage electrode.

However, in the case of the conventional capacitor, as the design rule of the highly integrated memory device is reduced to 2 μm or less, the sidewall of the storage electrode is formed to have a thin thickness of 500 μm or less. Moreover, the sidewalls of the storage electrodes consist of a single layer of polysilicon layer doped at the same concentration.

As a result, through-holes are easily formed in the sidewalls of the storage electrode when the hemispherical particles are formed in the sidewalls and the outer surface of the storage electrode. After the dielectric film and the plate electrode are formed in the storage electrode in this state in a subsequent process, the leakage current of the capacitor increases.

Accordingly, an object of the present invention is to provide a method of manufacturing a capacitor of a semiconductor memory device to prevent damage of the storage electrode when forming hemispherical particles on the sidewall of the storage electrode to improve the reliability of the storage electrode.

1 to 7 is a process chart showing a capacitor manufacturing method of a semiconductor memory device according to the present invention.

Capacitor manufacturing method of a semiconductor memory device according to the present invention for achieving the above object

Forming a first interlayer insulating film on the substrate, the first interlayer insulating film having a etch contact hole exposing a cell pad of the substrate;

Forming a conductive layer for immersion contact filled with the immersion contact hole to contact the cell pad and planarize the first interlayer insulating layer;

Forming a second interlayer insulating film on the first interlayer insulating film exposing the conductive layer for the memory contact and having an opening for forming a storage electrode;

Forming a cylindrical storage electrode having a multilayered stacked structure having different impurity concentrations on the second interlayer insulating film including the conductive contact conductive layer; And

And forming hemispherical particles on the outer surface of the storage electrode.

Preferably, the intermediate layer of the multilayer stack is doped at a higher concentration than the lower layer and the upper layer. The lower layer and the upper layer are doped at the same concentration.

Therefore, according to the present invention, since the intermediate layer of the storage electrode acts as a stopper doped at a higher concentration than the upper layer and the lower layer, a through hole is formed in the sidewall of the storage electrode when the intermediate layer forms hemispherical particles in the sidewall and the outer surface of the storage electrode. To reduce the leakage current of the capacitor.

Hereinafter, a method of manufacturing a capacitor of a semiconductor memory device according to the present invention will be described in detail with reference to the accompanying drawings.

1 to 7 are process charts showing a capacitor manufacturing method of a semiconductor memory device according to the present invention.

Referring to FIG. 1, first, for example, a field oxide film (not shown) is applied to a field region of a P-type substrate 10 in order to define an active region for a memory cell, or a shallow trench isolation (STI) process or a local oxidation (LOCOS) process. of silicon). Next, a MOS transistor is formed using a normal process. That is, a gate oxide film (not shown) is grown in the active region of the substrate 10 by a thermal oxidation process, a gate electrode (not shown) for a word line is formed in the gate oxide film of the active region for the gate electrode, and the gate N-type impurities such as phosphorus are implanted at low concentration into the active region of the transistor using the electrode as a mask, and spacers (not shown) of insulating films are formed on both side walls of the gate electrode, and the gate electrode and the spacer are used as masks. Phosphorus is implanted at a high concentration into the active region to form a source / drain (not shown). After formation of the source / drain is completed, an interlayer insulating film having an opening exposing the cell pad is formed on the resulting structure. Thereafter, a polysilicon layer for a cell pad is laminated on the interlayer insulating layer to a thickness thick enough to fill the openings, and is then subjected to an etch back process to planarize the interlayer insulating layer to form a cell pad electrically connected to the source. .

Subsequently, a first interlayer insulating film is stacked on the front surface of the substrate including the cell pad, for example, a first interlayer insulating film 20 made of BPSG material at a height for a buried contact conductive layer, and the cell pad is exposed by a photolithography process. Forming a contact hole of (20) and laminating a conductive contact layer 30, for example, a polysilicon layer, on the first interlayer insulating film 20 including the contact hole, to a thickness of 2000 kPa, and etching it. However, the pattern of the conductive contact conductive layer 30 is left only in the buried contact hole by the chemical mechanical polishing process. Accordingly, the surfaces of the first interlayer insulating film 20 and the conductive layer 30 are planarized.

Referring to FIG. 2, when the pattern of the conductive contact conductive layer 30 is formed, a nitride film (not shown) is formed on the first interlayer insulating layer 20 including the pattern of the conductive contact conductive layer 30. The second interlayer insulating film 40 is formed by laminating a thin layer, and depositing an oxide film on the film by a PE-TEOS process to a thick thickness of 13000 하고, and laminating an oxynitride film (not shown) by a thin film of 600 Å by the plasma process. . Here, the total thickness of the second interlayer insulating film 40 is set to a thickness corresponding to the height of the sidewall of the storage electrode to be formed in a subsequent process.

Next, a second area of the region for forming the opening of the second interlayer insulating film 40 overlapping the conductive contact layer 30 for etch contact by the photolithography process on the second interlayer insulating film 40 for forming the storage electrode. The oxynitride film and the oxide film of the interlayer insulating film 40 are etched until the nitride film below it is exposed. Subsequently, using the remaining oxynitride film and the oxide film as a mask, the exposed nitride film is etched until the conductive layer 30 below it is exposed.

Subsequently, a conductive layer 50 having a multilayer stack structure for the storage electrode is stacked on the second interlayer insulating film 40 including the exposed conductive contact layer 30 for uniform thickness. In more detail, the P-type impurity is deposited on the second interlayer insulating film 40 including the conductive contact conductive layer 30 by laminating a polysilicon layer, which is the lower layer 51 of the conductive layer 50, to a thickness of 250 GPa. to 0.8X10 ²² atoms / cm ³ and the high-concentration doped with the above intermediate layer 53, while the laminating polycrystalline silicon layer to a thickness of 150Å to high P-type impurity concentration than the lower layer (51), 6.6X10 ²² atoms / cm ³ P-type impurities are doped at a high concentration of 0.8 × 10 ²² atoms / cm ³ while stacking the polysilicon layer, which is the upper layer 55, on the intermediate layer 53 to a thickness of 250 GPa.

Referring to FIG. 3, after lamination of the conductive layer 50 is completed, a thick thickness sufficient to sufficiently fill the recessed portion by the upper layer 55 located on the opening of the second interlayer insulating film 40, for example, 3500 kPa An insulating film 60 such as USG (undoped silicate glass) is deposited on the conductive layer 50 to a thickness of.

Referring to FIG. 4, after the stacking of the insulating film 60 is completed, the insulating film 60 and the conductive layer 50 positioned outside the forming portion of the storage electrode are treated by an etch back process or a chemical mechanical polishing process to completely remove the insulating film 60. . At this time, the insulating film 60 remains in the recessed portion defined by the upper layer 51.

Referring to FIG. 5, only the remaining insulating film 60 is removed to expose the upper layer 51, and the oxynitride film and the oxide film of the second interlayer insulating film 40 are etched until the underlying nitride film is exposed. Inner and outer surfaces of the sidewalls of the storage electrodes are exposed.

Referring to FIG. 6, the hemispherical particles 57 are simultaneously formed on the outer and inner sidewalls of the cylindrical storage electrode using a conventional process to complete the storage electrode. At this time, since the intermediate layer 53 is doped to a higher concentration than the upper, lower layers 55 and 51, it acts as a stopper to block the movement of the polysilicon. Therefore, no through holes are formed in the intermediate layer 53 while the hemispherical particles 57 are formed on the outer surface of the storage electrode.

Referring to FIG. 7, after the formation of the hemispherical particles 57 is completed, the dielectric film 70 having an oxide / nitride / oxide (O / N / O) structure is formed on the entire surface of the substrate including the storage electrode. The particles 57 are laminated to a thickness of 55 얇은 thin enough to completely cover the conductive layer 80, for example, a polysilicon layer, for the plate electrode, to complete the capacitor manufacturing process of the DHOCS structure.

Meanwhile, the present invention will be described based on two storage electrodes for convenience of description, but it is obvious that much more storage electrodes are formed than this.

As described above, according to the present invention, instead of stacking the polysilicon layer for the storage electrode having a thin thickness as a single layer of the same doping concentration, the intermediate layer between the lower layer and the upper layer is laminated in the multilayer structure having the highest concentration. .

Therefore, in the present invention, even if hemispherical particles are formed on the outer and sidewalls of the storage electrode, the intermediate layer acts as a stopper to block the movement of the polysilicon, thereby preventing the formation of through holes in the sidewall of the storage electrode and further reducing the leakage current of the capacitor. Decrease.

On the other hand, the present invention is not limited to the contents described in the drawings and detailed description, it is obvious to those skilled in the art that various modifications can be made without departing from the spirit of the invention. .

Claims (3)

Forming a first interlayer insulating film on the substrate, the first interlayer insulating film having a etch contact hole exposing a cell pad of the substrate; Forming a conductive layer for immersion contact filled with the immersion contact hole to contact the cell pad and planarize the first interlayer insulating layer; Forming a second interlayer insulating film on the first interlayer insulating film exposing the conductive layer for the memory contact and having an opening for forming a storage electrode; Forming a cylindrical storage electrode having a multilayered stacked structure having different impurity concentrations on the second interlayer insulating film including the conductive contact conductive layer; And And forming hemispherical particles on an outer surface of the sidewall of the storage electrode. 2. The method of claim 1, wherein the intermediate layer of the multilayer stack structure is doped at a higher concentration than the lower layer and the upper layer. 3. The method of claim 2, wherein the lower layer and the upper layer are doped at the same concentration.